[BuildOptions]
+ RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8 --thumb
+ RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
+ RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+
+ GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb \r
+ GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a\r
+ GCC:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7-a
+ GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
+\r
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
- RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8 --thumb
- RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
- RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
################################################################################
#
orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)\r
mcr p15, 0, r0, c1, c0, 2\r
mov r0, #0x40000000 // Set EN bit in FPEXC\r
- msr FPEXC,r0\r
- \r
+ mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly\r
\r
// Set CPU vectors to start of DRAM\r
LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r