This check-in fixed the following bugs:

1.	Pci22.h EFI_LEGACY_EXPANSION_ROM_HEADER definition error
(MdePkg\Include\IndustryStandard\Pci22.h; Tools\CCode\Source\Include\IndustryStandard\Pci22.h)
2.	SetVariable() with DataSize=0xffffffff will cause system hang
(EdkModulePkg\Universal\Variable\RuntimeDxe\Variable.c)
3.	Windows XP Pro & XP HOME Fails to Install from Retail CD
(EdkModulePkg\Bus\Pci\Pcibus\Dxe\PciResourceSupport.c)
4.	Pci22.h header file needs to add some recent type
(MdePkg\Include\IndustryStandard\Pci22.h; Tools\CCode\Source\Include\IndustryStandard\Pci22.h)
5.	Fix issues when ODD cannot boot from Sil0680 PCI-IDE controller
(EdkModulePkg\Bus\Pci\PciBus\Dxe\PciOptionromSupport.c;
EdkModulePkg\Bus\Pci\PciBus\Dxe\PciBus.msa;
EdkModulePkg\ EdkModulePkg.spd)

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@1900 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciBus.msa b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciBus.msa
index f6c017cd76fc27699ac1ead2f0aae9b8bc6d1506..4fe1dac4a9e6077e43fb1051c81482a036aeb2fa 100644 (file)
--- a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciBus.msa
+++ b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciBus.msa
@@ -6,14 +6,14 @@
     <GuidValue>93B80004-9FB3-11d4-9A3A-0090273FC14D</GuidValue>\r
     <Version>1.0</Version>\r
     <Abstract>Component description file for PciBus module.</Abstract>\r
     <GuidValue>93B80004-9FB3-11d4-9A3A-0090273FC14D</GuidValue>\r
     <Version>1.0</Version>\r
     <Abstract>Component description file for PciBus module.</Abstract>\r

-    <Description>PCI bus driver. This module will probe all PCI devices and allocate MMIO and IO\r
+    <Description>PCI bus driver. This module will probe all PCI devices and allocate MMIO and IO

        space for these devices.</Description>\r
     <Copyright>Copyright (c) 2006, Intel Corporation</Copyright>\r
        space for these devices.</Description>\r
     <Copyright>Copyright (c) 2006, Intel Corporation</Copyright>\r

-    <License>All rights reserved. This program and the accompanying materials\r
-      are licensed and made available under the terms and conditions of the BSD License\r
-      which accompanies this distribution.  The full text of the license may be found at\r
-      http://opensource.org/licenses/bsd-license.php\r
-      THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+    <License>All rights reserved. This program and the accompanying materials
+      are licensed and made available under the terms and conditions of the BSD License
+      which accompanies this distribution.  The full text of the license may be found at
+      http://opensource.org/licenses/bsd-license.php
+      THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,

       WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>\r
     <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION   0x00000052</Specification>\r
   </MsaHeader>\r
       WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.</License>\r
     <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION   0x00000052</Specification>\r
   </MsaHeader>\r


@@ -56,6 +56,9 @@
     <LibraryClass Usage="ALWAYS_CONSUMED">\r
       <Keyword>PeCoffGetEntryPointLib</Keyword>\r
     </LibraryClass>\r
     <LibraryClass Usage="ALWAYS_CONSUMED">\r
       <Keyword>PeCoffGetEntryPointLib</Keyword>\r
     </LibraryClass>\r

+    <LibraryClass Usage="ALWAYS_CONSUMED">\r
+      <Keyword>PcdLib</Keyword>\r
+    </LibraryClass>\r

   </LibraryClassDefinitions>\r
   <SourceFiles>\r
     <Filename>PciBus.h</Filename>\r
   </LibraryClassDefinitions>\r
   <SourceFiles>\r
     <Filename>PciBus.h</Filename>\r


@@ -160,4 +163,16 @@
       <ComponentName>gPciBusComponentName</ComponentName>\r
     </Extern>\r
   </Externs>\r
       <ComponentName>gPciBusComponentName</ComponentName>\r
     </Extern>\r
   </Externs>\r

+  <PcdCoded>\r
+    <PcdEntry PcdItemType="FEATURE_FLAG" Usage="ALWAYS_CONSUMED">\r
+      <C_Name>PcdPciIsaEnable</C_Name>\r
+      <TokenSpaceGuidCName>gEfiGenericPlatformTokenSpaceGuid</TokenSpaceGuidCName>\r
+      <HelpText>Whether ISA decoding is enabled on this platform so we should avoid those aliased resources</HelpText>\r
+    </PcdEntry>\r
+    <PcdEntry PcdItemType="FEATURE_FLAG" Usage="ALWAYS_CONSUMED">\r
+      <C_Name>PcdPciVgaEnable</C_Name>\r
+      <TokenSpaceGuidCName>gEfiGenericPlatformTokenSpaceGuid</TokenSpaceGuidCName>\r
+      <HelpText>Whether VGA decoding is enabled on this platform so we should avoid those aliased resources</HelpText>\r
+    </PcdEntry>\r
+  </PcdCoded>\r

 </ModuleSurfaceArea>
\ No newline at end of file
 </ModuleSurfaceArea>
\ No newline at end of file

diff --git a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciResourceSupport.c b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciResourceSupport.c
index 8919b422a7474c5d5b8d509da11a6d7139ab7901..58dbc9fd4c3f0cd3c3bc90dd749d05b8cc9d8d98 100644 (file)
--- a/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciResourceSupport.c
+++ b/EdkModulePkg/Bus/Pci/PciBus/Dxe/PciResourceSupport.c
@@ -241,11 +241,24 @@ Returns:
   LIST_ENTRY        *CurrentLink;\r
   PCI_RESOURCE_NODE *Node;\r
   UINT64            offset;\r
   LIST_ENTRY        *CurrentLink;\r
   PCI_RESOURCE_NODE *Node;\r
   UINT64            offset;\r

+  BOOLEAN           IsaEnable;\r
+  BOOLEAN           VGAEnable;\r

 \r
   //\r
   // Always assume there is ISA device and VGA device on the platform\r
   // will be customized later\r
   //\r
 \r
   //\r
   // Always assume there is ISA device and VGA device on the platform\r
   // will be customized later\r
   //\r

+  IsaEnable = FALSE;\r
+  VGAEnable = FALSE;\r
+\r
+  if (FeaturePcdGet (PcdPciIsaEnable)){\r
+    IsaEnable = TRUE;\r
+  }\r
+\r
+  if (FeaturePcdGet (PcdPciVgaEnable)){\r
+    VGAEnable = TRUE;\r
+  }\r
+\r

   Aperture = 0;\r
 \r
   if (!Bridge) {\r
   Aperture = 0;\r
 \r
   if (!Bridge) {\r


@@ -278,6 +291,34 @@ Returns:
     // become too limited to meet the requirement of most of devices.\r
     //\r
 \r
     // become too limited to meet the requirement of most of devices.\r
     //\r
 \r

+    if (IsaEnable || VGAEnable) {\r
+      if (!IS_PCI_BRIDGE (&(Node->PciDev->Pci)) && !IS_CARDBUS_BRIDGE (&(Node->PciDev->Pci))) {\r
+        //\r
+        // Check if there is need to support ISA/VGA decoding\r
+        // If so, we need to avoid isa/vga aliasing range\r
+        //\r
+        if (IsaEnable) {\r
+          SkipIsaAliasAperture (\r
+            &Aperture,\r
+            Node->Length               \r
+            );\r
+          offset = Aperture & (Node->Alignment);\r
+          if (offset) {\r
+            Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+          }\r
+        } else if (VGAEnable) {\r
+          SkipVGAAperture (\r
+            &Aperture,\r
+            Node->Length\r
+            );\r
+          offset = Aperture & (Node->Alignment);\r
+          if (offset) {\r
+            Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+          }\r
+        }\r
+      }\r
+    }\r
+\r

     Node->Offset = Aperture;\r
 \r
     //\r
     Node->Offset = Aperture;\r
 \r
     //\r

diff --git a/EdkModulePkg/EdkModulePkg.spd b/EdkModulePkg/EdkModulePkg.spd
index 9a8861f838e337df37c81c0628893dc64600b0ae..da4eccebf5f5dec845e30065049d816274f94ed7 100644 (file)
--- a/EdkModulePkg/EdkModulePkg.spd
+++ b/EdkModulePkg/EdkModulePkg.spd
@@ -16,7 +16,7 @@
     <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION   0x00000052</Specification>\r
   </SpdHeader>\r
   <PackageDefinitions>\r
     <Specification>FRAMEWORK_BUILD_PACKAGING_SPECIFICATION   0x00000052</Specification>\r
   </SpdHeader>\r
   <PackageDefinitions>\r

-    <ReadOnly>true</ReadOnly>\r
+    <ReadOnly>false</ReadOnly>\r

     <RePackage>false</RePackage>\r
   </PackageDefinitions>\r
   <LibraryClassDeclarations>\r
     <RePackage>false</RePackage>\r
   </PackageDefinitions>\r
   <LibraryClassDeclarations>\r


@@ -1135,5 +1135,23 @@
       <DefaultValue>FALSE</DefaultValue>\r
       <HelpText>If TRUE, then the Device Path From Text Protocol should be produced by the platform</HelpText>\r
     </PcdEntry>\r
       <DefaultValue>FALSE</DefaultValue>\r
       <HelpText>If TRUE, then the Device Path From Text Protocol should be produced by the platform</HelpText>\r
     </PcdEntry>\r

+    <PcdEntry>\r
+      <C_Name>PcdPciIsaEnable</C_Name>\r
+      <Token>0x00010039</Token>\r
+      <TokenSpaceGuidCName>gEfiGenericPlatformTokenSpaceGuid</TokenSpaceGuidCName>\r
+      <DatumType>BOOLEAN</DatumType>\r
+      <ValidUsage>FEATURE_FLAG</ValidUsage>\r
+      <DefaultValue>FALSE</DefaultValue>\r
+      <HelpText>This is a switch to enable ISA</HelpText>\r
+    </PcdEntry>\r
+    <PcdEntry>\r
+      <C_Name>PcdPciVgaEnable</C_Name>\r
+      <Token>0x0001003a</Token>\r
+      <TokenSpaceGuidCName>gEfiGenericPlatformTokenSpaceGuid</TokenSpaceGuidCName>\r
+      <DatumType>BOOLEAN</DatumType>\r
+      <ValidUsage>FEATURE_FLAG</ValidUsage>\r
+      <DefaultValue>FALSE</DefaultValue>\r
+      <HelpText>Whether VGA decoding is enabled on this platform so we should avoid those aliased resources</HelpText>\r
+    </PcdEntry>\r

   </PcdDeclarations>\r
 </PackageSurfaceArea>
\ No newline at end of file
   </PcdDeclarations>\r
 </PackageSurfaceArea>
\ No newline at end of file

diff --git a/EdkModulePkg/Universal/Variable/RuntimeDxe/Variable.c b/EdkModulePkg/Universal/Variable/RuntimeDxe/Variable.c
index 178fa1ea598114d84919f95a2e268e80daa9e9e9..5d631a53682b91515f3bffb59265e2957f4e4cab 100644 (file)
--- a/EdkModulePkg/Universal/Variable/RuntimeDxe/Variable.c
+++ b/EdkModulePkg/Universal/Variable/RuntimeDxe/Variable.c
@@ -15,7 +15,7 @@ Module Name:
 \r
 Abstract:\r
 \r
 \r
 Abstract:\r
 \r

-  Provide support functions for variable services.\r
+Revision History\r

 \r
 --*/\r
 \r
 \r
 --*/\r
 \r


@@ -125,8 +125,7 @@ Arguments:
 \r
 Returns:\r
 \r
 \r
 Returns:\r
 \r

-  EFI_INVALID_PARAMETER   - Parameters not valid\r
-  EFI_SUCCESS             - Variable store successfully updated\r
+  EFI STATUS\r

 \r
 --*/\r
 {\r
 \r
 --*/\r
 {\r


@@ -177,10 +176,11 @@ Returns:
     if ((DataPtr + DataSize) >= ((UINTN) ((UINT8 *) VolatileBase + VolatileBase->Size))) {\r
       return EFI_INVALID_PARAMETER;\r
     }\r
     if ((DataPtr + DataSize) >= ((UINTN) ((UINT8 *) VolatileBase + VolatileBase->Size))) {\r
       return EFI_INVALID_PARAMETER;\r
     }\r

-\r
-    //\r
-    // If Volatile Variable just do a simple mem copy.\r
-    //\r
+  }\r
+  //\r
+  // If Volatile Variable just do a simple mem copy.\r
+  //\r
+  if (Volatile) {\r

     CopyMem ((UINT8 *) ((UINTN) DataPtr), Buffer, DataSize);\r
     return EFI_SUCCESS;\r
   }\r
     CopyMem ((UINT8 *) ((UINTN) DataPtr), Buffer, DataSize);\r
     return EFI_SUCCESS;\r
   }\r


@@ -212,7 +212,9 @@ Returns:
                     &CurrWriteSize,\r
                     CurrBuffer\r
                     );\r
                     &CurrWriteSize,\r
                     CurrBuffer\r
                     );\r

-          return Status;\r
+          if (EFI_ERROR (Status)) {\r
+            return Status;\r
+          }\r

         } else {\r
           Size = (UINT32) (LinearOffset + PtrBlockMapEntry->BlockLength - CurrWritePtr);\r
           Status = EfiFvbWriteBlock (\r
         } else {\r
           Size = (UINT32) (LinearOffset + PtrBlockMapEntry->BlockLength - CurrWritePtr);\r
           Status = EfiFvbWriteBlock (\r


@@ -813,7 +815,8 @@ Returns:
   //  The size of the VariableName, including the Unicode Null in bytes plus\r
   //  the DataSize is limited to maximum size of MAX_VARIABLE_SIZE (1024) bytes.\r
   //\r
   //  The size of the VariableName, including the Unicode Null in bytes plus\r
   //  the DataSize is limited to maximum size of MAX_VARIABLE_SIZE (1024) bytes.\r
   //\r

-  else if (sizeof (VARIABLE_HEADER) + ArrayLength (VariableName) + DataSize > MAX_VARIABLE_SIZE) {\r
+  else if ((DataSize > MAX_VARIABLE_SIZE) ||\r
+           (sizeof (VARIABLE_HEADER) + ArrayLength (VariableName) + DataSize > MAX_VARIABLE_SIZE)) {\r

     return EFI_INVALID_PARAMETER;\r
   }\r
   //\r
     return EFI_INVALID_PARAMETER;\r
   }\r
   //\r

diff --git a/MdePkg/Include/IndustryStandard/pci22.h b/MdePkg/Include/IndustryStandard/pci22.h
index 7fee279e8098ad7fb0d191a9bf122abf50da032b..b9098307a4ffcac1444250223499688d04e7d7d2 100644 (file)
--- a/MdePkg/Include/IndustryStandard/pci22.h
+++ b/MdePkg/Include/IndustryStandard/pci22.h
@@ -168,6 +168,65 @@ typedef struct {
 #define PCI_CLASS_BRIDGE_RACEWAY      0x08\r
 #define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80\r
 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete\r
 #define PCI_CLASS_BRIDGE_RACEWAY      0x08\r
 #define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80\r
 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete\r

+\r
+#define PCI_CLASS_SCC                 0x07  // Simple communications controllers \r
+#define PCI_SUBCLASS_SERIAL           0x00\r
+#define PCI_IF_GENERIC_XT             0x00\r
+#define PCI_IF_16450                  0x01\r
+#define PCI_IF_16550                  0x02\r
+#define PCI_IF_16650                  0x03\r
+#define PCI_IF_16750                  0x04\r
+#define PCI_IF_16850                  0x05\r
+#define PCI_IF_16950                  0x06\r
+#define PCI_SUBCLASS_PARALLEL         0x01\r
+#define PCI_IF_PARALLEL_PORT          0x00\r
+#define PCI_IF_BI_DIR_PARALLEL_PORT   0x01\r
+#define PCI_IF_ECP_PARALLEL_PORT      0x02\r
+#define PCI_IF_1284_CONTROLLER        0x03\r
+#define PCI_IF_1284_DEVICE            0xFE\r
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
+#define PCI_SUBCLASS_MODEM            0x03\r
+#define PCI_IF_GENERIC_MODEM          0x00\r
+#define PCI_IF_16450_MODEM            0x01\r
+#define PCI_IF_16550_MODEM            0x02\r
+#define PCI_IF_16650_MODEM            0x03\r
+#define PCI_IF_16750_MODEM            0x04\r
+#define PCI_SUBCLASS_OTHER            0x80\r
+\r
+#define PCI_CLASS_SYSTEM_PERIPHERAL   0x08\r
+#define PCI_SUBCLASS_PIC              0x00\r
+#define PCI_IF_8259_PIC               0x00\r
+#define PCI_IF_ISA_PIC                0x01\r
+#define PCI_IF_EISA_PIC               0x02\r
+#define PCI_IF_APIC_CONTROLLER        0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.  \r
+#define PCI_IF_APIC_CONTROLLER2       0x20 \r
+#define PCI_SUBCLASS_TIMER            0x02\r
+#define PCI_IF_8254_TIMER             0x00\r
+#define PCI_IF_ISA_TIMER              0x01\r
+#define PCI_EISA_TIMER                0x02\r
+#define PCI_SUBCLASS_RTC              0x03\r
+#define PCI_IF_GENERIC_RTC            0x00\r
+#define PCI_IF_ISA_RTC                0x00\r
+#define PCI_SUBCLASS_PNP_CONTROLLER   0x04 // HotPlug Controller\r
+\r
+#define PCI_CLASS_INPUT_DEVICE        0x09\r
+#define PCI_SUBCLASS_KEYBOARD         0x00\r
+#define PCI_SUBCLASS_PEN              0x01\r
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
+#define PCI_SUBCLASS_SCAN_CONTROLLER  0x03\r
+#define PCI_SUBCLASS_GAMEPORT         0x04\r
+\r
+#define PCI_CLASS_DOCKING_STATION     0x0A\r
+\r
+#define PCI_CLASS_PROCESSOR           0x0B\r
+#define PCI_SUBCLASS_PROC_386         0x00\r
+#define PCI_SUBCLASS_PROC_486         0x01\r
+#define PCI_SUBCLASS_PROC_PENTIUM     0x02\r
+#define PCI_SUBCLASS_PROC_ALPHA       0x10\r
+#define PCI_SUBCLASS_PROC_POWERPC     0x20\r
+#define PCI_SUBCLASS_PROC_MIPS        0x30\r
+#define PCI_SUBCLASS_PROC_CO_PORC     0x40 // Co-Processor\r
+\r

 #define PCI_CLASS_SERIAL              0x0C\r
 #define PCI_CLASS_SERIAL_FIREWIRE     0x00\r
 #define PCI_CLASS_SERIAL_ACCESS_BUS   0x01\r
 #define PCI_CLASS_SERIAL              0x0C\r
 #define PCI_CLASS_SERIAL_FIREWIRE     0x00\r
 #define PCI_CLASS_SERIAL_ACCESS_BUS   0x01\r


@@ -176,6 +235,25 @@ typedef struct {
 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
 #define PCI_CLASS_SERIAL_SMB          0x05\r
 \r
 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
 #define PCI_CLASS_SERIAL_SMB          0x05\r
 \r

+#define PCI_CLASS_WIRELESS            0x0D\r
+#define PCI_SUBCLASS_IRDA             0x00\r
+#define PCI_SUBCLASS_IR               0x01\r
+#define PCI_SUBCLASS_RF               0x02\r
+\r
+#define PCI_CLASS_INTELLIGENT_IO      0x0E\r
+\r
+#define PCI_CLASS_SATELLITE           0x0F\r
+#define PCI_SUBCLASS_TV               0x01\r
+#define PCI_SUBCLASS_AUDIO            0x02\r
+#define PCI_SUBCLASS_VOICE            0x03\r
+#define PCI_SUBCLASS_DATA             0x04\r
+\r
+#define PCI_SECURITY_CONTROLLER       0x10 // Encryption and decryption controller\r
+#define PCI_SUBCLASS_NET_COMPUT       0x00\r
+#define PCI_SUBCLASS_ENTERTAINMENT    0x10 \r
+\r
+#define PCI_CLASS_DPIO                0x11\r
+\r

 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))\r
 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))\r
 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r


@@ -208,8 +286,8 @@ typedef struct {
 #define PCI_DEVICE_ROMBAR             0x30\r
 #define PCI_BRIDGE_ROMBAR             0x38\r
 \r
 #define PCI_DEVICE_ROMBAR             0x30\r
 #define PCI_BRIDGE_ROMBAR             0x38\r
 \r

-#define PCI_MAX_BAR                   6\r
-#define PCI_MAX_CONFIG_OFFSET         0x100\r
+#define PCI_MAX_BAR                   0x0006\r
+#define PCI_MAX_CONFIG_OFFSET         0x0100\r

 //\r
 // bugbug: this is supported in PCI spec v2.3\r
 //\r
 //\r
 // bugbug: this is supported in PCI spec v2.3\r
 //\r


@@ -225,6 +303,18 @@ typedef struct {
 #define PCI_LATENCY_TIMER_OFFSET                    0x0D\r
 #define PCI_HEADER_TYPE_OFFSET                      0x0E\r
 #define PCI_BIST_OFFSET                             0x0F\r
 #define PCI_LATENCY_TIMER_OFFSET                    0x0D\r
 #define PCI_HEADER_TYPE_OFFSET                      0x0E\r
 #define PCI_BIST_OFFSET                             0x0F\r

+#define PCI_BASE_ADDRESSREG_OFFSET                  0x10\r
+#define PCI_CARDBUS_CIS_OFFSET                      0x28\r
+#define PCI_SVID_OFFSET                             0x2C // SubSystem Vendor id\r
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C\r
+#define PCI_SID_OFFSET                              0x2E // SubSystem ID\r
+#define PCI_SUBSYSTEM_ID_OFFSET                     0x2E\r
+#define PCI_EXPANSION_ROM_BASE                      0x30\r
+#define PCI_CAPBILITY_POINTER_OFFSET                0x34\r
+#define PCI_INT_LINE_OFFSET                         0x3C // Interrupt Line Register\r
+#define PCI_INT_PIN_OFFSET                          0x3D // Interrupt Pin Register\r
+#define PCI_MAXGNT_OFFSET                           0x3E // Max Grant Register\r
+#define PCI_MAXLAT_OFFSET                           0x3F // Max Latency Register\r

 \r
 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E\r
 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E\r
 \r
 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E\r
 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E\r


@@ -328,7 +418,8 @@ typedef struct {
 typedef struct {\r
   UINT16  Signature;    // 0xaa55\r
   UINT8   Size512;\r
 typedef struct {\r
   UINT16  Signature;    // 0xaa55\r
   UINT8   Size512;\r

-  UINT8   Reserved[15];\r
+  UINT8   InitEntryPoint[3];\r
+  UINT8   Reserved[0x12];\r

   UINT16  PcirOffset;\r
 } EFI_LEGACY_EXPANSION_ROM_HEADER;\r
 \r
   UINT16  PcirOffset;\r
 } EFI_LEGACY_EXPANSION_ROM_HEADER;\r
 \r


@@ -354,6 +445,23 @@ typedef struct {
   UINT16  Reserved1;\r
 } PCI_DATA_STRUCTURE;\r
 \r
   UINT16  Reserved1;\r
 } PCI_DATA_STRUCTURE;\r
 \r

+typedef struct {\r
+  UINT32  Signature;    // "PCIR"\r
+  UINT16  VendorId;\r
+  UINT16  DeviceId;\r
+  UINT16  DeviceListOffset;\r
+  UINT16  Length;\r
+  UINT8   Revision;\r
+  UINT8   ClassCode[3];\r
+  UINT16  ImageLength;\r
+  UINT16  CodeRevision;\r
+  UINT8   CodeType;\r
+  UINT8   Indicator;\r
+  UINT16  MaxRuntimeImageLength;\r
+  UINT16  ConfigUtilityCodeHeaderOffset;\r
+  UINT16  DMTFCLPEntryPointOffset;\r
+} PCI_3_0_DATA_STRUCTURE;\r
+\r

 //\r
 // PCI Capability List IDs and records\r
 //\r
 //\r
 // PCI Capability List IDs and records\r
 //\r

diff --git a/Tools/CCode/Source/Include/IndustryStandard/pci22.h b/Tools/CCode/Source/Include/IndustryStandard/pci22.h
index 7fee279e8098ad7fb0d191a9bf122abf50da032b..8893a8a22f8b766a89a2ff03cf139bbd5a874ac4 100644 (file)
--- a/Tools/CCode/Source/Include/IndustryStandard/pci22.h
+++ b/Tools/CCode/Source/Include/IndustryStandard/pci22.h
@@ -168,6 +168,65 @@ typedef struct {
 #define PCI_CLASS_BRIDGE_RACEWAY      0x08\r
 #define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80\r
 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete\r
 #define PCI_CLASS_BRIDGE_RACEWAY      0x08\r
 #define PCI_CLASS_BRIDGE_ISA_PDECODE  0x80\r
 #define PCI_CLASS_ISA_POSITIVE_DECODE 0x80  // obsolete\r

+\r
+#define PCI_CLASS_SCC                 0x07  // Simple communications controllers \r
+#define PCI_SUBCLASS_SERIAL           0x00\r
+#define PCI_IF_GENERIC_XT             0x00\r
+#define PCI_IF_16450                  0x01\r
+#define PCI_IF_16550                  0x02\r
+#define PCI_IF_16650                  0x03\r
+#define PCI_IF_16750                  0x04\r
+#define PCI_IF_16850                  0x05\r
+#define PCI_IF_16950                  0x06\r
+#define PCI_SUBCLASS_PARALLEL         0x01\r
+#define PCI_IF_PARALLEL_PORT          0x00\r
+#define PCI_IF_BI_DIR_PARALLEL_PORT   0x01\r
+#define PCI_IF_ECP_PARALLEL_PORT      0x02\r
+#define PCI_IF_1284_CONTROLLER        0x03\r
+#define PCI_IF_1284_DEVICE            0xFE\r
+#define PCI_SUBCLASS_MULTIPORT_SERIAL 0x02\r
+#define PCI_SUBCLASS_MODEM            0x03\r
+#define PCI_IF_GENERIC_MODEM          0x00\r
+#define PCI_IF_16450_MODEM            0x01\r
+#define PCI_IF_16550_MODEM            0x02\r
+#define PCI_IF_16650_MODEM            0x03\r
+#define PCI_IF_16750_MODEM            0x04\r
+#define PCI_SUBCLASS_OTHER            0x80\r
+\r
+#define PCI_CLASS_SYSTEM_PERIPHERAL   0x08\r
+#define PCI_SUBCLASS_PIC              0x00\r
+#define PCI_IF_8259_PIC               0x00\r
+#define PCI_IF_ISA_PIC                0x01\r
+#define PCI_IF_EISA_PIC               0x02\r
+#define PCI_IF_APIC_CONTROLLER        0x10 // I/O APIC interrupt controller , 32 bye none-prefectable memory.  \r
+#define PCI_IF_APIC_CONTROLLER2       0x20 \r
+#define PCI_SUBCLASS_TIMER            0x02\r
+#define PCI_IF_8254_TIMER             0x00\r
+#define PCI_IF_ISA_TIMER              0x01\r
+#define PCI_EISA_TIMER                0x02\r
+#define PCI_SUBCLASS_RTC              0x03\r
+#define PCI_IF_GENERIC_RTC            0x00\r
+#define PCI_IF_ISA_RTC                0x00\r
+#define PCI_SUBCLASS_PNP_CONTROLLER   0x04 // HotPlug Controller\r
+\r
+#define PCI_CLASS_INPUT_DEVICE        0x09\r
+#define PCI_SUBCLASS_KEYBOARD         0x00\r
+#define PCI_SUBCLASS_PEN              0x01\r
+#define PCI_SUBCLASS_MOUSE_CONTROLLER 0x02\r
+#define PCI_SUBCLASS_SCAN_CONTROLLER  0x03\r
+#define PCI_SUBCLASS_GAMEPORT         0x04\r
+\r
+#define PCI_CLASS_DOCKING_STATION     0x0A\r
+\r
+#define PCI_CLASS_PROCESSOR           0x0B\r
+#define PCI_SUBCLASS_PROC_386         0x00\r
+#define PCI_SUBCLASS_PROC_486         0x01\r
+#define PCI_SUBCLASS_PROC_PENTIUM     0x02\r
+#define PCI_SUBCLASS_PROC_ALPHA       0x10\r
+#define PCI_SUBCLASS_PROC_POWERPC     0x20\r
+#define PCI_SUBCLASS_PROC_MIPS        0x30\r
+#define PCI_SUBCLASS_PROC_CO_PORC     0x40 // Co-Processor\r
+\r

 #define PCI_CLASS_SERIAL              0x0C\r
 #define PCI_CLASS_SERIAL_FIREWIRE     0x00\r
 #define PCI_CLASS_SERIAL_ACCESS_BUS   0x01\r
 #define PCI_CLASS_SERIAL              0x0C\r
 #define PCI_CLASS_SERIAL_FIREWIRE     0x00\r
 #define PCI_CLASS_SERIAL_ACCESS_BUS   0x01\r


@@ -176,6 +235,25 @@ typedef struct {
 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
 #define PCI_CLASS_SERIAL_SMB          0x05\r
 \r
 #define PCI_CLASS_SERIAL_FIBRECHANNEL 0x04\r
 #define PCI_CLASS_SERIAL_SMB          0x05\r
 \r

+#define PCI_CLASS_WIRELESS            0x0D\r
+#define PCI_SUBCLASS_IRDA             0x00\r
+#define PCI_SUBCLASS_IR               0x01\r
+#define PCI_SUBCLASS_RF               0x02\r
+\r
+#define PCI_CLASS_INTELLIGENT_IO      0x0E\r
+\r
+#define PCI_CLASS_SATELLITE           0x0F\r
+#define PCI_SUBCLASS_TV               0x01\r
+#define PCI_SUBCLASS_AUDIO            0x02\r
+#define PCI_SUBCLASS_VOICE            0x03\r
+#define PCI_SUBCLASS_DATA             0x04\r
+\r
+#define PCI_SECURITY_CONTROLLER       0x10 // Encryption and decryption controller\r
+#define PCI_SUBCLASS_NET_COMPUT       0x00\r
+#define PCI_SUBCLASS_ENTERTAINMENT    0x10 \r
+\r
+#define PCI_CLASS_DPIO                0x11\r
+\r

 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))\r
 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r
 #define IS_CLASS1(_p, c)              ((_p)->Hdr.ClassCode[2] == (c))\r
 #define IS_CLASS2(_p, c, s)           (IS_CLASS1 (_p, c) && ((_p)->Hdr.ClassCode[1] == (s)))\r
 #define IS_CLASS3(_p, c, s, p)        (IS_CLASS2 (_p, c, s) && ((_p)->Hdr.ClassCode[0] == (p)))\r


@@ -208,8 +286,8 @@ typedef struct {
 #define PCI_DEVICE_ROMBAR             0x30\r
 #define PCI_BRIDGE_ROMBAR             0x38\r
 \r
 #define PCI_DEVICE_ROMBAR             0x30\r
 #define PCI_BRIDGE_ROMBAR             0x38\r
 \r

-#define PCI_MAX_BAR                   6\r
-#define PCI_MAX_CONFIG_OFFSET         0x100\r
+#define PCI_MAX_BAR                   0x0006\r
+#define PCI_MAX_CONFIG_OFFSET         0x0100\r

 //\r
 // bugbug: this is supported in PCI spec v2.3\r
 //\r
 //\r
 // bugbug: this is supported in PCI spec v2.3\r
 //\r


@@ -225,6 +303,18 @@ typedef struct {
 #define PCI_LATENCY_TIMER_OFFSET                    0x0D\r
 #define PCI_HEADER_TYPE_OFFSET                      0x0E\r
 #define PCI_BIST_OFFSET                             0x0F\r
 #define PCI_LATENCY_TIMER_OFFSET                    0x0D\r
 #define PCI_HEADER_TYPE_OFFSET                      0x0E\r
 #define PCI_BIST_OFFSET                             0x0F\r

+#define PCI_BASE_ADDRESSREG_OFFSET                  0x10\r
+#define PCI_CARDBUS_CIS_OFFSET                      0x28\r
+#define PCI_SVID_OFFSET                             0x2C // SubSystem Vendor id\r
+#define PCI_SUBSYSTEM_VENDOR_ID_OFFSET              0x2C\r
+#define PCI_SID_OFFSET                              0x2E // SubSystem ID\r
+#define PCI_SUBSYSTEM_ID_OFFSET                     0x2E\r
+#define PCI_EXPANSION_ROM_BASE                      0x30\r
+#define PCI_CAPBILITY_POINTER_OFFSET                0x34\r
+#define PCI_INT_LINE_OFFSET                         0x3C // Interrupt Line Register\r
+#define PCI_INT_PIN_OFFSET                          0x3D // Interrupt Pin Register\r
+#define PCI_MAXGNT_OFFSET                           0x3E // Max Grant Register\r
+#define PCI_MAXLAT_OFFSET                           0x3F // Max Latency Register\r

 \r
 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E\r
 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E\r
 \r
 #define PCI_BRIDGE_CONTROL_REGISTER_OFFSET          0x3E\r
 #define PCI_BRIDGE_STATUS_REGISTER_OFFSET           0x1E\r


@@ -328,7 +418,8 @@ typedef struct {
 typedef struct {\r
   UINT16  Signature;    // 0xaa55\r
   UINT8   Size512;\r
 typedef struct {\r
   UINT16  Signature;    // 0xaa55\r
   UINT8   Size512;\r

-  UINT8   Reserved[15];\r
+  UINT8   InitEntryPoint[3];\r
+  UINT8   Reserved[0x12];  \r

   UINT16  PcirOffset;\r
 } EFI_LEGACY_EXPANSION_ROM_HEADER;\r
 \r
   UINT16  PcirOffset;\r
 } EFI_LEGACY_EXPANSION_ROM_HEADER;\r
 \r