-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; SmiException.asm\r
-;\r
-; Abstract:\r
-;\r
-; Exception handlers used in SM mode\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
- .686p\r
- .model flat,C\r
-\r
-EXTERNDEF SmiPFHandler:PROC\r
-EXTERNDEF PageFaultStubFunction:PROC\r
-EXTERNDEF gcSmiIdtr:FWORD\r
-EXTERNDEF gcSmiGdtr:FWORD\r
-EXTERNDEF gTaskGateDescriptor:QWORD\r
-EXTERNDEF gcPsd:BYTE\r
-EXTERNDEF FeaturePcdGet (PcdCpuSmmProfileEnable):BYTE\r
-\r
-\r
- .data\r
-\r
-NullSeg DQ 0 ; reserved by architecture\r
-CodeSeg32 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 9bh\r
- DB 0cfh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-ProtModeCodeSeg32 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 9bh\r
- DB 0cfh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-ProtModeSsSeg32 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 93h\r
- DB 0cfh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-DataSeg32 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 93h\r
- DB 0cfh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-CodeSeg16 LABEL QWORD\r
- DW -1\r
- DW 0\r
- DB 0\r
- DB 9bh\r
- DB 8fh\r
- DB 0\r
-DataSeg16 LABEL QWORD\r
- DW -1\r
- DW 0\r
- DB 0\r
- DB 93h\r
- DB 8fh\r
- DB 0\r
-CodeSeg64 LABEL QWORD\r
- DW -1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 9bh\r
- DB 0afh ; LimitHigh\r
- DB 0 ; BaseHigh\r
-GDT_SIZE = $ - offset NullSeg\r
-\r
-TssSeg LABEL QWORD\r
- DW TSS_DESC_SIZE - 1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 89h\r
- DB 00h ; LimitHigh\r
- DB 0 ; BaseHigh\r
-ExceptionTssSeg LABEL QWORD\r
- DW TSS_DESC_SIZE - 1 ; LimitLow\r
- DW 0 ; BaseLow\r
- DB 0 ; BaseMid\r
- DB 89h\r
- DB 00h ; LimitHigh\r
- DB 0 ; BaseHigh\r
-\r
-CODE_SEL = offset CodeSeg32 - offset NullSeg\r
-DATA_SEL = offset DataSeg32 - offset NullSeg\r
-TSS_SEL = offset TssSeg - offset NullSeg\r
-EXCEPTION_TSS_SEL = offset ExceptionTssSeg - offset NullSeg\r
-\r
-IA32_TSS STRUC\r
- DW ?\r
- DW ?\r
- ESP0 DD ?\r
- SS0 DW ?\r
- DW ?\r
- ESP1 DD ?\r
- SS1 DW ?\r
- DW ?\r
- ESP2 DD ?\r
- SS2 DW ?\r
- DW ?\r
- _CR3 DD ?\r
- EIP DD ?\r
- EFLAGS DD ?\r
- _EAX DD ?\r
- _ECX DD ?\r
- _EDX DD ?\r
- _EBX DD ?\r
- _ESP DD ?\r
- _EBP DD ?\r
- _ESI DD ?\r
- _EDI DD ?\r
- _ES DW ?\r
- DW ?\r
- _CS DW ?\r
- DW ?\r
- _SS DW ?\r
- DW ?\r
- _DS DW ?\r
- DW ?\r
- _FS DW ?\r
- DW ?\r
- _GS DW ?\r
- DW ?\r
- LDT DW ?\r
- DW ?\r
- DW ?\r
- DW ?\r
-IA32_TSS ENDS\r
-\r
-; Create 2 TSS segments just after GDT\r
-TssDescriptor LABEL BYTE\r
- DW 0 ; PreviousTaskLink\r
- DW 0 ; Reserved\r
- DD 0 ; ESP0\r
- DW 0 ; SS0\r
- DW 0 ; Reserved\r
- DD 0 ; ESP1\r
- DW 0 ; SS1\r
- DW 0 ; Reserved\r
- DD 0 ; ESP2\r
- DW 0 ; SS2\r
- DW 0 ; Reserved\r
- DD 0 ; CR3\r
- DD 0 ; EIP\r
- DD 0 ; EFLAGS\r
- DD 0 ; EAX\r
- DD 0 ; ECX\r
- DD 0 ; EDX\r
- DD 0 ; EBX\r
- DD 0 ; ESP\r
- DD 0 ; EBP\r
- DD 0 ; ESI\r
- DD 0 ; EDI\r
- DW 0 ; ES\r
- DW 0 ; Reserved\r
- DW 0 ; CS\r
- DW 0 ; Reserved\r
- DW 0 ; SS\r
- DW 0 ; Reserved\r
- DW 0 ; DS\r
- DW 0 ; Reserved\r
- DW 0 ; FS\r
- DW 0 ; Reserved\r
- DW 0 ; GS\r
- DW 0 ; Reserved\r
- DW 0 ; LDT Selector\r
- DW 0 ; Reserved\r
- DW 0 ; T\r
- DW 0 ; I/O Map Base\r
-TSS_DESC_SIZE = $ - offset TssDescriptor\r
-\r
-ExceptionTssDescriptor LABEL BYTE\r
- DW 0 ; PreviousTaskLink\r
- DW 0 ; Reserved\r
- DD 0 ; ESP0\r
- DW 0 ; SS0\r
- DW 0 ; Reserved\r
- DD 0 ; ESP1\r
- DW 0 ; SS1\r
- DW 0 ; Reserved\r
- DD 0 ; ESP2\r
- DW 0 ; SS2\r
- DW 0 ; Reserved\r
- DD 0 ; CR3\r
- DD offset PFHandlerEntry ; EIP\r
- DD 00000002 ; EFLAGS\r
- DD 0 ; EAX\r
- DD 0 ; ECX\r
- DD 0 ; EDX\r
- DD 0 ; EBX\r
- DD 0 ; ESP\r
- DD 0 ; EBP\r
- DD 0 ; ESI\r
- DD 0 ; EDI\r
- DW DATA_SEL ; ES\r
- DW 0 ; Reserved\r
- DW CODE_SEL ; CS\r
- DW 0 ; Reserved\r
- DW DATA_SEL ; SS\r
- DW 0 ; Reserved\r
- DW DATA_SEL ; DS\r
- DW 0 ; Reserved\r
- DW DATA_SEL ; FS\r
- DW 0 ; Reserved\r
- DW DATA_SEL ; GS\r
- DW 0 ; Reserved\r
- DW 0 ; LDT Selector\r
- DW 0 ; Reserved\r
- DW 0 ; T\r
- DW 0 ; I/O Map Base\r
-\r
-gcPsd LABEL BYTE\r
- DB 'PSDSIG '\r
- DW PSD_SIZE\r
- DW 2\r
- DW 1 SHL 2\r
- DW CODE_SEL\r
- DW DATA_SEL\r
- DW DATA_SEL\r
- DW DATA_SEL\r
- DW 0\r
- DQ 0\r
- DQ 0\r
- DQ 0\r
- DQ offset NullSeg\r
- DD GDT_SIZE\r
- DD 0\r
- DB 24 dup (0)\r
- DQ 0\r
-PSD_SIZE = $ - offset gcPsd\r
-\r
-gcSmiGdtr LABEL FWORD\r
- DW GDT_SIZE - 1\r
- DD offset NullSeg\r
-\r
-gcSmiIdtr LABEL FWORD\r
- DW 0\r
- DD 0\r
-\r
-gTaskGateDescriptor LABEL QWORD\r
- DW 0 ; Reserved\r
- DW EXCEPTION_TSS_SEL ; TSS Segment selector\r
- DB 0 ; Reserved\r
- DB 85h ; Task Gate, present, DPL = 0\r
- DW 0 ; Reserved\r
-\r
-\r
- .code\r
-;------------------------------------------------------------------------------\r
-; PageFaultIdtHandlerSmmProfile is the entry point page fault only\r
-;\r
-;\r
-; Stack:\r
-; +---------------------+\r
-; + EFlags +\r
-; +---------------------+\r
-; + CS +\r
-; +---------------------+\r
-; + EIP +\r
-; +---------------------+\r
-; + Error Code +\r
-; +---------------------+\r
-; + Vector Number +\r
-; +---------------------+\r
-; + EBP +\r
-; +---------------------+ <-- EBP\r
-;\r
-;\r
-;------------------------------------------------------------------------------\r
-PageFaultIdtHandlerSmmProfile PROC\r
- push 0eh ; Page Fault\r
-\r
- push ebp\r
- mov ebp, esp\r
-\r
-\r
- ;\r
- ; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32\r
- ; is 16-byte aligned\r
- ;\r
- and esp, 0fffffff0h\r
- sub esp, 12\r
-\r
-;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- push eax\r
- push ecx\r
- push edx\r
- push ebx\r
- lea ecx, [ebp + 6 * 4]\r
- push ecx ; ESP\r
- push dword ptr [ebp] ; EBP\r
- push esi\r
- push edi\r
-\r
-;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
- mov eax, ss\r
- push eax\r
- movzx eax, word ptr [ebp + 4 * 4]\r
- push eax\r
- mov eax, ds\r
- push eax\r
- mov eax, es\r
- push eax\r
- mov eax, fs\r
- push eax\r
- mov eax, gs\r
- push eax\r
-\r
-;; UINT32 Eip;\r
- mov eax, [ebp + 3 * 4]\r
- push eax\r
-\r
-;; UINT32 Gdtr[2], Idtr[2];\r
- sub esp, 8\r
- sidt [esp]\r
- mov eax, [esp + 2]\r
- xchg eax, [esp]\r
- and eax, 0FFFFh\r
- mov [esp+4], eax\r
-\r
- sub esp, 8\r
- sgdt [esp]\r
- mov eax, [esp + 2]\r
- xchg eax, [esp]\r
- and eax, 0FFFFh\r
- mov [esp+4], eax\r
-\r
-;; UINT32 Ldtr, Tr;\r
- xor eax, eax\r
- str ax\r
- push eax\r
- sldt ax\r
- push eax\r
-\r
-;; UINT32 EFlags;\r
- mov eax, [ebp + 5 * 4]\r
- push eax\r
-\r
-;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- mov eax, cr4\r
- or eax, 208h\r
- mov cr4, eax\r
- push eax\r
- mov eax, cr3\r
- push eax\r
- mov eax, cr2\r
- push eax\r
- xor eax, eax\r
- push eax\r
- mov eax, cr0\r
- push eax\r
-\r
-;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
- mov eax, dr7\r
- push eax\r
- mov eax, dr6\r
- push eax\r
- mov eax, dr3\r
- push eax\r
- mov eax, dr2\r
- push eax\r
- mov eax, dr1\r
- push eax\r
- mov eax, dr0\r
- push eax\r
-\r
-;; FX_SAVE_STATE_IA32 FxSaveState;\r
- sub esp, 512\r
- mov edi, esp\r
- db 0fh, 0aeh, 07h ;fxsave [edi]\r
-\r
-; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
- cld\r
-\r
-;; UINT32 ExceptionData;\r
- push dword ptr [ebp + 2 * 4]\r
-\r
-;; call into exception handler\r
-\r
-;; Prepare parameter and call\r
- mov edx, esp\r
- push edx\r
- mov edx, dword ptr [ebp + 1 * 4]\r
- push edx\r
-\r
- ;\r
- ; Call External Exception Handler\r
- ;\r
- mov eax, SmiPFHandler\r
- call eax\r
- add esp, 8\r
-\r
-;; UINT32 ExceptionData;\r
- add esp, 4\r
-\r
-;; FX_SAVE_STATE_IA32 FxSaveState;\r
- mov esi, esp\r
- db 0fh, 0aeh, 0eh ; fxrstor [esi]\r
- add esp, 512\r
-\r
-;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
-;; Skip restoration of DRx registers to support debuggers\r
-;; that set breakpoint in interrupt/exception context\r
- add esp, 4 * 6\r
-\r
-;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- pop eax\r
- mov cr0, eax\r
- add esp, 4 ; not for Cr1\r
- pop eax\r
- mov cr2, eax\r
- pop eax\r
- mov cr3, eax\r
- pop eax\r
- mov cr4, eax\r
-\r
-;; UINT32 EFlags;\r
- pop dword ptr [ebp + 5 * 4]\r
-\r
-;; UINT32 Ldtr, Tr;\r
-;; UINT32 Gdtr[2], Idtr[2];\r
-;; Best not let anyone mess with these particular registers...\r
- add esp, 24\r
-\r
-;; UINT32 Eip;\r
- pop dword ptr [ebp + 3 * 4]\r
-\r
-;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
-;; NOTE - modified segment registers could hang the debugger... We\r
-;; could attempt to insulate ourselves against this possibility,\r
-;; but that poses risks as well.\r
-;;\r
- pop gs\r
- pop fs\r
- pop es\r
- pop ds\r
- pop dword ptr [ebp + 4 * 4]\r
- pop ss\r
-\r
-;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- pop edi\r
- pop esi\r
- add esp, 4 ; not for ebp\r
- add esp, 4 ; not for esp\r
- pop ebx\r
- pop edx\r
- pop ecx\r
- pop eax\r
-\r
- mov esp, ebp\r
- pop ebp\r
-\r
-; Enable TF bit after page fault handler runs\r
- bts dword ptr [esp + 16], 8 ; EFLAGS\r
-\r
- add esp, 8 ; skip INT# & ErrCode\r
-Return:\r
- iretd\r
-;\r
-; Page Fault Exception Handler entry when SMM Stack Guard is enabled\r
-; Executiot starts here after a task switch\r
-;\r
-PFHandlerEntry::\r
-;\r
-; Get this processor's TSS\r
-;\r
- sub esp, 8\r
- sgdt [esp + 2]\r
- mov eax, [esp + 4] ; GDT base\r
- add esp, 8\r
- mov ecx, [eax + TSS_SEL + 2]\r
- shl ecx, 8\r
- mov cl, [eax + TSS_SEL + 7]\r
- ror ecx, 8 ; ecx = TSS base\r
-\r
- mov ebp, esp\r
-\r
- ;\r
- ; Align stack to make sure that EFI_FX_SAVE_STATE_IA32 of EFI_SYSTEM_CONTEXT_IA32\r
- ; is 16-byte aligned\r
- ;\r
- and esp, 0fffffff0h\r
- sub esp, 12\r
-\r
-;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- push (IA32_TSS ptr [ecx])._EAX\r
- push (IA32_TSS ptr [ecx])._ECX\r
- push (IA32_TSS ptr [ecx])._EDX\r
- push (IA32_TSS ptr [ecx])._EBX\r
- push (IA32_TSS ptr [ecx])._ESP\r
- push (IA32_TSS ptr [ecx])._EBP\r
- push (IA32_TSS ptr [ecx])._ESI\r
- push (IA32_TSS ptr [ecx])._EDI\r
-\r
-;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
- movzx eax, (IA32_TSS ptr [ecx])._SS\r
- push eax\r
- movzx eax, (IA32_TSS ptr [ecx])._CS\r
- push eax\r
- movzx eax, (IA32_TSS ptr [ecx])._DS\r
- push eax\r
- movzx eax, (IA32_TSS ptr [ecx])._ES\r
- push eax\r
- movzx eax, (IA32_TSS ptr [ecx])._FS\r
- push eax\r
- movzx eax, (IA32_TSS ptr [ecx])._GS\r
- push eax\r
-\r
-;; UINT32 Eip;\r
- push (IA32_TSS ptr [ecx]).EIP\r
-\r
-;; UINT32 Gdtr[2], Idtr[2];\r
- sub esp, 8\r
- sidt [esp]\r
- mov eax, [esp + 2]\r
- xchg eax, [esp]\r
- and eax, 0FFFFh\r
- mov [esp+4], eax\r
-\r
- sub esp, 8\r
- sgdt [esp]\r
- mov eax, [esp + 2]\r
- xchg eax, [esp]\r
- and eax, 0FFFFh\r
- mov [esp+4], eax\r
-\r
-;; UINT32 Ldtr, Tr;\r
- mov eax, TSS_SEL\r
- push eax\r
- movzx eax, (IA32_TSS ptr [ecx]).LDT\r
- push eax\r
-\r
-;; UINT32 EFlags;\r
- push (IA32_TSS ptr [ecx]).EFLAGS\r
-\r
-;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- mov eax, cr4\r
- or eax, 208h\r
- mov cr4, eax\r
- push eax\r
- mov eax, cr3\r
- push eax\r
- mov eax, cr2\r
- push eax\r
- xor eax, eax\r
- push eax\r
- mov eax, cr0\r
- push eax\r
-\r
-;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
- mov eax, dr7\r
- push eax\r
- mov eax, dr6\r
- push eax\r
- mov eax, dr3\r
- push eax\r
- mov eax, dr2\r
- push eax\r
- mov eax, dr1\r
- push eax\r
- mov eax, dr0\r
- push eax\r
-\r
-;; FX_SAVE_STATE_IA32 FxSaveState;\r
-;; Clear TS bit in CR0 to avoid Device Not Available Exception (#NM)\r
-;; when executing fxsave/fxrstor instruction\r
- clts\r
- sub esp, 512\r
- mov edi, esp\r
- db 0fh, 0aeh, 07h ;fxsave [edi]\r
-\r
-; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear\r
- cld\r
-\r
-;; UINT32 ExceptionData;\r
- push dword ptr [ebp]\r
-\r
-;; call into exception handler\r
- mov ebx, ecx\r
- mov eax, SmiPFHandler\r
-\r
-;; Prepare parameter and call\r
- mov edx, esp\r
- push edx\r
- mov edx, 14\r
- push edx\r
-\r
- ;\r
- ; Call External Exception Handler\r
- ;\r
- call eax\r
- add esp, 8\r
-\r
- mov ecx, ebx\r
-;; UINT32 ExceptionData;\r
- add esp, 4\r
-\r
-;; FX_SAVE_STATE_IA32 FxSaveState;\r
- mov esi, esp\r
- db 0fh, 0aeh, 0eh ; fxrstor [esi]\r
- add esp, 512\r
-\r
-;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;\r
-;; Skip restoration of DRx registers to support debuggers\r
-;; that set breakpoints in interrupt/exception context\r
- add esp, 4 * 6\r
-\r
-;; UINT32 Cr0, Cr1, Cr2, Cr3, Cr4;\r
- pop eax\r
- mov cr0, eax\r
- add esp, 4 ; not for Cr1\r
- pop eax\r
- mov cr2, eax\r
- pop eax\r
- mov (IA32_TSS ptr [ecx])._CR3, eax\r
- pop eax\r
- mov cr4, eax\r
-\r
-;; UINT32 EFlags;\r
- pop (IA32_TSS ptr [ecx]).EFLAGS\r
-\r
-;; UINT32 Ldtr, Tr;\r
-;; UINT32 Gdtr[2], Idtr[2];\r
-;; Best not let anyone mess with these particular registers...\r
- add esp, 24\r
-\r
-;; UINT32 Eip;\r
- pop (IA32_TSS ptr [ecx]).EIP\r
-\r
-;; UINT32 Gs, Fs, Es, Ds, Cs, Ss;\r
-;; NOTE - modified segment registers could hang the debugger... We\r
-;; could attempt to insulate ourselves against this possibility,\r
-;; but that poses risks as well.\r
-;;\r
- pop eax\r
- mov (IA32_TSS ptr [ecx])._GS, ax\r
- pop eax\r
- mov (IA32_TSS ptr [ecx])._FS, ax\r
- pop eax\r
- mov (IA32_TSS ptr [ecx])._ES, ax\r
- pop eax\r
- mov (IA32_TSS ptr [ecx])._DS, ax\r
- pop eax\r
- mov (IA32_TSS ptr [ecx])._CS, ax\r
- pop eax\r
- mov (IA32_TSS ptr [ecx])._SS, ax\r
-\r
-;; UINT32 Edi, Esi, Ebp, Esp, Ebx, Edx, Ecx, Eax;\r
- pop (IA32_TSS ptr [ecx])._EDI\r
- pop (IA32_TSS ptr [ecx])._ESI\r
- add esp, 4 ; not for ebp\r
- add esp, 4 ; not for esp\r
- pop (IA32_TSS ptr [ecx])._EBX\r
- pop (IA32_TSS ptr [ecx])._EDX\r
- pop (IA32_TSS ptr [ecx])._ECX\r
- pop (IA32_TSS ptr [ecx])._EAX\r
-\r
- mov esp, ebp\r
-\r
-; Set single step DB# if SMM profile is enabled and page fault exception happens\r
- cmp FeaturePcdGet (PcdCpuSmmProfileEnable), 0\r
- jz @Done2\r
-\r
-; Create return context for iretd in stub function\r
- mov eax, (IA32_TSS ptr [ecx])._ESP ; Get old stack pointer\r
- mov ebx, (IA32_TSS ptr [ecx]).EIP\r
- mov [eax - 0ch], ebx ; create EIP in old stack\r
- movzx ebx, (IA32_TSS ptr [ecx])._CS\r
- mov [eax - 08h], ebx ; create CS in old stack\r
- mov ebx, (IA32_TSS ptr [ecx]).EFLAGS\r
- bts ebx, 8\r
- mov [eax - 04h], ebx ; create eflags in old stack\r
- mov eax, (IA32_TSS ptr [ecx])._ESP ; Get old stack pointer\r
- sub eax, 0ch ; minus 12 byte\r
- mov (IA32_TSS ptr [ecx])._ESP, eax ; Set new stack pointer\r
-; Replace the EIP of interrupted task with stub function\r
- mov eax, PageFaultStubFunction\r
- mov (IA32_TSS ptr [ecx]).EIP, eax\r
-; Jump to the iretd so next page fault handler as a task will start again after iretd.\r
-@Done2:\r
- add esp, 4 ; skip ErrCode\r
-\r
- jmp Return\r
-PageFaultIdtHandlerSmmProfile ENDP\r
-\r
-PageFaultStubFunction PROC\r
-;\r
-; we need clean TS bit in CR0 to execute\r
-; x87 FPU/MMX/SSE/SSE2/SSE3/SSSE3/SSE4 instructions.\r
-;\r
- clts\r
- iretd\r
-PageFaultStubFunction ENDP\r
-\r
- END\r