MdeModulePkg/XhciDxe: rename "Lenth" to "Length" in TRB structs

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Feng Tian <feng.tian@intel.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Baraneedharan Anbazhagan <anbazhagan@hp.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17205 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
index 657020f0da1e175ecf5969b95c08813c9825a53d..c353d494c45b5e226751c6cd6d36b39c4fde6b8b 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.c
@@ -2,7 +2,7 @@
 \r
   XHCI transfer scheduling routines.\r
 \r
-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -295,7 +295,7 @@ XhcCreateTransferTrb (
       TrbStart->TrbCtrSetup.wValue        = Urb->Request->Value;\r
       TrbStart->TrbCtrSetup.wIndex        = Urb->Request->Index;\r
       TrbStart->TrbCtrSetup.wLength       = Urb->Request->Length;\r
-      TrbStart->TrbCtrSetup.Lenth         = 8;\r
+      TrbStart->TrbCtrSetup.Length        = 8;\r
       TrbStart->TrbCtrSetup.IntTarget     = 0;\r
       TrbStart->TrbCtrSetup.IOC           = 1;\r
       TrbStart->TrbCtrSetup.IDT           = 1;\r
@@ -321,7 +321,7 @@ XhcCreateTransferTrb (
         TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
         TrbStart->TrbCtrData.TRBPtrLo  = XHC_LOW_32BIT(Urb->DataPhy);\r
         TrbStart->TrbCtrData.TRBPtrHi  = XHC_HIGH_32BIT(Urb->DataPhy);\r
-        TrbStart->TrbCtrData.Lenth     = (UINT32) Urb->DataLen;\r
+        TrbStart->TrbCtrData.Length    = (UINT32) Urb->DataLen;\r
         TrbStart->TrbCtrData.TDSize    = 0;\r
         TrbStart->TrbCtrData.IntTarget = 0;\r
         TrbStart->TrbCtrData.ISP       = 1;\r
@@ -387,7 +387,7 @@ XhcCreateTransferTrb (
         TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
         TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
         TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
-        TrbStart->TrbNormal.Lenth     = (UINT32) Len;\r
+        TrbStart->TrbNormal.Length    = (UINT32) Len;\r
         TrbStart->TrbNormal.TDSize    = 0;\r
         TrbStart->TrbNormal.IntTarget = 0;\r
         TrbStart->TrbNormal.ISP       = 1;\r
@@ -422,7 +422,7 @@ XhcCreateTransferTrb (
         TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r
         TrbStart->TrbNormal.TRBPtrLo  = XHC_LOW_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
         TrbStart->TrbNormal.TRBPtrHi  = XHC_HIGH_32BIT((UINT8 *) Urb->DataPhy + TotalLen);\r
-        TrbStart->TrbNormal.Lenth     = (UINT32) Len;\r
+        TrbStart->TrbNormal.Length    = (UINT32) Len;\r
         TrbStart->TrbNormal.TDSize    = 0;\r
         TrbStart->TrbNormal.IntTarget = 0;\r
         TrbStart->TrbNormal.ISP       = 1;\r
@@ -1137,7 +1137,7 @@ XhcCheckUrbResult (
         if ((TRBType == TRB_TYPE_DATA_STAGE) ||\r
             (TRBType == TRB_TYPE_NORMAL) ||\r
             (TRBType == TRB_TYPE_ISOCH)) {\r
-          CheckedUrb->Completed += (CheckedUrb->DataLen - EvtTrb->Lenth);\r
+          CheckedUrb->Completed += (CheckedUrb->DataLen - EvtTrb->Length);\r
         }\r
 \r
         break;\r

diff --git a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
index 023c1089f29c78d93a737885702377fb6ad4aac7..1b6e34590ec612dae8495951c11844ede8d1e400 100644 (file)
--- a/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
+++ b/MdeModulePkg/Bus/Pci/XhciDxe/XhciSched.h
@@ -2,7 +2,7 @@
 \r
   This file contains the definition for XHCI host controller schedule routines.\r
 \r
-Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -224,7 +224,7 @@ typedef struct _TRANSFER_TRB_NORMAL {
 \r
   UINT32                  TRBPtrHi;\r
 \r
-  UINT32                  Lenth:17;\r
+  UINT32                  Length:17;\r
   UINT32                  TDSize:5;\r
   UINT32                  IntTarget:10;\r
 \r
@@ -253,7 +253,7 @@ typedef struct _TRANSFER_TRB_CONTROL_SETUP {
   UINT32                  wIndex:16;\r
   UINT32                  wLength:16;\r
 \r
-  UINT32                  Lenth:17;\r
+  UINT32                  Length:17;\r
   UINT32                  RsvdZ1:5;\r
   UINT32                  IntTarget:10;\r
 \r
@@ -276,7 +276,7 @@ typedef struct _TRANSFER_TRB_CONTROL_DATA {
 \r
   UINT32                  TRBPtrHi;\r
 \r
-  UINT32                  Lenth:17;\r
+  UINT32                  Length:17;\r
   UINT32                  TDSize:5;\r
   UINT32                  IntTarget:10;\r
 \r
@@ -325,7 +325,7 @@ typedef struct _EVT_TRB_TRANSFER {
 \r
   UINT32                  TRBPtrHi;\r
 \r
-  UINT32                  Lenth:24;\r
+  UINT32                  Length:24;\r
   UINT32                  Completecode:8;\r
 \r
   UINT32                  CycleBit:1;\r