+++ /dev/null
-#\r
-# Copyright (c) 2013-2015, ARM Limited. All rights reserved.\r
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-################################################################################\r
-#\r
-# Defines Section - statements that will be processed to create a Makefile.\r
-#\r
-################################################################################\r
-[Defines]\r
- PLATFORM_NAME = ArmJuno\r
- PLATFORM_GUID = ca0722fd-7d3d-45ea-948c-d62b2199807d\r
- PLATFORM_VERSION = 0.1\r
- DSC_SPECIFICATION = 0x00010005\r
- OUTPUT_DIRECTORY = Build/ArmJuno\r
- SUPPORTED_ARCHITECTURES = AARCH64|ARM\r
- BUILD_TARGETS = DEBUG|RELEASE\r
- SKUID_IDENTIFIER = DEFAULT\r
- FLASH_DEFINITION = ArmPlatformPkg/ArmJunoPkg/ArmJuno.fdf\r
-\r
-# On RTSM, most peripherals are VExpress Motherboard peripherals\r
-!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc\r
-\r
-[LibraryClasses.common]\r
- ArmPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/ArmJunoLib/ArmJunoLib.inf\r
- ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
-\r
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf\r
- NorFlashPlatformLib|ArmPlatformPkg/ArmJunoPkg/Library/NorFlashJunoLib/NorFlashJunoLib.inf\r
- EfiResetSystemLib|ArmPkg/Library/ArmPsciResetSystemLib/ArmPsciResetSystemLib.inf\r
-\r
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
-\r
- # USB Requirements\r
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf\r
-\r
-[LibraryClasses.ARM]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
-\r
-[LibraryClasses.AARCH64]\r
- ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
-\r
-[LibraryClasses.common.SEC]\r
- PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf\r
- ExtractGuidedSectionLib|EmbeddedPkg/Library/PrePiExtractGuidedSectionLib/PrePiExtractGuidedSectionLib.inf\r
- LzmaDecompressLib|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
- MemoryAllocationLib|EmbeddedPkg/Library/PrePiMemoryAllocationLib/PrePiMemoryAllocationLib.inf\r
- HobLib|EmbeddedPkg/Library/PrePiHobLib/PrePiHobLib.inf\r
- PrePiHobListPointerLib|ArmPlatformPkg/Library/PrePiHobListPointerLib/PrePiHobListPointerLib.inf\r
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf\r
- PlatformPeiLib|ArmPlatformPkg/PlatformPei/PlatformPeiLib.inf\r
-\r
-[LibraryClasses.common.SEC, LibraryClasses.common.PEIM]\r
- MemoryInitPeiLib|ArmPlatformPkg/MemoryInitPei/MemoryInitPeiLib.inf\r
-\r
-[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]\r
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
-\r
-[BuildOptions]\r
- *_*_*_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmJunoPkg/Include\r
-\r
-################################################################################\r
-#\r
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
-#\r
-################################################################################\r
-\r
-[PcdsFeatureFlag.common]\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE\r
-\r
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
- # It could be set FALSE to save size.\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
-\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdTurnOffUsbLegacySupport|TRUE\r
-\r
-[PcdsFixedAtBuild.common]\r
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Juno"\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmJuno"\r
-\r
- #\r
- # NV Storage PCDs. Use base of 0x08000000 for NOR0\r
- #\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0BFC0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0BFD0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0BFE0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000\r
-\r
- # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000\r
-\r
- # Juno Dual-Cluster profile\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount|6\r
- gArmPlatformTokenSpaceGuid.PcdClusterCount|2\r
-\r
- gArmTokenSpaceGuid.PcdVFPEnabled|1\r
-\r
- #\r
- # ARM PrimeCell\r
- #\r
-\r
- ## PL011 - Serial Terminal\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x7FF80000\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200\r
- gArmPlatformTokenSpaceGuid.PL011UartInteger|4\r
- gArmPlatformTokenSpaceGuid.PL011UartFractional|0\r
-\r
- ## PL031 RealTimeClock\r
- gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000\r
-\r
- # LAN9118 Ethernet Driver\r
- gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x18000000\r
- gEmbeddedTokenSpaceGuid.PcdLan9118DefaultMacAddress|0x1215161822242628\r
-\r
- #\r
- # ARM General Interrupt Controller\r
- #\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C010000\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C02F000\r
-\r
- #\r
- # PLDA PCI Root Complex\r
- #\r
- gArmPlatformTokenSpaceGuid.PcdPciBusMax|255\r
- gArmPlatformTokenSpaceGuid.PcdPciIoBase|0x5f800000\r
- gArmPlatformTokenSpaceGuid.PcdPciIoSize|0x00800000\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Base|0x50000000\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio32Size|0x08000000\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio64Base|0x4000000000\r
- gArmPlatformTokenSpaceGuid.PcdPciMmio64Size|0x100000000\r
-\r
- # List of Device Paths that support BootMonFs\r
- gArmPlatformTokenSpaceGuid.PcdBootMonFsSupportedDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)"\r
-\r
- #\r
- # ARM OS Loader\r
- #\r
- # Support the Linux EFI stub by default\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"EFI Linux from NOR Flash"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/Image"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L"console=ttyAMA0,115200 earlycon=pl011,0x7ff80000 root=/dev/sda1 rootwait verbose debug"\r
-\r
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"\r
-\r
- #\r
- # ARM Architectural Timer Frequency\r
- #\r
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000\r
- gEmbeddedTokenSpaceGuid.PcdMetronomeTickPeriod|1000\r
-\r
-[PcdsPatchableInModule]\r
- # Console Resolution (Full HD)\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|1920\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|1080\r
-\r
-[PcdsDynamicDefault.common]\r
- #\r
- # The size of a dynamic PCD of the (VOID*) type can not be increased at run\r
- # time from its size at build time. Set the "PcdFdtDevicePaths" PCD to a 128\r
- # character "empty" string, to allow to be able to set FDT text device paths\r
- # up to 128 characters long.\r
- #\r
- gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L" "\r
-\r
- # Not all Juno platforms support PCI. This dynamic PCD disables or enable\r
- # PCI support.\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdPciDisableBusEnumeration|TRUE\r
-\r
-################################################################################\r
-#\r
-# Components Section - list of all EDK II Modules needed by this Platform\r
-#\r
-################################################################################\r
-[Components.common]\r
- #\r
- # PEI Phase modules\r
- #\r
- ArmPlatformPkg/PrePi/PeiMPCore.inf\r
-\r
- #\r
- # DXE\r
- #\r
- MdeModulePkg/Core/Dxe/DxeMain.inf {\r
- <LibraryClasses>\r
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
- NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
- }\r
-\r
- #\r
- # Architectural Protocols\r
- #\r
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
-\r
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {\r
- <LibraryClasses>\r
- NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf\r
- }\r
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
-\r
- #\r
- # ACPI Support\r
- #\r
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
- ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf\r
-\r
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
- ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf\r
-\r
- #\r
- # Semi-hosting filesystem\r
- #\r
- ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- # Required by PCI\r
- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
-\r
- #\r
- # PCI Support\r
- #\r
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
- ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
-\r
- #\r
- # SATA Controller\r
- #\r
- MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf\r
- EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf\r
-\r
- #\r
- # Networking stack\r
- #\r
- EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf\r
-\r
- #\r
- # Usb Support\r
- #\r
- MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
- MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
- MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf\r
- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
-\r
- #\r
- # Juno platform driver\r
- #\r
- ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf\r
-\r
- #\r
- # Bds\r
- #\r
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
- ArmPlatformPkg/Bds/Bds.inf\r
-\r
+++ /dev/null
-#\r
-# Copyright (c) 2013-2015, ARM Limited. All rights reserved.\r
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-################################################################################\r
-#\r
-# FD Section\r
-# The [FD] Section is made up of the definition statements and a\r
-# description of what goes into the Flash Device Image. Each FD section\r
-# defines one flash "device" image. A flash device image may be one of\r
-# the following: Removable media bootable image (like a boot floppy\r
-# image,) an Option ROM image (that would be "flashed" into an add-in\r
-# card,) a System "Flash" image (that would be burned into a system's\r
-# flash) or an Update ("Capsule") image that will be used to update and\r
-# existing system flash.\r
-#\r
-################################################################################\r
-\r
-[FD.BL33_AP_UEFI]\r
-BaseAddress = 0xE0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.\r
-Size = 0x000F0000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device\r
-ErasePolarity = 1\r
-\r
-# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
-BlockSize = 0x00001000\r
-NumBlocks = 0xF0\r
-\r
-################################################################################\r
-#\r
-# Following are lists of FD Region layout which correspond to the locations of different\r
-# images within the flash device.\r
-#\r
-# Regions must be defined in ascending order and may not overlap.\r
-#\r
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
-# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
-# "0x" characters. Like:\r
-# Offset|Size\r
-# PcdOffsetCName|PcdSizeCName\r
-# RegionType <FV, DATA, or FILE>\r
-#\r
-################################################################################\r
-\r
-0x00000000|0x000F0000\r
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
-FV = FVMAIN_COMPACT\r
-\r
-\r
-################################################################################\r
-#\r
-# FV Section\r
-#\r
-# [FV] section is used to define what components or modules are placed within a flash\r
-# device file. This section also defines order the components and modules are positioned\r
-# within the image. The [FV] section consists of define statements, set statements and\r
-# module statements.\r
-#\r
-################################################################################\r
-\r
-[FV.FvMain]\r
-BlockSize = 0x40\r
-NumBlocks = 0 # This FV gets compressed so make it just big enough\r
-FvAlignment = 8 # FV alignment and FV attributes setting.\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-FvNameGuid = B73FE497-B92E-416e-8326-45AD0D270092\r
-\r
- APRIORI DXE {\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
- }\r
-\r
- INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
-\r
- #\r
- # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
- #\r
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
- INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
-\r
- #\r
- # ACPI Support\r
- #\r
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
- INF RuleOverride=ACPITABLE ArmPlatformPkg/ArmJunoPkg/AcpiTables/AcpiTables.inf\r
-\r
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- #\r
- # Multiple Console IO support\r
- #\r
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
-\r
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
- INF ArmPkg/Drivers/GenericWatchdogDxe/GenericWatchdogDxe.inf\r
-\r
- # NOR Flash driver\r
- INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
-\r
- # Versatile Express FileSystem\r
- INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- # Required by PCI\r
- INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf\r
-\r
- # FV FileSystem\r
- INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf\r
-\r
- #\r
- # Usb Support\r
- #\r
- INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf\r
- INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf\r
- INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf\r
- INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf\r
- INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf\r
-\r
- #\r
- # PCI Support\r
- #\r
- INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
- INF ArmPlatformPkg/ArmJunoPkg/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
-\r
- #\r
- # SATA Controller\r
- #\r
- INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf\r
- INF EmbeddedPkg/Drivers/SataSiI3132Dxe/SataSiI3132Dxe.inf\r
-\r
- #\r
- # Networking stack\r
- #\r
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf\r
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf\r
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf\r
- INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf\r
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf\r
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf\r
- INF EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf\r
-\r
- #\r
- # UEFI applications\r
- #\r
- INF ShellBinPkg/UefiShell/UefiShell.inf\r
- INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf\r
-\r
- #\r
- # Juno platform driver\r
- #\r
- INF ArmPlatformPkg/ArmJunoPkg/Drivers/ArmJunoDxe/ArmJunoDxe.inf\r
-\r
- #\r
- # Bds\r
- #\r
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
- INF ArmPlatformPkg/Bds/Bds.inf\r
-\r
- #\r
- # FDT installation\r
- #\r
- # The UEFI driver is at the end of the list of the driver to be dispatched\r
- # after the device drivers (eg: Ethernet) to ensure we have support for them.\r
- INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf\r
-\r
-[FV.FVMAIN_COMPACT]\r
-FvAlignment = 8\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
- INF ArmPlatformPkg/PrePi/PeiMPCore.inf\r
-\r
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
- SECTION FV_IMAGE = FVMAIN\r
- }\r
- }\r
-\r
-\r
-################################################################################\r
-#\r
-# Rules are use with the [FV] section's module INF type to define\r
-# how an FFS file is created for a given INF file. The following Rule are the default\r
-# rules for the different module type. User can add the customized rules to define the\r
-# content of the FFS file.\r
-#\r
-################################################################################\r
-\r
-\r
-############################################################################\r
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
-############################################################################\r
-#\r
-#[Rule.Common.DXE_DRIVER]\r
-# FILE DRIVER = $(NAMED_GUID) {\r
-# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
-# COMPRESS PI_STD {\r
-# GUIDED {\r
-# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
-# UI STRING="$(MODULE_NAME)" Optional\r
-# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
-# }\r
-# }\r
-# }\r
-#\r
-############################################################################\r
-\r
-#\r
-# These SEC rules are used for ArmPlatformPkg/PrePi module.\r
-# ArmPlatformPkg/PrePi is declared as a SEC module to make GenFv patch the\r
-# UEFI Firmware to jump to ArmPlatformPkg/PrePi entrypoint\r
-#\r
-[Rule.ARM.SEC]\r
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
- TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.AARCH64.SEC]\r
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {\r
- TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-# A shim specific rule is required to ensure the alignment is 4K.\r
-# Otherwise BaseTools pick up the AArch32 alignment (ie: 32)\r
-[Rule.ARM.SEC.SHIM]\r
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
- TE TE Align = 4K $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.PEI_CORE]\r
- FILE PEI_CORE = $(NAMED_GUID) FIXED {\r
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM]\r
- FILE PEIM = $(NAMED_GUID) FIXED {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM.TIANOCOMPRESSED]\r
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
- }\r
-\r
-[Rule.Common.DXE_CORE]\r
- FILE DXE_CORE = $(NAMED_GUID) {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_RUNTIME_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER.BINARY]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional |.depex\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION.BINARY]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
-\r
-[Rule.Common.USER_DEFINED.ACPITABLE]\r
- FILE FREEFORM = $(NAMED_GUID) {\r
- RAW ACPI |.acpi\r
- RAW ASL |.aml\r
- }\r
+++ /dev/null
-#\r
-# Copyright (c) 2012-2015, ARM Limited. All rights reserved.\r
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-################################################################################\r
-#\r
-# Defines Section - statements that will be processed to create a Makefile.\r
-#\r
-################################################################################\r
-[Defines]\r
- PLATFORM_NAME = ArmVExpressPkg-CTA15-A7\r
- PLATFORM_GUID = 0b511920-978d-4b34-acc0-3d9f8e6f9d81\r
- PLATFORM_VERSION = 0.1\r
- DSC_SPECIFICATION = 0x00010005\r
- OUTPUT_DIRECTORY = Build/ArmVExpress-CTA15-A7\r
- SUPPORTED_ARCHITECTURES = ARM\r
- BUILD_TARGETS = DEBUG|RELEASE\r
- SKUID_IDENTIFIER = DEFAULT\r
- FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA15-A7.fdf\r
-\r
- DEFINE EDK2_SKIP_PEICORE = 1\r
- DEFINE ARM_BIGLITTLE_TC2 = 1 # We build for the TC2 hardware by default\r
-\r
-!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc\r
-\r
-[LibraryClasses.common]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
- ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf\r
-\r
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf\r
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf\r
-\r
- #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf\r
-\r
- # ARM General Interrupt Driver in Secure and Non-secure\r
- ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicLib.inf\r
-\r
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/HdLcdArmVExpressLib/HdLcdArmVExpressLib.inf\r
-\r
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
- ArmSmcLib|ArmPkg/Library/ArmSmcLib/ArmSmcLib.inf\r
-\r
-[BuildOptions]\r
-!ifdef ARM_BIGLITTLE_TC2\r
- *_*_ARM_ARCHCC_FLAGS = -DARM_BIGLITTLE_TC2=1\r
- *_*_ARM_PP_FLAGS = -DARM_BIGLITTLE_TC2=1\r
-!endif\r
-\r
- RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7\r
-\r
- GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7\r
-\r
- XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA15-A7\r
-\r
-################################################################################\r
-#\r
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
-#\r
-################################################################################\r
-\r
-[PcdsFeatureFlag.common]\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE\r
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE\r
-\r
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
- # It could be set FALSE to save size.\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
-\r
-[PcdsFixedAtBuild.common]\r
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress-CTA15-A7"\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount|5\r
-\r
- #\r
- # NV Storage PCDs. Use base of 0x0C000000 for NOR1\r
- #\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000\r
-\r
- gArmTokenSpaceGuid.PcdVFPEnabled|1\r
-\r
- # Stacks for MPCores in Secure World\r
- # SRAM (CS1) is only available between 0x14000000 and 0x14001000 on the model\r
- # ZBT SRAM is available between 0x2E000000 and 0x2E010000 on the model\r
-!ifdef ARM_BIGLITTLE_TC2\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x17000000\r
-!else\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E000000\r
-!endif\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x8000\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x1000\r
- # Share Monitor stacks with Secure World\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0\r
-\r
- # System Memory (1GB) - An additional 1GB will be added if UEFI is running on a 2GB Test Chip\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000\r
-\r
-!ifdef ARM_BIGLITTLE_TC2\r
- # TC2 Dual-Cluster profile\r
- gArmPlatformTokenSpaceGuid.PcdClusterCount|2\r
-\r
- # Core Ids and Gic values\r
- # A15_0 = 0x000, GicCoreId = 0\r
- # A15_1 = 0x001, GicCoreId = 1\r
- # A7_0 = 0x100, GicCoreId = 2\r
- # A7_1 = 0x101, GicCoreId = 3\r
- # A7_2 = 0x102, GicCoreId = 4\r
- gArmTokenSpaceGuid.PcdArmPrimaryCore|0x100\r
-!endif\r
-\r
- #\r
- # ARM PrimeCell\r
- #\r
-\r
- ## SP805 Watchdog - Motherboard Watchdog\r
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000\r
-\r
- ## PL011 - Serial Terminal\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1C090000\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
-\r
- ## PL031 RealTimeClock\r
- gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000\r
-\r
-!ifdef ARM_BIGLITTLE_TC2\r
- ## PL111 Lcd & HdLcd\r
- gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000\r
- gArmPlatformTokenSpaceGuid.PcdArmHdLcdBase|0x2B000000\r
- gArmVExpressTokenSpaceGuid.PcdHdLcdVideoModeOscId|5\r
-!endif\r
-\r
- #\r
- # PL180 MMC/SD card controller\r
- #\r
- gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048\r
- gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000\r
-\r
-\r
- #\r
- # ARM General Interrupt Controller\r
- #\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
-\r
- # ISP1761 USB OTG Controller\r
- gEmbeddedTokenSpaceGuid.PcdIsp1761BaseAddress|0x1B000000\r
-\r
- # Ethernet (SMSC LAN9118)\r
- gEmbeddedTokenSpaceGuid.PcdLan9118DxeBaseAddress|0x1A000000\r
-\r
- #\r
- # Define the device path to the FDT for the platform\r
- #\r
- gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/ca15a7"\r
-\r
- #\r
- # ARM OS Loader\r
- #\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from NorFlash"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"Fv(73DCB643-3862-4904-9076-A94AF1890243)/LinuxLoader.efi"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L"VenHw(E7223039-5836-41E1-B542-D7EC736C5E59)/kernel -c \"console=ttyAMA0,38400 earlyprintk debug verbose\""\r
-\r
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)\r
- # PL111 - CLCD\r
- #gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"\r
- # HDLCD\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(CE660500-824D-11E0-AC72-0002A5D5C51B)"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"\r
-\r
- #\r
- # ARM Architectural Timer Frequency\r
- #\r
-!ifdef ARM_BIGLITTLE_TC2\r
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|24000000\r
-!else\r
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|10000000\r
-!endif\r
-\r
-################################################################################\r
-#\r
-# Components Section - list of all EDK II Modules needed by this Platform\r
-#\r
-################################################################################\r
-[Components.common]\r
- #\r
- # PEI Phase modules\r
- #\r
- ArmPlatformPkg/PrePi/PeiMPCore.inf {\r
- <LibraryClasses>\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
- ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA15-A7/ArmVExpressLib.inf\r
- }\r
-\r
- #\r
- # DXE\r
- #\r
- MdeModulePkg/Core/Dxe/DxeMain.inf {\r
- <LibraryClasses>\r
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
- NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
- }\r
-\r
- #\r
- # Architectural Protocols\r
- #\r
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {\r
- <LibraryClasses>\r
- NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf\r
- }\r
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
-\r
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
- #ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf\r
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
-\r
- #\r
- # Platform\r
- #\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf\r
-\r
- #\r
- # Filesystems\r
- #\r
-!ifndef ARM_BIGLITTLE_TC2\r
- ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
-!endif\r
-\r
- #\r
- # Multimedia Card Interface\r
- #\r
- EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
- ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
-\r
- # SMSC LAN 9118\r
- EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
-\r
- #\r
- # Bds\r
- #\r
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
- ArmPlatformPkg/Bds/Bds.inf\r
+++ /dev/null
-#\r
-# Copyright (c) 2012-2015, ARM Limited. All rights reserved.\r
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-################################################################################\r
-#\r
-# FD Section\r
-# The [FD] Section is made up of the definition statements and a\r
-# description of what goes into the Flash Device Image. Each FD section\r
-# defines one flash "device" image. A flash device image may be one of\r
-# the following: Removable media bootable image (like a boot floppy\r
-# image,) an Option ROM image (that would be "flashed" into an add-in\r
-# card,) a System "Flash" image (that would be burned into a system's\r
-# flash) or an Update ("Capsule") image that will be used to update and\r
-# existing system flash.\r
-#\r
-################################################################################\r
-\r
-[FD.ARM_VEXPRESS_CTA15A7_EFI]\r
-BaseAddress = 0xB0000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in remapped DRAM.\r
-Size = 0x000C8000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device\r
-ErasePolarity = 1\r
-BlockSize = 0x00001000\r
-NumBlocks = 0xC8\r
-\r
-0x00000000|0x000C8000\r
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
-FV = FVMAIN_COMPACT\r
-\r
-################################################################################\r
-#\r
-# FV Section\r
-#\r
-# [FV] section is used to define what components or modules are placed within a flash\r
-# device file. This section also defines order the components and modules are positioned\r
-# within the image. The [FV] section consists of define statements, set statements and\r
-# module statements.\r
-#\r
-################################################################################\r
-[FV.FvMain]\r
-BlockSize = 0x40\r
-NumBlocks = 0 # This FV gets compressed so make it just big enough\r
-FvAlignment = 8 # FV alignment and FV attributes setting.\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-FvNameGuid = 73dcb643-3862-4904-9076-a94af1890243\r
-\r
- INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
-\r
- #\r
- # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
- #\r
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
- INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- #\r
- # Multiple Console IO support\r
- #\r
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
-\r
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
- INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
- #INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
- INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/HdLcdGraphicsOutputDxe.inf\r
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
-\r
- #\r
- # Platform\r
- #\r
- INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmHwDxe.inf\r
-\r
- #\r
- # Multimedia Card Interface\r
- #\r
- INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
- INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
-\r
- #\r
- # Filesystems\r
- #\r
-!ifndef $(ARM_BIGLITTLE_TC2)\r
- INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
-!endif\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- # Versatile Express FileSystem\r
- INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf\r
-\r
- #\r
- # USB support\r
- #\r
- INF EmbeddedPkg/Drivers/Isp1761UsbDxe/Isp1761UsbDxe.inf\r
-\r
- #\r
- # Android Fastboot\r
- #\r
- INF EmbeddedPkg/Application/AndroidFastboot/AndroidFastbootApp.inf\r
- INF EmbeddedPkg/Drivers/AndroidFastbootTransportUsbDxe/FastbootTransportUsbDxe.inf\r
- INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressFastBootDxe/ArmVExpressFastBootDxe.inf\r
-\r
- # ACPI Support\r
- INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
-\r
- #\r
- # Networking stack\r
- #\r
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf\r
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf\r
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf\r
- INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf\r
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf\r
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf\r
- INF EmbeddedPkg/Drivers/Lan9118Dxe/Lan9118Dxe.inf\r
-\r
- #\r
- # UEFI application\r
- #\r
- INF ShellBinPkg/UefiShell/UefiShell.inf\r
-\r
- #\r
- # Bds\r
- #\r
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
- INF ArmPlatformPkg/Bds/Bds.inf\r
-\r
- # Legacy Linux Loader\r
- INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf\r
-\r
- # FV Filesystem\r
- INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf\r
-\r
- #\r
- # FDT installation\r
- #\r
- # The UEFI driver is at the end of the list of the driver to be dispatched\r
- # after the device drivers (eg: Ethernet) to ensure we have support for them.\r
- INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf\r
-\r
- # Example to add a Device Tree to the Firmware Volume\r
- #FILE FREEFORM = PCD(gArmVExpressTokenSpaceGuid.PcdFdtVExpressHwA15x2A7x3) {\r
- # SECTION RAW = ArmPlatformPkg/ArmVExpressPkg/Fdts/vexpress-v2p-ca15_a7.dtb\r
- #}\r
-\r
-[FV.FVMAIN_COMPACT]\r
-FvBaseAddress = 0xB0000000\r
-FvForceRebase = TRUE\r
-FvAlignment = 8\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
- INF ArmPlatformPkg/PrePi/PeiMPCore.inf\r
-\r
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
- SECTION FV_IMAGE = FVMAIN\r
- }\r
- }\r
-\r
-\r
-################################################################################\r
-#\r
-# Rules are use with the [FV] section's module INF type to define\r
-# how an FFS file is created for a given INF file. The following Rule are the default\r
-# rules for the different module type. User can add the customized rules to define the\r
-# content of the FFS file.\r
-#\r
-################################################################################\r
-\r
-\r
-############################################################################\r
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
-############################################################################\r
-#\r
-#[Rule.Common.DXE_DRIVER]\r
-# FILE DRIVER = $(NAMED_GUID) {\r
-# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
-# COMPRESS PI_STD {\r
-# GUIDED {\r
-# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
-# UI STRING="$(MODULE_NAME)" Optional\r
-# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
-# }\r
-# }\r
-# }\r
-#\r
-############################################################################\r
-\r
-[Rule.Common.SEC]\r
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
- TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.PEI_CORE]\r
- FILE PEI_CORE = $(NAMED_GUID) {\r
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM]\r
- FILE PEIM = $(NAMED_GUID) {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM.TIANOCOMPRESSED]\r
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
- }\r
-\r
-[Rule.Common.DXE_CORE]\r
- FILE DXE_CORE = $(NAMED_GUID) {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_RUNTIME_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER.BINARY]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional |.depex\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION.BINARY]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-################################################################################\r
-#\r
-# Defines Section - statements that will be processed to create a Makefile.\r
-#\r
-################################################################################\r
-[Defines]\r
- PLATFORM_NAME = ArmVExpress-FVP-AArch64\r
- PLATFORM_GUID = 0de70077-9b3b-43bf-ba38-0ea37d77141b\r
- PLATFORM_VERSION = 0.1\r
- DSC_SPECIFICATION = 0x00010005\r
- OUTPUT_DIRECTORY = Build/ArmVExpress-FVP-AArch64\r
- SUPPORTED_ARCHITECTURES = AARCH64\r
- BUILD_TARGETS = DEBUG|RELEASE\r
- SKUID_IDENTIFIER = DEFAULT\r
- FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-FVP-AArch64.fdf\r
-\r
-!ifndef ARM_FVP_RUN_NORFLASH\r
- DEFINE EDK2_SKIP_PEICORE=1\r
-!endif\r
-\r
-\r
-!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc\r
-\r
-[LibraryClasses.common]\r
- ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexAEMv8Lib/ArmCortexAEMv8Lib.inf\r
- ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf\r
-\r
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf\r
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf\r
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf\r
-\r
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
-\r
- # Virtio Support\r
- VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf\r
- VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf\r
-\r
-[LibraryClasses.common.SEC]\r
- ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf\r
- ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf\r
- ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf\r
-\r
-[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]\r
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
-\r
-[BuildOptions]\r
- GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
-\r
-\r
-################################################################################\r
-#\r
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
-#\r
-################################################################################\r
-\r
-[PcdsFeatureFlag.common]\r
-\r
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
- # It could be set FALSE to save size.\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
-\r
-[PcdsFixedAtBuild.common]\r
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Fixed Virtual Platform"\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ARM-FVP"\r
-\r
- # Up to 8 cores on Base models. This works fine if model happens to have less.\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount|8\r
- gArmPlatformTokenSpaceGuid.PcdClusterCount|2\r
-\r
- #\r
- # NV Storage PCDs. Use base of 0x0C000000 for NOR1\r
- #\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000\r
-\r
- gArmTokenSpaceGuid.PcdVFPEnabled|1\r
-\r
- # FVP models can have 2 clusters with 4 cpus each\r
- # Stacks for MPCores in Secure World\r
- # Trusted SRAM (DRAM on Foundation model)\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x04000000\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize|0x800\r
-\r
- # Stacks for MPCores in Normal World\r
- # Non-Trusted SRAM\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000\r
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecondaryStackSize|0x1000\r
-\r
- # System Memory (2GB - 16MB of Trusted DRAM at the top of the 32bit address space)\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x7F000000\r
-\r
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
-\r
- #\r
- # ARM Pcds\r
- #\r
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000\r
-\r
- ## Trustzone enable (to make the transition from EL3 to NS EL2 in ArmPlatformPkg/Sec)\r
- gArmTokenSpaceGuid.PcdTrustzoneSupport|TRUE\r
-\r
- #\r
- # ARM PrimeCell\r
- #\r
-\r
- ## SP805 Watchdog - Motherboard Watchdog at 24MHz\r
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000\r
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogClockFrequencyInHz|24000000\r
-\r
- ## PL011 - Serial Terminal\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
-\r
- ## PL031 RealTimeClock\r
- gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000\r
-\r
- ## PL111 Versatile Express Motherboard controller\r
- gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000\r
-\r
- ## PL180 MMC/SD card controller\r
- gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048\r
- gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000\r
-\r
- #\r
- # ARM General Interrupt Controller\r
- #\r
-!ifdef ARM_FVP_LEGACY_GICV2_LOCATION\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
-!else\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x2f000000\r
- gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x2f100000\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000\r
-!endif\r
-\r
- #\r
- # ARM OS Loader\r
- #\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SemiHosting"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"Fv(87940482-FC81-41C3-87E6-399CF85AC8A0)/LinuxLoader.efi"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/Image -f VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/filesystem.cpio.gz -c \"console=ttyAMA0 earlycon=pl011,0x1c090000 debug user_debug=31 loglevel=9\""\r
-\r
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"\r
-\r
- #\r
- # ARM Architectural Timer Frequency\r
- #\r
- # Set tick frequency value to 100Mhz\r
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000\r
-\r
-[PcdsDynamicDefault.common]\r
- #\r
- # The size of a dynamic PCD of the (VOID*) type can not be increased at run\r
- # time from its size at build time. Set the "PcdFdtDevicePaths" PCD to a 128\r
- # character "empty" string, to allow to be able to set FDT text device paths\r
- # up to 128 characters long.\r
- #\r
- gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L" "\r
-\r
-################################################################################\r
-#\r
-# Components Section - list of all EDK II Modules needed by this Platform\r
-#\r
-################################################################################\r
-[Components.common]\r
-\r
- #\r
- # SEC\r
- #\r
- ArmPlatformPkg/Sec/Sec.inf {\r
- <LibraryClasses>\r
- # Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
- }\r
-\r
- #\r
- # PEI Phase modules\r
- #\r
-!ifdef EDK2_SKIP_PEICORE\r
- # UEFI is placed in RAM by bootloader\r
- ArmPlatformPkg/PrePi/PeiMPCore.inf {\r
- <LibraryClasses>\r
- ArmLib|ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf\r
- ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf\r
- }\r
-!else\r
- # UEFI lives in FLASH and copies itself to RAM\r
- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf\r
- MdeModulePkg/Core/Pei/PeiMain.inf\r
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
- <LibraryClasses>\r
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
- }\r
- ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
- ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
- ArmPkg/Drivers/CpuPei/CpuPei.inf\r
- IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
- Nt32Pkg/BootModePei/BootModePei.inf\r
- MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
- <LibraryClasses>\r
- NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
- }\r
-!endif\r
-\r
- #\r
- # DXE\r
- #\r
- MdeModulePkg/Core/Dxe/DxeMain.inf {\r
- <LibraryClasses>\r
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
- NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
- }\r
-\r
- #\r
- # Architectural Protocols\r
- #\r
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {\r
- <LibraryClasses>\r
- NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf\r
- }\r
- SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r
-!else\r
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
-!endif\r
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {\r
- <LibraryClasses>\r
- NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf\r
- }\r
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
-\r
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashAuthenticatedDxe.inf\r
-!else\r
- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
-!endif\r
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
-\r
- #\r
- # Semi-hosting filesystem\r
- #\r
- ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
-\r
- #\r
- # Multimedia Card Interface\r
- #\r
- EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
- ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
-\r
- #\r
- # Platform Driver\r
- #\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf\r
- OvmfPkg/VirtioBlkDxe/VirtioBlk.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- #\r
- # Bds\r
- #\r
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
-!if $(USE_ARM_BDS) == TRUE\r
- ArmPlatformPkg/Bds/Bds.inf\r
-!else\r
- MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
- IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
-!endif\r
+++ /dev/null
-#\r
-# Copyright (c) 2011 - 2015, ARM Limited. All rights reserved.\r
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-################################################################################\r
-#\r
-# FD Section\r
-# The [FD] Section is made up of the definition statements and a\r
-# description of what goes into the Flash Device Image. Each FD section\r
-# defines one flash "device" image. A flash device image may be one of\r
-# the following: Removable media bootable image (like a boot floppy\r
-# image,) an Option ROM image (that would be "flashed" into an add-in\r
-# card,) a System "Flash" image (that would be burned into a system's\r
-# flash) or an Update ("Capsule") image that will be used to update and\r
-# existing system flash.\r
-#\r
-################################################################################\r
-\r
-[FD.FVP_AARCH64_EFI_SEC]\r
-BaseAddress = 0x00000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in SecureROM.\r
-Size = 0x04000000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the device (64MiB).\r
-ErasePolarity = 1\r
-\r
-# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
-BlockSize = 0x00001000\r
-NumBlocks = 0x4000\r
-\r
-################################################################################\r
-#\r
-# Following are lists of FD Region layout which correspond to the locations of different\r
-# images within the flash device.\r
-#\r
-# Regions must be defined in ascending order and may not overlap.\r
-#\r
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
-# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
-# "0x" characters. Like:\r
-# Offset|Size\r
-# PcdOffsetCName|PcdSizeCName\r
-# RegionType <FV, DATA, or FILE>\r
-#\r
-################################################################################\r
-\r
-0x00000000|0x00080000\r
-gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize\r
-FV = FVMAIN_SEC\r
-\r
-[FD.FVP_AARCH64_EFI]\r
-!ifdef ARM_FVP_RUN_NORFLASH\r
-BaseAddress = 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in Flash0.\r
-!else\r
-BaseAddress = 0x88000000|gArmTokenSpaceGuid.PcdFdBaseAddress # UEFI in DRAM + 128MB.\r
-!endif\r
-Size = 0x04000000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the device (64MiB).\r
-ErasePolarity = 1\r
-\r
-# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
-BlockSize = 0x00001000\r
-NumBlocks = 0x4000\r
-\r
-0x00000000|0x00280000\r
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
-FV = FVMAIN_COMPACT\r
-\r
-################################################################################\r
-#\r
-# FV Section\r
-#\r
-# [FV] section is used to define what components or modules are placed within a flash\r
-# device file. This section also defines order the components and modules are positioned\r
-# within the image. The [FV] section consists of define statements, set statements and\r
-# module statements.\r
-#\r
-################################################################################\r
-\r
-[FV.FVMAIN_SEC]\r
-FvBaseAddress = 0x0 # Secure ROM\r
-FvForceRebase = TRUE\r
-FvAlignment = 16\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
- INF ArmPlatformPkg/Sec/Sec.inf\r
-\r
-\r
-[FV.FvMain]\r
-BlockSize = 0x40\r
-NumBlocks = 0 # This FV gets compressed so make it just big enough\r
-FvAlignment = 16 # FV alignment and FV attributes setting.\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-FvNameGuid = 87940482-fc81-41c3-87e6-399cf85ac8a0\r
-\r
- APRIORI DXE {\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
- }\r
-\r
- INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
-\r
- #\r
- # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
- #\r
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf\r
-!endif\r
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
- INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- #\r
- # Multiple Console IO support\r
- #\r
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
-\r
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
-!if $(SECURE_BOOT_ENABLE) == TRUE\r
- INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashAuthenticatedDxe.inf\r
-!else\r
- INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
-!endif\r
- INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
-\r
- #\r
- # Semi-hosting filesystem\r
- #\r
- INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- #\r
- # Multimedia Card Interface\r
- #\r
- INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
- INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
-\r
- #\r
- # Platform Driver\r
- #\r
- INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf\r
- INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf\r
-\r
- #\r
- # UEFI application (Shell Embedded Boot Loader)\r
- #\r
- INF ShellBinPkg/UefiShell/UefiShell.inf\r
-\r
- #\r
- # Bds\r
- #\r
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
-!if $(USE_ARM_BDS) == TRUE\r
- INF ArmPlatformPkg/Bds/Bds.inf\r
-!else\r
- INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf\r
- INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
- INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
-\r
- #\r
- # TianoCore logo (splash screen)\r
- #\r
- FILE FREEFORM = PCD(gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLogoFile) {\r
- SECTION RAW = MdeModulePkg/Logo/Logo.bmp\r
- }\r
-!endif\r
-\r
- # Legacy Linux Loader\r
- INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf\r
-\r
- # FV Filesystem\r
- INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf\r
-\r
- #\r
- # FDT installation\r
- #\r
- # The UEFI driver is at the end of the list of the driver to be dispatched\r
- # after the device drivers (eg: Ethernet) to ensure we have support for them.\r
- INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf\r
-\r
-!ifdef $(DTB_DIR)\r
- #\r
- # Embed flattened device tree (FDT) images for all known\r
- # variants of this platform\r
- #\r
- FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV2) {\r
- $(DTB_DIR)/fvp-base-gicv2-psci.dtb\r
- }\r
- FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV2Legacy) {\r
- $(DTB_DIR)/fvp-base-gicv2legacy-psci.dtb\r
- }\r
- FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpBaseAEMv8x4GicV3) {\r
- $(DTB_DIR)/fvp-base-gicv3-psci.dtb\r
- }\r
- FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV2) {\r
- $(DTB_DIR)/fvp-foundation-gicv2-psci.dtb\r
- }\r
- FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV2Legacy) {\r
- $(DTB_DIR)/fvp-foundation-gicv2legacy-psci.dtb\r
- }\r
- FILE RAW = PCD (gArmVExpressTokenSpaceGuid.PcdFdtFvpFoundationGicV3) {\r
- $(DTB_DIR)/fvp-foundation-gicv3-psci.dtb\r
- }\r
-!endif\r
-\r
-[FV.FVMAIN_COMPACT]\r
-FvAlignment = 16\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
-!if $(EDK2_SKIP_PEICORE) == 1\r
- INF ArmPlatformPkg/PrePi/PeiMPCore.inf\r
-!else\r
- INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf\r
- INF MdeModulePkg/Core/Pei/PeiMain.inf\r
- INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
- INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
- INF ArmPkg/Drivers/CpuPei/CpuPei.inf\r
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
- INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
- INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
- INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
-!endif\r
-\r
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
- SECTION FV_IMAGE = FVMAIN\r
- }\r
- }\r
-\r
-\r
-################################################################################\r
-#\r
-# Rules are use with the [FV] section's module INF type to define\r
-# how an FFS file is created for a given INF file. The following Rule are the default\r
-# rules for the different module type. User can add the customized rules to define the\r
-# content of the FFS file.\r
-#\r
-################################################################################\r
-\r
-\r
-############################################################################\r
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
-############################################################################\r
-#\r
-#[Rule.Common.DXE_DRIVER]\r
-# FILE DRIVER = $(NAMED_GUID) {\r
-# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
-# COMPRESS PI_STD {\r
-# GUIDED {\r
-# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
-# UI STRING="$(MODULE_NAME)" Optional\r
-# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
-# }\r
-# }\r
-# }\r
-#\r
-############################################################################\r
-\r
-[Rule.Common.SEC]\r
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED FIXED {\r
- TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.PEI_CORE]\r
- FILE PEI_CORE = $(NAMED_GUID) FIXED {\r
- TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM]\r
- FILE PEIM = $(NAMED_GUID) FIXED {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- TE TE Align = Auto $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM.TIANOCOMPRESSED]\r
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
- }\r
-\r
-[Rule.Common.DXE_CORE]\r
- FILE DXE_CORE = $(NAMED_GUID) {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_RUNTIME_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER.BINARY]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional |.depex\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION.BINARY]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#\r
-\r
-################################################################################\r
-#\r
-# Defines Section - statements that will be processed to create a Makefile.\r
-#\r
-################################################################################\r
-[Defines]\r
- PLATFORM_NAME = ArmVExpressPkg-RTSM-A15_MPCore\r
- PLATFORM_GUID = 3a91a0f8-3af4-409d-a71d-a199dc134357\r
- PLATFORM_VERSION = 0.1\r
- DSC_SPECIFICATION = 0x00010005\r
- OUTPUT_DIRECTORY = Build/ArmVExpress-RTSM-A15_MPCore\r
- SUPPORTED_ARCHITECTURES = ARM\r
- BUILD_TARGETS = DEBUG|RELEASE\r
- SKUID_IDENTIFIER = DEFAULT\r
- FLASH_DEFINITION = ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A15_MPCore.fdf\r
-\r
-!include ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc\r
-\r
-[LibraryClasses.common]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
- ArmCpuLib|ArmPkg/Drivers/ArmCpuLib/ArmCortexA15Lib/ArmCortexA15Lib.inf\r
- ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf\r
-\r
- ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf\r
- NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf\r
- LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf\r
-\r
- #DebugAgentTimerLib|ArmPlatformPkg/ArmVExpressPkg/Library/DebugAgentTimerLib/DebugAgentTimerLib.inf\r
-\r
- TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf\r
-\r
- # Virtio Support\r
- VirtioLib|OvmfPkg/Library/VirtioLib/VirtioLib.inf\r
- VirtioMmioDeviceLib|OvmfPkg/Library/VirtioMmioDeviceLib/VirtioMmioDeviceLib.inf\r
-\r
-[LibraryClasses.common.SEC]\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf\r
- ArmPlatformSecLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSecLibRTSM/ArmVExpressSecLib.inf\r
- ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLibSec.inf\r
-\r
-[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]\r
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
-\r
-[BuildOptions]\r
- RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
-\r
- GCC:*_*_ARM_PLATFORM_FLAGS == -mcpu=cortex-a15 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
-\r
- XCODE:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM\r
-\r
-################################################################################\r
-#\r
-# Pcd Section - list of all EDK II PCD Entries defined by this Platform\r
-#\r
-################################################################################\r
-\r
-[PcdsFeatureFlag.common]\r
-!ifdef EDK2_SKIP_PEICORE\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE\r
- gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE\r
-!endif\r
-\r
- ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.\r
- # It could be set FALSE to save size.\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
-\r
-[PcdsFixedAtBuild.common]\r
- gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"\r
- gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"ArmVExpress-RTSM"\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCoreCount|2\r
-\r
- #\r
- # NV Storage PCDs. Use base of 0x0C000000 for NOR1\r
- #\r
-!if $(EDK2_ARMVE_SUPPORT_QEMU) == 1\r
- # QEMU only models a single flash block size, so use larger blocks\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FF00000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00040000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FF40000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00040000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FF80000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00040000\r
-!else\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|0x0FFC0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize|0x00010000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|0x0FFD0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize|0x00010000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|0x0FFE0000\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize|0x00010000\r
-!endif\r
-\r
- gArmTokenSpaceGuid.PcdVFPEnabled|1\r
-\r
- # Stacks for MPCores in Secure World\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0x2E009000\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x1000\r
-\r
- # Stacks for MPCores in Monitor Mode\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0x2E008000\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100\r
-\r
- # Stacks for MPCores in Normal World\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0x2E000000\r
- gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x4000\r
-\r
- # System Memory (1GB)\r
- gArmTokenSpaceGuid.PcdSystemMemoryBase|0x80000000\r
- gArmTokenSpaceGuid.PcdSystemMemorySize|0x40000000\r
-\r
- # Size of the region used by UEFI in permanent memory (Reserved 64MB)\r
- gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x04000000\r
-\r
- #\r
- # ARM Pcds\r
- #\r
- gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000\r
-\r
- #\r
- # ARM PrimeCell\r
- #\r
-\r
- ## SP805 Watchdog - Motherboard Watchdog\r
- gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x1C0F0000\r
-\r
- ## PL011 - Serial Terminal\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000\r
- gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|38400\r
-\r
- ## PL031 RealTimeClock\r
- gArmPlatformTokenSpaceGuid.PcdPL031RtcBase|0x1C170000\r
-\r
- ## PL111 Versatile Express Motherboard controller\r
- gArmPlatformTokenSpaceGuid.PcdPL111LcdBase|0x1C1F0000\r
-\r
- ## PL180 MMC/SD card controller\r
- gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress|0x1C010048\r
- gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress|0x1C050000\r
-\r
- #\r
- # ARM General Interrupt Controller\r
- #\r
- gArmTokenSpaceGuid.PcdGicDistributorBase|0x2C001000\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C002000\r
-\r
- #\r
- # ARM OS Loader\r
- #\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SemiHosting"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"Fv(12C68BE9-0996-49D3-8C5B-4957379027EE)/LinuxLoader.efi"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|L"VenHw(C5B9C74A-6D72-4719-99AB-C59F199091EB)/Image -c \"console=ttyAMA0,38400 earlyprintk debug verbose\""\r
-\r
- # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"\r
- gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(38400,8,N,1)/VenPcAnsi()"\r
-\r
- #\r
- # ARM Architectural Timer Frequency\r
- #\r
- gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|100000000\r
-\r
-[PcdsDynamicDefault.common]\r
- #\r
- # The size of a dynamic PCD of the (VOID*) type can not be increased at run\r
- # time from its size at build time. Set the "PcdFdtDevicePaths" PCD to a 128\r
- # character "empty" string, to allow to be able to set FDT text device paths\r
- # up to 128 characters long.\r
- #\r
- gEmbeddedTokenSpaceGuid.PcdFdtDevicePaths|L" "\r
-\r
-################################################################################\r
-#\r
-# Components Section - list of all EDK II Modules needed by this Platform\r
-#\r
-################################################################################\r
-[Components.common]\r
-\r
- #\r
- # SEC\r
- #\r
- ArmPlatformPkg/Sec/Sec.inf {\r
- <LibraryClasses>\r
- # Use the implementation which set the Secure bits\r
- ArmGicLib|ArmPkg/Drivers/ArmGic/ArmGicSecLib.inf\r
- }\r
-\r
- #\r
- # PEI Phase modules\r
- #\r
-!ifdef EDK2_SKIP_PEICORE\r
- ArmPlatformPkg/PrePi/PeiMPCore.inf {\r
- <LibraryClasses>\r
- ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
- ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf\r
- }\r
-!else\r
- ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf\r
- MdeModulePkg/Core/Pei/PeiMain.inf\r
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
- <LibraryClasses>\r
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
- }\r
- ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
- ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
- ArmPkg/Drivers/CpuPei/CpuPei.inf\r
- IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
- Nt32Pkg/BootModePei/BootModePei.inf\r
- MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
- MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
- <LibraryClasses>\r
- NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
- }\r
-!endif\r
-\r
- #\r
- # DXE\r
- #\r
- MdeModulePkg/Core/Dxe/DxeMain.inf {\r
- <LibraryClasses>\r
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
- NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf\r
- }\r
-\r
- #\r
- # Architectural Protocols\r
- #\r
- ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
- MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {\r
- <LibraryClasses>\r
- NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf\r
- }\r
- MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
- MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
-\r
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
- ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
- ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
- ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
-\r
- #\r
- # Semi-hosting filesystem\r
- #\r
- ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
-\r
- #\r
- # Multimedia Card Interface\r
- #\r
- EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
- ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
-\r
- #\r
- # Platform Driver\r
- #\r
- ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf\r
- OvmfPkg/VirtioBlkDxe/VirtioBlk.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- #\r
- # Bds\r
- #\r
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
- ArmPlatformPkg/Bds/Bds.inf\r
+++ /dev/null
-#\r
-# Copyright (c) 2011-2015, ARM Limited. All rights reserved.\r
-# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-\r
-################################################################################\r
-#\r
-# FD Section\r
-# The [FD] Section is made up of the definition statements and a\r
-# description of what goes into the Flash Device Image. Each FD section\r
-# defines one flash "device" image. A flash device image may be one of\r
-# the following: Removable media bootable image (like a boot floppy\r
-# image,) an Option ROM image (that would be "flashed" into an add-in\r
-# card,) a System "Flash" image (that would be burned into a system's\r
-# flash) or an Update ("Capsule") image that will be used to update and\r
-# existing system flash.\r
-#\r
-################################################################################\r
-\r
-[FD.RTSM_VE_Cortex-A15_MPCore_EFI]\r
-BaseAddress = 0x08000000|gArmTokenSpaceGuid.PcdFdBaseAddress # The base address of the Firmware in NOR Flash.\r
-Size = 0x00300000|gArmTokenSpaceGuid.PcdFdSize # The size in bytes of the FLASH Device\r
-ErasePolarity = 1\r
-\r
-# This one is tricky, it must be: BlockSize * NumBlocks = Size\r
-BlockSize = 0x00001000\r
-NumBlocks = 0x300\r
-\r
-################################################################################\r
-#\r
-# Following are lists of FD Region layout which correspond to the locations of different\r
-# images within the flash device.\r
-#\r
-# Regions must be defined in ascending order and may not overlap.\r
-#\r
-# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
-# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
-# "0x" characters. Like:\r
-# Offset|Size\r
-# PcdOffsetCName|PcdSizeCName\r
-# RegionType <FV, DATA, or FILE>\r
-#\r
-################################################################################\r
-\r
-0x00000000|0x00080000\r
-gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize\r
-FV = FVMAIN_SEC\r
-\r
-0x00080000|0x00280000\r
-gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize\r
-FV = FVMAIN_COMPACT\r
-\r
-\r
-################################################################################\r
-#\r
-# FV Section\r
-#\r
-# [FV] section is used to define what components or modules are placed within a flash\r
-# device file. This section also defines order the components and modules are positioned\r
-# within the image. The [FV] section consists of define statements, set statements and\r
-# module statements.\r
-#\r
-################################################################################\r
-\r
-[FV.FVMAIN_SEC]\r
-FvAlignment = 8\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
- INF ArmPlatformPkg/Sec/Sec.inf\r
-\r
-\r
-[FV.FvMain]\r
-BlockSize = 0x40\r
-NumBlocks = 0 # This FV gets compressed so make it just big enough\r
-FvAlignment = 8 # FV alignment and FV attributes setting.\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-FvNameGuid = 12c68be9-0996-49d3-8c5b-4957379027ee\r
-\r
- APRIORI DXE {\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
- }\r
-\r
- INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
- INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
-\r
- #\r
- # PI DXE Drivers producing Architectural Protocols (EFI Services)\r
- #\r
- INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf\r
- INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
- INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
- INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
- INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf\r
- INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf\r
- INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
- INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf\r
- INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf\r
- INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf\r
-\r
- INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
-\r
- #\r
- # Networking stack\r
- #\r
- INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf\r
- INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf\r
- INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf\r
- INF MdeModulePkg/Universal/Network/VlanConfigDxe/VlanConfigDxe.inf\r
- INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf\r
- INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf\r
- INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf\r
-\r
- #\r
- # Multiple Console IO support\r
- #\r
- INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
- INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
- INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
- INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
- INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf\r
-\r
- INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf\r
- INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf\r
- INF ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf\r
- INF ArmPlatformPkg/Drivers/LcdGraphicsOutputDxe/PL111LcdGraphicsOutputDxe.inf\r
- INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf\r
-\r
- #\r
- # Semi-hosting filesystem\r
- #\r
- INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf\r
-\r
- #\r
- # FAT filesystem + GPT/MBR partitioning\r
- #\r
- INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
- INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
- INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
- INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
-\r
- # Versatile Express FileSystem\r
- INF ArmPlatformPkg/FileSystem/BootMonFs/BootMonFs.inf\r
-\r
- #\r
- # Multimedia Card Interface\r
- #\r
- INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf\r
- INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf\r
-\r
- #\r
- # Platform Driver\r
- #\r
- INF ArmPlatformPkg/ArmVExpressPkg/ArmVExpressDxe/ArmFvpDxe.inf\r
- INF OvmfPkg/VirtioBlkDxe/VirtioBlk.inf\r
-\r
- #\r
- # UEFI application (Shell Embedded Boot Loader)\r
- #\r
- INF ShellBinPkg/UefiShell/UefiShell.inf\r
-\r
- #\r
- # Bds\r
- #\r
- INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
- INF ArmPlatformPkg/Bds/Bds.inf\r
-\r
- # FV Filesystem\r
- INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf\r
-\r
- #\r
- # FDT installation\r
- #\r
- # The UEFI driver is at the end of the list of the driver to be dispatched\r
- # after the device drivers (eg: Ethernet) to ensure we have support for them.\r
- INF EmbeddedPkg/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf\r
-\r
- # Example to add a Device Tree to the Firmware Volume\r
- #FILE FREEFORM = PCD(gArmVExpressTokenSpaceGuid.PcdFdtVExpressFvpA15x4) {\r
- # SECTION RAW = ArmPlatformPkg/ArmVExpressPkg/Fdts/rtsm_ve-ca15x4.dtb\r
- #}\r
-\r
- # Legacy Linux Loader\r
- INF ArmPkg/Application/LinuxLoader/LinuxLoader.inf\r
-\r
-[FV.FVMAIN_COMPACT]\r
-FvAlignment = 8\r
-ERASE_POLARITY = 1\r
-MEMORY_MAPPED = TRUE\r
-STICKY_WRITE = TRUE\r
-LOCK_CAP = TRUE\r
-LOCK_STATUS = TRUE\r
-WRITE_DISABLED_CAP = TRUE\r
-WRITE_ENABLED_CAP = TRUE\r
-WRITE_STATUS = TRUE\r
-WRITE_LOCK_CAP = TRUE\r
-WRITE_LOCK_STATUS = TRUE\r
-READ_DISABLED_CAP = TRUE\r
-READ_ENABLED_CAP = TRUE\r
-READ_STATUS = TRUE\r
-READ_LOCK_CAP = TRUE\r
-READ_LOCK_STATUS = TRUE\r
-\r
-!if $(EDK2_SKIP_PEICORE) == 1\r
- INF ArmPlatformPkg/PrePi/PeiMPCore.inf\r
-!else\r
- INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf\r
- INF MdeModulePkg/Core/Pei/PeiMain.inf\r
- INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
- INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
- INF ArmPkg/Drivers/CpuPei/CpuPei.inf\r
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
- INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
- INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
- INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
-!endif\r
-\r
- FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {\r
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {\r
- SECTION FV_IMAGE = FVMAIN\r
- }\r
- }\r
-\r
-\r
-################################################################################\r
-#\r
-# Rules are use with the [FV] section's module INF type to define\r
-# how an FFS file is created for a given INF file. The following Rule are the default\r
-# rules for the different module type. User can add the customized rules to define the\r
-# content of the FFS file.\r
-#\r
-################################################################################\r
-\r
-\r
-############################################################################\r
-# Example of a DXE_DRIVER FFS file with a Checksum encapsulation section #\r
-############################################################################\r
-#\r
-#[Rule.Common.DXE_DRIVER]\r
-# FILE DRIVER = $(NAMED_GUID) {\r
-# DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
-# COMPRESS PI_STD {\r
-# GUIDED {\r
-# PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
-# UI STRING="$(MODULE_NAME)" Optional\r
-# VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
-# }\r
-# }\r
-# }\r
-#\r
-############################################################################\r
-\r
-[Rule.Common.SEC]\r
- FILE SEC = $(NAMED_GUID) RELOCS_STRIPPED {\r
- TE TE Align = 32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.PEI_CORE]\r
- FILE PEI_CORE = $(NAMED_GUID) {\r
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM]\r
- FILE PEIM = $(NAMED_GUID) {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- TE TE $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.PEIM.TIANOCOMPRESSED]\r
- FILE PEIM = $(NAMED_GUID) DEBUG_MYTOOLS_IA32 {\r
- PEI_DEPEX PEI_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
- }\r
-\r
-[Rule.Common.DXE_CORE]\r
- FILE DXE_CORE = $(NAMED_GUID) {\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.DXE_RUNTIME_DRIVER]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional $(INF_OUTPUT)/$(MODULE_NAME).depex\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- UI STRING ="$(MODULE_NAME)" Optional\r
- PE32 PE32 $(INF_OUTPUT)/$(MODULE_NAME).efi\r
- }\r
-\r
-[Rule.Common.UEFI_DRIVER.BINARY]\r
- FILE DRIVER = $(NAMED_GUID) {\r
- DXE_DEPEX DXE_DEPEX Optional |.depex\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
-\r
-[Rule.Common.UEFI_APPLICATION.BINARY]\r
- FILE APPLICATION = $(NAMED_GUID) {\r
- PE32 PE32 |.efi\r
- UI STRING="$(MODULE_NAME)" Optional\r
- VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
- }\r
Status = gBS->CalculateCrc32 ((VOID*)gST, gST->Hdr.HeaderSize, &gST->Hdr.CRC32);\r
ASSERT_EFI_ERROR (Status);\r
\r
+ // Now we need to setup the EFI System Table with information about the console devices.\r
+ InitializeConsole ();\r
+\r
// If BootNext environment variable is defined then we just load it !\r
BootNextSize = sizeof(UINT16);\r
Status = GetGlobalEnvironmentVariable (L"BootNext", NULL, &BootNextSize, (VOID**)&BootNext);\r
// If Boot Order does not exist then create a default entry\r
DefineDefaultBootEntries ();\r
\r
- // Now we need to setup the EFI System Table with information about the console devices.\r
- InitializeConsole ();\r
-\r
//\r
// Update the CRC32 in the EFI System Table header\r
//\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Chipset/AArch64.h>\r
-\r
-VOID\r
-EFIAPI\r
-ArmSecArchTrustzoneInit (\r
- VOID\r
- )\r
-{\r
- // Do not trap any access to Floating Point and Advanced SIMD in EL3.\r
- ArmWriteCptr (0);\r
-}\r
+++ /dev/null
-#========================================================================================\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http:#opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#=======================================================================================\r
-\r
-#include <AsmMacroIoLibV8.h>\r
-#include <Chipset/AArch64.h>\r
-\r
-#start of the code section\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(SwitchToNSExceptionLevel1)\r
-GCC_ASM_EXPORT(enter_monitor_mode)\r
-GCC_ASM_EXPORT(return_from_exception)\r
-GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
-GCC_ASM_EXPORT(set_non_secure_mode)\r
-\r
-// Switch from EL3 to NS-EL1\r
-ASM_PFX(SwitchToNSExceptionLevel1):\r
- // Now setup our EL1. Controlled by EL2 config on Model\r
- mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
- orr x0, x0, #(1 << 31) // Set EL1 to be 64bit\r
-\r
- // Send all interrupts to their respective Exception levels for EL2\r
- and x0, x0, #~(ARM_HCR_FMO | ARM_HCR_IMO | ARM_HCR_AMO) // Disable virtual FIQ, IRQ, SError and Abort\r
- msr hcr_el2, x0 // Write back our settings\r
-\r
- msr cptr_el2, xzr // Disable copro traps to EL2\r
-\r
- msr sctlr_el2, xzr\r
-\r
- // Enable architected timer access\r
- mrs x0, cnthctl_el2\r
- orr x0, x0, #3 // Enable EL1 access to timers\r
- msr cnthctl_el2, x0\r
-\r
- mrs x0, cntkctl_el1\r
- orr x0, x0, #3 // EL0 access to counters\r
- msr cntkctl_el1, x0\r
-\r
- // Set ID regs\r
- mrs x0, midr_el1\r
- mrs x1, mpidr_el1\r
- msr vpidr_el2, x0\r
- msr vmpidr_el2, x1\r
-\r
- ret\r
-\r
-\r
-// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7\r
-// we don't need a mode switch, just setup the Arguments and jump.\r
-// x0: Monitor World EntryPoint\r
-// x1: MpId\r
-// x2: SecBootMode\r
-// x3: Secure Monitor mode stack\r
-ASM_PFX(enter_monitor_mode):\r
- mov x4, x0 // Swap EntryPoint and MpId registers\r
- mov x0, x1\r
- mov x1, x2\r
- mov x2, x3\r
- br x4\r
-\r
-// Put the address in correct ELR_ELx and do a eret.\r
-// We may need to do some config before we change to another Mode.\r
-ASM_PFX(return_from_exception):\r
- msr elr_el3, x0\r
- eret\r
-\r
-// For AArch64 we need to construct the spsr we want from individual bits and pieces.\r
-ASM_PFX(copy_cpsr_into_spsr):\r
- mrs x0, CurrentEl // Get the current exception level we are running at.\r
- mrs x1, SPSel // Which Stack are we using\r
- orr x0, x0, x1\r
- mrs x1, daif // Which interrupts are enabled\r
- orr x0, x0, x1\r
- msr spsr_el3, x0 // Write to spsr\r
- ret\r
-\r
-// Get this from platform file.\r
-ASM_PFX(set_non_secure_mode):\r
- msr spsr_el3, x0\r
- ret\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AutoGen.h>\r
-#include <AsmMacroIoLibV8.h>\r
-#include "SecInternal.h"\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_IMPORT(CEntryPoint)\r
-GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
-GCC_ASM_IMPORT(ArmDisableInterrupts)\r
-GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
-GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_IMPORT(ArmCallWFE)\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-StartupAddr: .8byte ASM_PFX(CEntryPoint)\r
-\r
-ASM_PFX(_ModuleEntryPoint):\r
-\r
-// NOTE: We could be booting from EL3, EL2 or EL1. Need to correctly detect\r
-// and configure the system accordingly. EL2 is default if possible.\r
-// If we started in EL3 we need to switch and run at EL2.\r
-// If we are running at EL2 stay in EL2\r
-// If we are starting at EL1 stay in EL1.\r
-\r
-// Sec only runs in EL3. Othewise we jump to PEI without changing anything.\r
-// If Sec runs we change to EL2 before switching to PEI.\r
-\r
-// Which EL are we running at? Every EL needs some level of setup...\r
- EL1_OR_EL2_OR_EL3(x0)\r
-1:// If we are at EL1 or EL2 leave SEC for PEI.\r
-2:b ASM_PFX(JumpToPEI)\r
- // If we are at EL3 we need to configure it and switch to EL2\r
-3:b ASM_PFX(MainEntryPoint)\r
-\r
-ASM_PFX(MainEntryPoint):\r
- // First ensure all interrupts are disabled\r
- bl ASM_PFX(ArmDisableInterrupts)\r
-\r
- // Ensure that the MMU and caches are off\r
- bl ASM_PFX(ArmDisableCachesAndMmu)\r
-\r
- // By default, we are doing a cold boot\r
- mov x10, #ARM_SEC_COLD_BOOT\r
-\r
- // Jump to Platform Specific Boot Action function\r
- bl ASM_PFX(ArmPlatformSecBootAction)\r
-\r
-_IdentifyCpu:\r
- // Identify CPU ID\r
- bl ASM_PFX(ArmReadMpidr)\r
- // Keep a copy of the MpId register value\r
- mov x5, x0\r
-\r
- // Is it the Primary Core ?\r
- bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
- cmp x0, #1\r
- // Only the primary core initialize the memory (SMC)\r
- b.eq _InitMem\r
-\r
-_WaitInitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- // Otherwise we have to wait the Primary Core to finish the initialization\r
- cmp x10, #ARM_SEC_COLD_BOOT\r
- b.ne _SetupSecondaryCoreStack\r
-\r
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
- bl ASM_PFX(ArmCallWFE)\r
- // Now the Init Mem is initialized, we setup the secondary core stacks\r
- b _SetupSecondaryCoreStack\r
-\r
-_InitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- cmp x10, #ARM_SEC_COLD_BOOT\r
- b.ne _SetupPrimaryCoreStack\r
-\r
- // Initialize Init Boot Memory\r
- bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
-\r
-_SetupPrimaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)\r
- add x1, x1, x2\r
-\r
- mov sp, x1\r
- b _PrepareArguments\r
-\r
-_SetupSecondaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), x1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), x2)\r
- add x6, x1, x2\r
-\r
- // Get the Core Position\r
- mov x0, x5\r
- bl ASM_PFX(ArmPlatformGetCorePosition)\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add x0, x0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), x2)\r
- mul x0, x0, x2\r
- // SP = StackBase + StackOffset\r
- add sp, x6, x0\r
-\r
-_PrepareArguments:\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr x3, StartupAddr\r
-\r
- // Jump to SEC C code\r
- // r0 = mp_id\r
- // r1 = Boot Mode\r
- mov x0, x5\r
- mov x1, x10\r
- blr x3\r
-\r
- ret\r
-\r
-ASM_PFX(JumpToPEI):\r
- LoadConstantToReg (FixedPcdGet32(PcdFvBaseAddress), x0)\r
- blr x0\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Chipset/ArmV7.h>\r
-\r
-VOID\r
-EFIAPI\r
-ArmSecArchTrustzoneInit (\r
- VOID\r
- )\r
-{\r
- // Write to CP15 Non-secure Access Control Register\r
- ArmWriteNsacr (PcdGet32 (PcdArmNsacr));\r
-}\r
+++ /dev/null
-#========================================================================================\r
-# Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#=======================================================================================\r
-\r
-#start of the code section\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_EXPORT(return_from_exception)\r
-GCC_ASM_EXPORT(enter_monitor_mode)\r
-GCC_ASM_EXPORT(copy_cpsr_into_spsr)\r
-GCC_ASM_EXPORT(set_non_secure_mode)\r
-\r
-# r0: Monitor World EntryPoint\r
-# r1: MpId\r
-# r2: SecBootMode\r
-# r3: Secure Monitor mode stack\r
-ASM_PFX(enter_monitor_mode):\r
- cmp r3, #0 @ If a Secure Monitor stack base has not been defined then use the Secure stack\r
- moveq r3, sp\r
-\r
- mrs r4, cpsr @ Save current mode (SVC) in r4\r
- bic r5, r4, #0x1f @ Clear all mode bits\r
- orr r5, r5, #0x16 @ Set bits for Monitor mode\r
- msr cpsr_cxsf, r5 @ We are now in Monitor Mode\r
-\r
- mov sp, r3 @ Set the stack of the Monitor Mode\r
-\r
- mov lr, r0 @ Use the pass entrypoint as lr\r
-\r
- msr spsr_cxsf, r4 @ Use saved mode for the MOVS jump to the kernel\r
-\r
- mov r4, r0 @ Swap EntryPoint and MpId registers\r
- mov r0, r1\r
- mov r1, r2\r
- mov r2, r3\r
-\r
- bx r4\r
-\r
-# Return-from-exception is not an interworking return, so we must do it\r
-# in two steps, in case r0 has the Thumb bit set.\r
-ASM_PFX(return_from_exception):\r
- adr lr, returned_exception\r
- movs pc, lr\r
-returned_exception: @ We are now in non-secure state\r
- bx r0\r
-\r
-# Save the current Program Status Register (PSR) into the Saved PSR\r
-ASM_PFX(copy_cpsr_into_spsr):\r
- mrs r0, cpsr\r
- msr spsr_cxsf, r0\r
- bx lr\r
-\r
-# Set the Non Secure Mode\r
-ASM_PFX(set_non_secure_mode):\r
- push { r1 }\r
- and r0, r0, #0x1f @ Keep only the mode bits\r
- mrs r1, spsr @ Read the spsr\r
- bic r1, r1, #0x1f @ Clear all mode bits\r
- orr r1, r1, r0\r
- msr spsr_cxsf, r1 @ write back spsr (may have caused a mode switch)\r
- isb\r
- pop { r1 }\r
- bx lr @ return (hopefully thumb-safe!)\r
-\r
-ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
- EXPORT return_from_exception\r
- EXPORT enter_monitor_mode\r
- EXPORT copy_cpsr_into_spsr\r
- EXPORT set_non_secure_mode\r
-\r
- AREA Helper, CODE, READONLY\r
-\r
-// r0: Monitor World EntryPoint\r
-// r1: MpId\r
-// r2: SecBootMode\r
-// r3: Secure Monitor mode stack\r
-enter_monitor_mode FUNCTION\r
- cmp r3, #0 // If a Secure Monitor stack base has not been defined then use the Secure stack\r
- moveq r3, sp\r
-\r
- mrs r4, cpsr // Save current mode (SVC) in r4\r
- bic r5, r4, #0x1f // Clear all mode bits\r
- orr r5, r5, #0x16 // Set bits for Monitor mode\r
- msr cpsr_cxsf, r5 // We are now in Monitor Mode\r
-\r
- mov sp, r3 // Set the stack of the Monitor Mode\r
-\r
- mov lr, r0 // Use the pass entrypoint as lr\r
-\r
- msr spsr_cxsf, r4 // Use saved mode for the MOVS jump to the kernel\r
-\r
- mov r4, r0 // Swap EntryPoint and MpId registers\r
- mov r0, r1\r
- mov r1, r2\r
- mov r2, r3\r
-\r
- bx r4\r
- ENDFUNC\r
-\r
-// Return-from-exception is not an interworking return, so we must do it\r
-// in two steps, in case r0 has the Thumb bit set.\r
-return_from_exception\r
- adr lr, returned_exception\r
- movs pc, lr\r
-returned_exception // We are now in non-secure state\r
- bx r0\r
-\r
-// Save the current Program Status Register (PSR) into the Saved PSR\r
-copy_cpsr_into_spsr\r
- mrs r0, cpsr\r
- msr spsr_cxsf, r0\r
- bx lr\r
-\r
-// Set the Non Secure Mode\r
-set_non_secure_mode\r
- push { r1 }\r
- and r0, r0, #0x1f // Keep only the mode bits\r
- mrs r1, spsr // Read the spsr\r
- bic r1, r1, #0x1f // Clear all mode bits\r
- orr r1, r1, r0\r
- msr spsr_cxsf, r1 // write back spsr (may have caused a mode switch)\r
- isb\r
- pop { r1 }\r
- bx lr // return (hopefully thumb-safe!)\r
-\r
-dead\r
- B dead\r
-\r
- END\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AutoGen.h>\r
-#include <AsmMacroIoLib.h>\r
-#include "SecInternal.h"\r
-\r
-.text\r
-.align 3\r
-\r
-GCC_ASM_IMPORT(CEntryPoint)\r
-GCC_ASM_IMPORT(ArmPlatformIsPrimaryCore)\r
-GCC_ASM_IMPORT(ArmPlatformGetCorePosition)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootAction)\r
-GCC_ASM_IMPORT(ArmPlatformSecBootMemoryInit)\r
-GCC_ASM_IMPORT(ArmDisableInterrupts)\r
-GCC_ASM_IMPORT(ArmDisableCachesAndMmu)\r
-GCC_ASM_IMPORT(ArmReadMpidr)\r
-GCC_ASM_IMPORT(ArmCallWFE)\r
-GCC_ASM_EXPORT(_ModuleEntryPoint)\r
-\r
-StartupAddr: .word ASM_PFX(CEntryPoint)\r
-\r
-ASM_PFX(_ModuleEntryPoint):\r
- // First ensure all interrupts are disabled\r
- bl ASM_PFX(ArmDisableInterrupts)\r
-\r
- // Ensure that the MMU and caches are off\r
- bl ASM_PFX(ArmDisableCachesAndMmu)\r
-\r
- // By default, we are doing a cold boot\r
- mov r10, #ARM_SEC_COLD_BOOT\r
-\r
- // Jump to Platform Specific Boot Action function\r
- blx ASM_PFX(ArmPlatformSecBootAction)\r
-\r
-_IdentifyCpu:\r
- // Identify CPU ID\r
- bl ASM_PFX(ArmReadMpidr)\r
- // Keep a copy of the MpId register value\r
- mov r9, r0\r
-\r
- // Is it the Primary Core ?\r
- bl ASM_PFX(ArmPlatformIsPrimaryCore)\r
- cmp r0, #1\r
- // Only the primary core initialize the memory (SMC)\r
- beq _InitMem\r
-\r
-_WaitInitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- // Otherwise we have to wait the Primary Core to finish the initialization\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupSecondaryCoreStack\r
-\r
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
- bl ASM_PFX(ArmCallWFE)\r
- // Now the Init Mem is initialized, we setup the secondary core stacks\r
- b _SetupSecondaryCoreStack\r
-\r
-_InitMem:\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupPrimaryCoreStack\r
-\r
- // Initialize Init Boot Memory\r
- bl ASM_PFX(ArmPlatformSecBootMemoryInit)\r
-\r
-_SetupPrimaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- mov sp, r1\r
- b _PrepareArguments\r
-\r
-_SetupSecondaryCoreStack:\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r6, r1, r2\r
-\r
- // Get the Core Position\r
- mov r0, r9\r
- bl ASM_PFX(ArmPlatformGetCorePosition)\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add r0, r0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
- mul r0, r0, r2\r
- // SP = StackBase + StackOffset\r
- add sp, r6, r0\r
-\r
-_PrepareArguments:\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r3, StartupAddr\r
-\r
- // Jump to SEC C code\r
- // r0 = mp_id\r
- // r1 = Boot Mode\r
- mov r0, r9\r
- mov r1, r10\r
- blx r3\r
-\r
-_NeverReturn:\r
- b _NeverReturn\r
+++ /dev/null
-//\r
-// Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-//\r
-// This program and the accompanying materials\r
-// are licensed and made available under the terms and conditions of the BSD License\r
-// which accompanies this distribution. The full text of the license may be found at\r
-// http://opensource.org/licenses/bsd-license.php\r
-//\r
-// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-//\r
-//\r
-\r
-#include <AutoGen.h>\r
-#include <AsmMacroIoLib.h>\r
-#include "SecInternal.h"\r
-\r
- INCLUDE AsmMacroIoLib.inc\r
-\r
- IMPORT CEntryPoint\r
- IMPORT ArmPlatformIsPrimaryCore\r
- IMPORT ArmPlatformGetCorePosition\r
- IMPORT ArmPlatformSecBootAction\r
- IMPORT ArmPlatformSecBootMemoryInit\r
- IMPORT ArmDisableInterrupts\r
- IMPORT ArmDisableCachesAndMmu\r
- IMPORT ArmReadMpidr\r
- IMPORT ArmCallWFE\r
- EXPORT _ModuleEntryPoint\r
-\r
- PRESERVE8\r
- AREA SecEntryPoint, CODE, READONLY\r
-\r
-StartupAddr DCD CEntryPoint\r
-\r
-_ModuleEntryPoint FUNCTION\r
- // First ensure all interrupts are disabled\r
- bl ArmDisableInterrupts\r
-\r
- // Ensure that the MMU and caches are off\r
- bl ArmDisableCachesAndMmu\r
-\r
- // By default, we are doing a cold boot\r
- mov r10, #ARM_SEC_COLD_BOOT\r
-\r
- // Jump to Platform Specific Boot Action function\r
- blx ArmPlatformSecBootAction\r
-\r
-_IdentifyCpu\r
- // Identify CPU ID\r
- bl ArmReadMpidr\r
- // Keep a copy of the MpId register value\r
- mov r9, r0\r
-\r
- // Is it the Primary Core ?\r
- bl ArmPlatformIsPrimaryCore\r
- cmp r0, #1\r
- // Only the primary core initialize the memory (SMC)\r
- beq _InitMem\r
-\r
-_WaitInitMem\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- // Otherwise we have to wait the Primary Core to finish the initialization\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupSecondaryCoreStack\r
-\r
- // Wait for the primary core to initialize the initial memory (event: BOOT_MEM_INIT)\r
- bl ArmCallWFE\r
- // Now the Init Mem is initialized, we setup the secondary core stacks\r
- b _SetupSecondaryCoreStack\r
-\r
-_InitMem\r
- // If we are not doing a cold boot in this case we should assume the Initial Memory to be already initialized\r
- cmp r10, #ARM_SEC_COLD_BOOT\r
- bne _SetupPrimaryCoreStack\r
-\r
- // Initialize Init Boot Memory\r
- bl ArmPlatformSecBootMemoryInit\r
-\r
-_SetupPrimaryCoreStack\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r1, r1, r2\r
-\r
- mov sp, r1\r
- b _PrepareArguments\r
-\r
-_SetupSecondaryCoreStack\r
- // Get the top of the primary stacks (and the base of the secondary stacks)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoresSecStackBase), r1)\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecPrimaryStackSize), r2)\r
- add r6, r1, r2\r
-\r
- // Get the Core Position\r
- mov r0, r9\r
- bl ArmPlatformGetCorePosition\r
- // The stack starts at the top of the stack region. Add '1' to the Core Position to get the top of the stack\r
- add r0, r0, #1\r
-\r
- // StackOffset = CorePos * StackSize\r
- LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecSecondaryStackSize), r2)\r
- mul r0, r0, r2\r
- // SP = StackBase + StackOffset\r
- add sp, r6, r0\r
-\r
-_PrepareArguments\r
- // Move sec startup address into a data register\r
- // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
- ldr r3, StartupAddr\r
-\r
- // Jump to SEC C code\r
- // r0 = mp_id\r
- // r1 = Boot Mode\r
- mov r0, r9\r
- mov r1, r10\r
- blx r3\r
- ENDFUNC\r
-\r
-_NeverReturn\r
- b _NeverReturn\r
- END\r
+++ /dev/null
-/** @file\r
-* Main file supporting the SEC Phase on ARM Platforms\r
-*\r
-* Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#include <Library/ArmTrustedMonitorLib.h>\r
-#include <Library/DebugAgentLib.h>\r
-#include <Library/PrintLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
-#include <Library/SerialPortLib.h>\r
-#include <Library/ArmGicLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-\r
-#include "SecInternal.h"\r
-\r
-#define SerialPrint(txt) SerialPortWrite ((UINT8*)txt, AsciiStrLen(txt)+1);\r
-\r
-VOID\r
-CEntryPoint (\r
- IN UINTN MpId,\r
- IN UINTN SecBootMode\r
- )\r
-{\r
- CHAR8 Buffer[100];\r
- UINTN CharCount;\r
- UINTN JumpAddress;\r
-\r
- // Invalidate the data cache. Doesn't have to do the Data cache clean.\r
- ArmInvalidateDataCache ();\r
-\r
- // Invalidate Instruction Cache\r
- ArmInvalidateInstructionCache ();\r
-\r
- // Invalidate I & D TLBs\r
- ArmInvalidateTlb ();\r
-\r
- // CPU specific settings\r
- ArmCpuSetup (MpId);\r
-\r
- // Enable Floating Point Coprocessor if supported by the platform\r
- if (FixedPcdGet32 (PcdVFPEnabled)) {\r
- ArmEnableVFP ();\r
- }\r
-\r
- // Initialize peripherals that must be done at the early stage\r
- // Example: Some L2 controller, interconnect, clock, DMC, etc\r
- ArmPlatformSecInitialize (MpId);\r
-\r
- // Primary CPU clears out the SCU tag RAMs, secondaries wait\r
- if (ArmPlatformIsPrimaryCore (MpId) && (SecBootMode == ARM_SEC_COLD_BOOT)) {\r
- if (ArmIsMpCore()) {\r
- // Signal for the initial memory is configured (event: BOOT_MEM_INIT)\r
- ArmCallSEV ();\r
- }\r
-\r
- // SEC phase needs to run library constructors by hand. This assumes we are linked against the SerialLib\r
- // In non SEC modules the init call is in autogenerated code.\r
- SerialPortInitialize ();\r
-\r
- // Start talking\r
- if (FixedPcdGetBool (PcdTrustzoneSupport)) {\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Secure firmware (version %s built at %a on %a)\n\r",\r
- (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
- } else {\r
- CharCount = AsciiSPrint (Buffer,sizeof (Buffer),"Boot firmware (version %s built at %a on %a)\n\r",\r
- (CHAR16*)PcdGetPtr(PcdFirmwareVersionString), __TIME__, __DATE__);\r
- }\r
- SerialPortWrite ((UINT8 *) Buffer, CharCount);\r
-\r
- // Initialize the Debug Agent for Source Level Debugging\r
- InitializeDebugAgent (DEBUG_AGENT_INIT_PREMEM_SEC, NULL, NULL);\r
- SaveAndSetDebugTimerInterrupt (TRUE);\r
-\r
- // Enable the GIC distributor and CPU Interface\r
- // - no other Interrupts are enabled, doesn't have to worry about the priority.\r
- // - all the cores are in secure state, use secure SGI's\r
- ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));\r
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
- } else {\r
- // Enable the GIC CPU Interface\r
- ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));\r
- }\r
-\r
- // Enable Full Access to CoProcessors\r
- ArmWriteCpacr (CPACR_CP_FULL_ACCESS);\r
-\r
- // Test if Trustzone is supported on this platform\r
- if (FixedPcdGetBool (PcdTrustzoneSupport)) {\r
- if (ArmIsMpCore ()) {\r
- // Setup SMP in Non Secure world\r
- ArmCpuSetupSmpNonSecure (GET_CORE_ID(MpId));\r
- }\r
-\r
- // Either we use the Secure Stacks for Secure Monitor (in this case (Base == 0) && (Size == 0))\r
- // Or we use separate Secure Monitor stacks (but (Base != 0) && (Size != 0))\r
- ASSERT (((PcdGet32(PcdCPUCoresSecMonStackBase) == 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) == 0)) ||\r
- ((PcdGet32(PcdCPUCoresSecMonStackBase) != 0) && (PcdGet32(PcdCPUCoreSecMonStackSize) != 0)));\r
-\r
- // Enter Monitor Mode\r
- enter_monitor_mode (\r
- (UINTN)TrustedWorldInitialization, MpId, SecBootMode,\r
- (VOID*) (PcdGet32 (PcdCPUCoresSecMonStackBase) +\r
- (PcdGet32 (PcdCPUCoreSecMonStackSize) * (ArmPlatformGetCorePosition (MpId) + 1)))\r
- );\r
- } else {\r
- if (ArmPlatformIsPrimaryCore (MpId)) {\r
- SerialPrint ("Trust Zone Configuration is disabled\n\r");\r
- }\r
-\r
- // With Trustzone support the transition from Sec to Normal world is done by return_from_exception().\r
- // If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program\r
- // Status Register as the the current one (CPSR).\r
- copy_cpsr_into_spsr ();\r
-\r
- // Call the Platform specific function to execute additional actions if required\r
- JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
- ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
-\r
- NonTrustedWorldTransition (MpId, JumpAddress);\r
- }\r
- ASSERT (0); // We must never return from the above function\r
-}\r
-\r
-VOID\r
-TrustedWorldInitialization (\r
- IN UINTN MpId,\r
- IN UINTN SecBootMode\r
- )\r
-{\r
- UINTN JumpAddress;\r
-\r
- //-------------------- Monitor Mode ---------------------\r
-\r
- // Set up Monitor World (Vector Table, etc)\r
- ArmSecureMonitorWorldInitialize ();\r
-\r
- // Transfer the interrupt to Non-secure World\r
- ArmGicSetupNonSecure (MpId, PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase));\r
-\r
- // Initialize platform specific security policy\r
- ArmPlatformSecTrustzoneInit (MpId);\r
-\r
- // Setup the Trustzone Chipsets\r
- if (SecBootMode == ARM_SEC_COLD_BOOT) {\r
- if (ArmPlatformIsPrimaryCore (MpId)) {\r
- if (ArmIsMpCore()) {\r
- // Signal the secondary core the Security settings is done (event: EVENT_SECURE_INIT)\r
- ArmCallSEV ();\r
- }\r
- } else {\r
- // The secondary cores need to wait until the Trustzone chipsets configuration is done\r
- // before switching to Non Secure World\r
-\r
- // Wait for the Primary Core to finish the initialization of the Secure World (event: EVENT_SECURE_INIT)\r
- ArmCallWFE ();\r
- }\r
- }\r
-\r
- // Call the Platform specific function to execute additional actions if required\r
- JumpAddress = PcdGet64 (PcdFvBaseAddress);\r
- ArmPlatformSecExtraAction (MpId, &JumpAddress);\r
-\r
- // Initialize architecture specific security policy\r
- ArmSecArchTrustzoneInit ();\r
-\r
- // CP15 Secure Configuration Register\r
- ArmWriteScr (PcdGet32 (PcdArmScr));\r
-\r
- NonTrustedWorldTransition (MpId, JumpAddress);\r
-}\r
-\r
-VOID\r
-NonTrustedWorldTransition (\r
- IN UINTN MpId,\r
- IN UINTN JumpAddress\r
- )\r
-{\r
- // If PcdArmNonSecModeTransition is defined then set this specific mode to CPSR before the transition\r
- // By not set, the mode for Non Secure World is SVC\r
- if (PcdGet32 (PcdArmNonSecModeTransition) != 0) {\r
- set_non_secure_mode ((ARM_PROCESSOR_MODE)PcdGet32 (PcdArmNonSecModeTransition));\r
- }\r
-\r
- return_from_exception (JumpAddress);\r
- //-------------------- Non Secure Mode ---------------------\r
-\r
- // PEI Core should always load and never return\r
- ASSERT (FALSE);\r
-}\r
-\r
+++ /dev/null
-#/** @file\r
-# SEC - Reset vector code that jumps to C and starts the PEI phase\r
-#\r
-# (C) Copyright 2015 Hewlett-Packard Development Company, L.P.<BR>\r
-# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-#\r
-# This program and the accompanying materials\r
-# are licensed and made available under the terms and conditions of the BSD License\r
-# which accompanies this distribution. The full text of the license may be found at\r
-# http://opensource.org/licenses/bsd-license.php\r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-#\r
-#**/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = ArmPlatformSec\r
- FILE_GUID = c536bbfe-c813-4e48-9f90-01fe1ecf9d54\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
-\r
-[Sources]\r
- Sec.c\r
-\r
-[Sources.ARM]\r
- Arm/Arch.c\r
- Arm/Helper.asm | RVCT\r
- Arm/Helper.S | GCC\r
- Arm/SecEntryPoint.S | GCC\r
- Arm/SecEntryPoint.asm | RVCT\r
-\r
-[Sources.AARCH64]\r
- AArch64/Arch.c\r
- AArch64/Helper.S\r
- AArch64/SecEntryPoint.S\r
-\r
-[Packages]\r
- MdePkg/MdePkg.dec\r
- MdeModulePkg/MdeModulePkg.dec\r
- ArmPkg/ArmPkg.dec\r
- ArmPlatformPkg/ArmPlatformPkg.dec\r
-\r
-[LibraryClasses]\r
- ArmCpuLib\r
- ArmLib\r
- ArmPlatformLib\r
- ArmPlatformSecLib\r
- ArmTrustedMonitorLib\r
- BaseLib\r
- DebugLib\r
- DebugAgentLib\r
- IoLib\r
- ArmGicLib\r
- PrintLib\r
- SerialPortLib\r
-\r
-[Pcd]\r
- gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString\r
-\r
-[FixedPcd.common]\r
-\r
- gArmTokenSpaceGuid.PcdTrustzoneSupport\r
- gArmTokenSpaceGuid.PcdVFPEnabled\r
-\r
- gArmTokenSpaceGuid.PcdArmScr\r
- gArmTokenSpaceGuid.PcdArmNonSecModeTransition\r
-\r
- gArmTokenSpaceGuid.PcdSecureFvBaseAddress\r
- gArmTokenSpaceGuid.PcdSecureFvSize\r
-\r
- gArmTokenSpaceGuid.PcdFvBaseAddress\r
-\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecSecondaryStackSize\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase\r
- gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize\r
-\r
- gArmTokenSpaceGuid.PcdGicDistributorBase\r
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase\r
-\r
-[FixedPcd.ARM]\r
- gArmTokenSpaceGuid.PcdArmNsacr\r
+++ /dev/null
-/** @file\r
-* Main file supporting the SEC Phase on ARM PLatforms\r
-*\r
-* Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
-*\r
-* This program and the accompanying materials\r
-* are licensed and made available under the terms and conditions of the BSD License\r
-* which accompanies this distribution. The full text of the license may be found at\r
-* http://opensource.org/licenses/bsd-license.php\r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-*\r
-**/\r
-\r
-#ifndef __SEC_H__\r
-#define __SEC_H__\r
-\r
-#include <Base.h>\r
-#include <Library/ArmLib.h>\r
-#include <Library/ArmCpuLib.h>\r
-#include <Library/ArmPlatformLib.h>\r
-#include <Library/ArmPlatformSecLib.h>\r
-#include <Library/BaseLib.h>\r
-#include <Library/DebugLib.h>\r
-#include <Library/PcdLib.h>\r
-\r
-#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)\r
-\r
-VOID\r
-TrustedWorldInitialization (\r
- IN UINTN MpId,\r
- IN UINTN SecBootMode\r
- );\r
-\r
-VOID\r
-NonTrustedWorldTransition (\r
- IN UINTN MpId,\r
- IN UINTN JumpAddress\r
- );\r
-\r
-VOID\r
-ArmSetupGicNonSecure (\r
- IN INTN GicDistributorBase,\r
- IN INTN GicInterruptInterfaceBase\r
-);\r
-\r
-VOID\r
-enter_monitor_mode (\r
- IN UINTN MonitorEntryPoint,\r
- IN UINTN MpId,\r
- IN UINTN SecBootMode,\r
- IN VOID* MonitorStackBase\r
- );\r
-\r
-VOID\r
-return_from_exception (\r
- IN UINTN NonSecureBase\r
- );\r
-\r
-VOID\r
-copy_cpsr_into_spsr (\r
- VOID\r
- );\r
-\r
-VOID\r
-set_non_secure_mode (\r
- IN ARM_PROCESSOR_MODE Mode\r
- );\r
-\r
-VOID\r
-SecCommonExceptionEntry (\r
- IN UINT32 Entry,\r
- IN UINTN LR\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-ArmSecArchTrustzoneInit (\r
- VOID\r
- );\r
-\r
-#endif\r
W: https://github.com/tianocore/tianocore.github.io/wiki/SecurityPkg\r
M: Chao Zhang <chao.b.zhang@intel.com>\r
\r
-ShellPkg, ShellBinPkg\r
+ShellBinPkg\r
+W: https://github.com/tianocore/tianocore.github.io/wiki/ShellPkg\r
+M: Jaben Carsey <jaben.carsey@intel.com> (Ia32/X64)\r
+M: Shumin Qiu <shumin.qiu@intel.com> (Ia32/X64)\r
+M: Leif Lindholm <leif.lindholm@linaro.org> (ARM/AArch64)\r
+M: Ard Biesheuvel <ard.biesheuvel@linaro.org> (ARM/AArch64)\r
+\r
+ShellPkg\r
W: https://github.com/tianocore/tianocore.github.io/wiki/ShellPkg\r
M: Jaben Carsey <jaben.carsey@intel.com>\r
M: Shumin Qiu <shumin.qiu@intel.com>\r
//\r
// if we have space save it...\r
//\r
- if ((CountSoFar+1)*sizeof(CHAR16) < *Size){\r
+ if ((CountSoFar + 1) * CharSize < *Size){\r
ASSERT(Buffer != NULL);\r
- ((CHAR16*)Buffer)[CountSoFar] = CharBuffer;\r
- ((CHAR16*)Buffer)[CountSoFar+1] = CHAR_NULL;\r
+ if (*Ascii) {\r
+ ((CHAR8*)Buffer)[CountSoFar] = (CHAR8) CharBuffer;\r
+ ((CHAR8*)Buffer)[CountSoFar+1] = '\0';\r
+ }\r
+ else {\r
+ ((CHAR16*)Buffer)[CountSoFar] = CharBuffer;\r
+ ((CHAR16*)Buffer)[CountSoFar+1] = CHAR_NULL;\r
+ }\r
}\r
}\r
\r
//\r
// if we ran out of space tell when...\r
//\r
- if ((CountSoFar+1)*sizeof(CHAR16) > *Size){\r
- *Size = (CountSoFar+1)*sizeof(CHAR16);\r
- if (!Truncate) {\r
- gEfiShellProtocol->SetFilePosition(Handle, OriginalFilePosition);\r
- } else {\r
- DEBUG((DEBUG_WARN, "The line was truncated in ShellFileHandleReadLine"));\r
+ if (Status != EFI_END_OF_FILE){\r
+ if ((CountSoFar + 1) * CharSize > *Size){\r
+ *Size = (CountSoFar + 1) * CharSize;\r
+ if (!Truncate) {\r
+ gEfiShellProtocol->SetFilePosition(Handle, OriginalFilePosition);\r
+ } else {\r
+ DEBUG((DEBUG_WARN, "The line was truncated in ShellFileHandleReadLine"));\r
+ }\r
+ return (EFI_BUFFER_TOO_SMALL);\r
+ }\r
+\r
+ if (*Ascii) {\r
+ if (CountSoFar && ((CHAR8*)Buffer)[CountSoFar - 1] == '\r') {\r
+ ((CHAR8*)Buffer)[CountSoFar - 1] = '\0';\r
+ }\r
+ }\r
+ else {\r
+ if (CountSoFar && Buffer[CountSoFar - 1] == L'\r') {\r
+ Buffer[CountSoFar - 1] = CHAR_NULL;\r
+ }\r
}\r
- return (EFI_BUFFER_TOO_SMALL);\r
- }\r
- while(Buffer[StrLen(Buffer)-1] == L'\r') {\r
- Buffer[StrLen(Buffer)-1] = CHAR_NULL;\r
}\r
\r
return (Status);\r
projects / mirror_edk2.git / commitdiff