ArmPkg/ArmDmaLib: use double buffering only for bus master write

The ArmPkg implementation of DmaLib uses double buffering to ensure
that any attempt to perform non-coherent DMA on unaligned buffers cannot
corrupt adjacent unrelated data which happens to share cachelines with
the data we are exchanging with the device.

Such corruption can only occur on bus master write, in which case we have
to invalidate the caches to ensure the CPU will see the data written to
memory by the device. In the bus master read case, we can simply clean
and invalidate at the same time, which may purge unrelated adjacent data
from the caches, but will not corrupt its contents.

Also, this double buffer does not necessarily have to be allocated from
uncached memory: by the same reasoning, we can perform cache invalidation
on an ordinary pool allocation as long as we take the same alignment
constraints into account.

So update our code accordingly: remove double buffering from the bus
master read path, and switch to a pool allocation for the double buffer.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
index f4ee9e4c5ea2ba61e03bd8dcfda6b58cbfb8db18..566f77d03f293109e1e0d99fe5ca72b0301b34a0 100644 (file)
--- a/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
+++ b/ArmPkg/Library/ArmDmaLib/ArmDmaLib.c
@@ -2,6 +2,7 @@
   Generic ARM implementation of DmaLib.h\r
 \r
   Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r
+  Copyright (c) 2015 - 2017, Linaro, Ltd. All rights reserved.<BR>\r
 \r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
@@ -80,6 +81,7 @@ DmaMap (
   MAP_INFO_INSTANCE               *Map;\r
   VOID                            *Buffer;\r
   EFI_GCD_MEMORY_SPACE_DESCRIPTOR GcdDescriptor;\r
+  UINTN                           AllocSize;\r
 \r
   if (HostAddress == NULL || NumberOfBytes == NULL || DeviceAddress == NULL || Mapping == NULL ) {\r
     return EFI_INVALID_PARAMETER;\r
@@ -104,8 +106,9 @@ DmaMap (
     return  EFI_OUT_OF_RESOURCES;\r
   }\r
 \r
-  if ((((UINTN)HostAddress & (mCpu->DmaBufferAlignment - 1)) != 0) ||\r
-      ((*NumberOfBytes & (mCpu->DmaBufferAlignment - 1)) != 0)) {\r
+  if (Operation != MapOperationBusMasterRead &&\r
+      ((((UINTN)HostAddress & (mCpu->DmaBufferAlignment - 1)) != 0) ||\r
+       ((*NumberOfBytes & (mCpu->DmaBufferAlignment - 1)) != 0))) {\r
 \r
     // Get the cacheability of the region\r
     Status = gDS->GetMemorySpaceDescriptor ((UINTN)HostAddress, &GcdDescriptor);\r
@@ -129,21 +132,31 @@ DmaMap (
       }\r
 \r
       //\r
-      // If the buffer does not fill entire cache lines we must double buffer into\r
-      // uncached memory. Device (PCI) address becomes uncached page.\r
+      // If the buffer does not fill entire cache lines we must double buffer\r
+      // into a suitably aligned allocation that allows us to invalidate the\r
+      // cache without running the risk of corrupting adjacent unrelated data.\r
+      // Note that pool allocations are guaranteed to be 8 byte aligned, so\r
+      // we only have to add (alignment - 8) worth of padding.\r
       //\r
-      Map->DoubleBuffer  = TRUE;\r
-      Status = DmaAllocateBuffer (EfiBootServicesData, EFI_SIZE_TO_PAGES (*NumberOfBytes), &Buffer);\r
-      if (EFI_ERROR (Status)) {\r
+      Map->DoubleBuffer = TRUE;\r
+      AllocSize = ALIGN_VALUE (*NumberOfBytes, mCpu->DmaBufferAlignment) +\r
+                  (mCpu->DmaBufferAlignment - 8);\r
+      Map->BufferAddress = AllocatePool (AllocSize);\r
+      if (Map->BufferAddress == NULL) {\r
+        Status = EFI_OUT_OF_RESOURCES;\r
         goto FreeMapInfo;\r
       }\r
 \r
-      if (Operation == MapOperationBusMasterRead) {\r
-        CopyMem (Buffer, HostAddress, *NumberOfBytes);\r
-      }\r
-\r
+      Buffer = ALIGN_POINTER (Map->BufferAddress, mCpu->DmaBufferAlignment);\r
       *DeviceAddress = HostToDeviceAddress (ConvertToPhysicalAddress (Buffer));\r
-      Map->BufferAddress = Buffer;\r
+\r
+      //\r
+      // Get rid of any dirty cachelines covering the double buffer. This\r
+      // prevents them from being written back unexpectedly, potentially\r
+      // overwriting the data we receive from the device.\r
+      //\r
+      mCpu->FlushDataCache (mCpu, (UINTN)Buffer, *NumberOfBytes,\r
+              EfiCpuFlushTypeWriteBack);\r
     } else {\r
       Map->DoubleBuffer  = FALSE;\r
     }\r
@@ -207,6 +220,7 @@ DmaUnmap (
 {\r
   MAP_INFO_INSTANCE *Map;\r
   EFI_STATUS        Status;\r
+  VOID              *Buffer;\r
 \r
   if (Mapping == NULL) {\r
     ASSERT (FALSE);\r
@@ -217,17 +231,20 @@ DmaUnmap (
 \r
   Status = EFI_SUCCESS;\r
   if (Map->DoubleBuffer) {\r
-    ASSERT (Map->Operation != MapOperationBusMasterCommonBuffer);\r
+    ASSERT (Map->Operation == MapOperationBusMasterWrite);\r
 \r
-    if (Map->Operation == MapOperationBusMasterCommonBuffer) {\r
+    if (Map->Operation != MapOperationBusMasterWrite) {\r
       Status = EFI_INVALID_PARAMETER;\r
-    } else if (Map->Operation == MapOperationBusMasterWrite) {\r
-      CopyMem ((VOID *)(UINTN)Map->HostAddress, Map->BufferAddress,\r
-        Map->NumberOfBytes);\r
-    }\r
+    } else {\r
+      Buffer = ALIGN_POINTER (Map->BufferAddress, mCpu->DmaBufferAlignment);\r
 \r
-    DmaFreeBuffer (EFI_SIZE_TO_PAGES (Map->NumberOfBytes), Map->BufferAddress);\r
+      mCpu->FlushDataCache (mCpu, (UINTN)Buffer, Map->NumberOfBytes,\r
+              EfiCpuFlushTypeInvalidate);\r
 \r
+      CopyMem ((VOID *)(UINTN)Map->HostAddress, Buffer, Map->NumberOfBytes);\r
+\r
+      FreePool (Map->BufferAddress);\r
+    }\r
   } else {\r
     if (Map->Operation == MapOperationBusMasterWrite) {\r
       //\r