(DisplayFamily == 0x06 && \\r
( \\r
DisplayModel == 0x4E || \\r
- DisplayModel == 0x5E \\r
+ DisplayModel == 0x5E || \\r
+ DisplayModel == 0x55 || \\r
+ DisplayModel == 0x8E || \\r
+ DisplayModel == 0x9E || \\r
+ DisplayModel == 0x66 \\r
) \\r
)\r
\r
#define MSR_SKYLAKE_LASTBRANCH_TOS 0x000001C9\r
\r
\r
+/**\r
+ Core. Power Control Register See http://biosbits.org.\r
+\r
+ @param ECX MSR_SKYLAKE_POWER_CTL (0x000001FC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_POWER_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_POWER_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_POWER_CTL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_POWER_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_POWER_CTL 0x000001FC\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_POWER_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Package. C1E Enable (R/W) When set to '1', will enable the CPU\r
+ /// to switch to the Minimum Enhanced Intel SpeedStep Technology operating\r
+ /// point when all execution cores enter MWAIT (C1).\r
+ ///\r
+ UINT32 C1EEnable:1;\r
+ UINT32 Reserved2:17;\r
+ ///\r
+ /// [Bit 19] Disable Race to Halt Optimization (R/W) Setting this bit\r
+ /// disables the Race to Halt optimization and avoids this optimization\r
+ /// limitation to execute below the most efficient frequency ratio.\r
+ /// Default value is 0 for processors that support Race to Halt\r
+ /// optimization. Default value is 1 for processors that do not support\r
+ /// Race to Halt optimization.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ ///\r
+ /// [Bit 20] Disable Energy Efficiency Optimization (R/W) Setting this bit\r
+ /// disables the P-States energy efficiency optimization. Default value is\r
+ /// 0. Disable/enable the energy efficiency optimization in P-State legacy\r
+ /// mode (when IA32_PM_ENABLE[HWP_ENABLE] = 0), has an effect only in the\r
+ /// turbo range or into PERF_MIN_CTL value if it is not zero set. In HWP\r
+ /// mode (IA32_PM_ENABLE[HWP_ENABLE] == 1), has an effect between the OS\r
+ /// desired or OS maximize to the OS minimize performance setting.\r
+ ///\r
+ UINT32 DisableEnergyEfficiencyOptimization:1;\r
+ UINT32 Reserved3:11;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_POWER_CTL_REGISTER;\r
+\r
+\r
/**\r
Package. Lower 64 Bit OwnerEpoch Component of SGX Key (RO). Low 64 bits of\r
an 128-bit external entropy value for key derivation of an enclave.\r
UINT64 Uint64;\r
} MSR_SKYLAKE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r
\r
+\r
+/**\r
+ Package. NPK Address Used by AET Messages (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE (0x00000080)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE 0x00000080\r
+\r
+/**\r
+ MSR information returned for MSR index\r
+ #MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Lock Bit If set, this MSR cannot be re-written anymore. Lock\r
+ /// bit has to be set in order for the AET packets to be directed to NPK\r
+ /// MMIO.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ UINT32 Reserved:17;\r
+ ///\r
+ /// [Bits 31:18] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
+ ///\r
+ UINT32 ACPIBAR_BASE_ADDRESS:14;\r
+ ///\r
+ /// [Bits 63:32] ACPIBAR_BASE_ADDRESS AET target address in NPK MMIO space.\r
+ ///\r
+ UINT32 Fix_Me_2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_TRACE_HUB_STH_ACPIBAR_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Processor Reserved Memory Range Register - Physical Base Control\r
+ Register (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_PRMRR_PHYS_BASE (0x000001F4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_BASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PRMRR_PHYS_BASE 0x000001F4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] MemType PRMRR BASE MemType.\r
+ ///\r
+ UINT32 MemTypePRMRRBASEMemType:3;\r
+ UINT32 Reserved1:9;\r
+ ///\r
+ /// [Bits 31:12] Base PRMRR Base Address.\r
+ ///\r
+ UINT32 BasePRMRRBaseAddress:20;\r
+ ///\r
+ /// [Bits 45:32] Base PRMRR Base Address.\r
+ ///\r
+ UINT32 Fix_Me_1:14;\r
+ UINT32 Reserved2:18;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PRMRR_PHYS_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Processor Reserved Memory Range Register - Physical Mask Control\r
+ Register (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_PRMRR_PHYS_MASK (0x000001F5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_PHYS_MASK, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PRMRR_PHYS_MASK 0x000001F5\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_PHYS_MASK\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:10;\r
+ ///\r
+ /// [Bit 10] Lock Lock bit for the PRMRR.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ ///\r
+ /// [Bit 11] VLD Enable bit for the PRMRR.\r
+ ///\r
+ UINT32 VLD:1;\r
+ ///\r
+ /// [Bits 31:12] Mask PRMRR MASK bits.\r
+ ///\r
+ UINT32 Fix_Me_2:20;\r
+ ///\r
+ /// [Bits 45:32] Mask PRMRR MASK bits.\r
+ ///\r
+ UINT32 Fix_Me_3:14;\r
+ UINT32 Reserved2:18;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PRMRR_PHYS_MASK_REGISTER;\r
+\r
+\r
+/**\r
+ Core. Valid PRMRR Configurations (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_PRMRR_VALID_CONFIG (0x000001FB)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PRMRR_VALID_CONFIG, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PRMRR_VALID_CONFIG 0x000001FB\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PRMRR_VALID_CONFIG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] 1M supported MEE size.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bit 5] 32M supported MEE size.\r
+ ///\r
+ UINT32 Fix_Me_2:1;\r
+ ///\r
+ /// [Bit 6] 64M supported MEE size.\r
+ ///\r
+ UINT32 Fix_Me_3:1;\r
+ ///\r
+ /// [Bit 7] 128M supported MEE size.\r
+ ///\r
+ UINT32 Fix_Me_4:1;\r
+ UINT32 Reserved2:24;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PRMRR_VALID_CONFIG_REGISTER;\r
+\r
+\r
+/**\r
+ Package. (R/W) The PRMRR range is used to protect Xucode memory from\r
+ unauthorized reads and writes. Any IO access to this range is aborted. This\r
+ register controls the location of the PRMRR range by indicating its starting\r
+ address. It functions in tandem with the PRMRR mask register.\r
+\r
+ @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE (0x000002F4)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE 0x000002F4\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:12;\r
+ ///\r
+ /// [Bits 31:12] Range Base This field corresponds to bits 38:12 of the\r
+ /// base address memory range which is allocated to PRMRR memory.\r
+ ///\r
+ UINT32 Fix_Me_1:20;\r
+ ///\r
+ /// [Bits 38:32] Range Base This field corresponds to bits 38:12 of the\r
+ /// base address memory range which is allocated to PRMRR memory.\r
+ ///\r
+ UINT32 Fix_Me_2:7;\r
+ UINT32 Reserved2:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_BASE_REGISTER;\r
+\r
+\r
+/**\r
+ Package. (R/W) This register controls the size of the PRMRR range by\r
+ indicating which address bits must match the PRMRR base register value.\r
+\r
+ @param ECX MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK (0x000002F5)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK 0x000002F5\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:10;\r
+ ///\r
+ /// [Bit 10] Lock Setting this bit locks all writeable settings in this\r
+ /// register, including itself.\r
+ ///\r
+ UINT32 Fix_Me_1:1;\r
+ ///\r
+ /// [Bit 11] Range_En Indicates whether the PRMRR range is enabled and\r
+ /// valid.\r
+ ///\r
+ UINT32 Fix_Me_2:1;\r
+ UINT32 Reserved2:20;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_UNCORE_PRMRR_PHYS_MASK_REGISTER;\r
+\r
+/**\r
+ Package. Ring Ratio Limit (R/W) This register provides Min/Max Ratio Limits\r
+ for the LLC and Ring.\r
+\r
+ @param ECX MSR_SKYLAKE_RING_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_RING_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_RING_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_RING_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_Ratio This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 Fix_Me_1:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_Ratio Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 Fix_Me_2:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_RING_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Branch Monitoring Global Control (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_BR_DETECT_CTRL (0x00000350)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_CTRL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_BR_DETECT_CTRL 0x00000350\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_CTRL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] EnMonitoring Global enable for branch monitoring.\r
+ ///\r
+ UINT32 EnMonitoring:1;\r
+ ///\r
+ /// [Bit 1] EnExcept Enable branch monitoring event signaling on threshold\r
+ /// trip. The branch monitoring event handler is signaled via the existing\r
+ /// PMI signaling mechanism as programmed from the corresponding local\r
+ /// APIC LVT entry.\r
+ ///\r
+ UINT32 EnExcept:1;\r
+ ///\r
+ /// [Bit 2] EnLBRFrz Enable LBR freeze on threshold trip. This will cause\r
+ /// the LBR frozen bit 58 to be set in IA32_PERF_GLOBAL_STATUS when a\r
+ /// triggering condition occurs and this bit is enabled.\r
+ ///\r
+ UINT32 EnLBRFrz:1;\r
+ ///\r
+ /// [Bit 3] DisableInGuest When set to '1', branch monitoring, event\r
+ /// triggering and LBR freeze actions are disabled when operating at VMX\r
+ /// non-root operation.\r
+ ///\r
+ UINT32 DisableInGuest:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 17:8] WindowSize Window size defined by WindowCntSel. Values 0 -\r
+ /// 1023 are supported. Once the Window counter reaches the WindowSize\r
+ /// count both the Window Counter and all Branch Monitoring Counters are\r
+ /// cleared.\r
+ ///\r
+ UINT32 WindowSize:10;\r
+ UINT32 Reserved2:6;\r
+ ///\r
+ /// [Bits 25:24] WindowCntSel Window event count select: '00 =\r
+ /// Instructions retired. '01 = Branch instructions retired '10 = Return\r
+ /// instructions retired. '11 = Indirect branch instructions retired.\r
+ ///\r
+ UINT32 WindowCntSel:2;\r
+ ///\r
+ /// [Bit 26] CntAndMode When set to '1', the overall branch monitoring\r
+ /// event triggering condition is true only if all enabled counters'\r
+ /// threshold conditions are true. When '0', the threshold tripping\r
+ /// condition is true if any enabled counters' threshold is true.\r
+ ///\r
+ UINT32 CntAndMode:1;\r
+ UINT32 Reserved3:5;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_BR_DETECT_CTRL_REGISTER;\r
+\r
+/**\r
+ Branch Monitoring Global Status (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_BR_DETECT_STATUS (0x00000351)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_BR_DETECT_STATUS, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_BR_DETECT_STATUS 0x00000351\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_BR_DETECT_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Branch Monitoring Event Signaled When set to '1', Branch\r
+ /// Monitoring event signaling is blocked until this bit is cleared by\r
+ /// software.\r
+ ///\r
+ UINT32 BranchMonitoringEventSignaled:1;\r
+ ///\r
+ /// [Bit 1] LBRsValid This status bit is set to '1' if the LBR state is\r
+ /// considered valid for sampling by branch monitoring software.\r
+ ///\r
+ UINT32 LBRsValid:1;\r
+ UINT32 Reserved1:6;\r
+ ///\r
+ /// [Bit 8] CntrHit0 Branch monitoring counter #0 threshold hit. This\r
+ /// status bit is sticky and once set requires clearing by software.\r
+ /// Counter operation continues independent of the state of the bit.\r
+ ///\r
+ UINT32 CntrHit0:1;\r
+ ///\r
+ /// [Bit 9] CntrHit1 Branch monitoring counter #1 threshold hit. This\r
+ /// status bit is sticky and once set requires clearing by software.\r
+ /// Counter operation continues independent of the state of the bit.\r
+ ///\r
+ UINT32 CntrHit1:1;\r
+ UINT32 Reserved2:6;\r
+ ///\r
+ /// [Bits 25:16] CountWindow The current value of the window counter. The\r
+ /// count value is frozen on a valid branch monitoring triggering\r
+ /// condition. This is a 10-bit unsigned value.\r
+ ///\r
+ UINT32 CountWindow:10;\r
+ UINT32 Reserved3:6;\r
+ ///\r
+ /// [Bits 39:32] Count0 The current value of counter 0 updated after each\r
+ /// occurrence of the event being counted. The count value is frozen on a\r
+ /// valid branch monitoring triggering condition (in which case CntrHit0\r
+ /// will also be set). This is an 8-bit signed value (2's complement).\r
+ /// Heuristic events which only increment will saturate and freeze at\r
+ /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
+ /// value 0x7F (+127) and minimum value 0x80 (-128).\r
+ ///\r
+ UINT32 Count0:8;\r
+ ///\r
+ /// [Bits 47:40] Count1 The current value of counter 1 updated after each\r
+ /// occurrence of the event being counted. The count value is frozen on a\r
+ /// valid branch monitoring triggering condition (in which case CntrHit1\r
+ /// will also be set). This is an 8-bit signed value (2's complement).\r
+ /// Heuristic events which only increment will saturate and freeze at\r
+ /// maximum value 0xFF (256). RET-CALL event counter saturate at maximum\r
+ /// value 0x7F (+127) and minimum value 0x80 (-128).\r
+ ///\r
+ UINT32 Count1:8;\r
+ UINT32 Reserved4:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_BR_DETECT_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Package C3 Residency Counter (R/O). Note: C-state values are\r
+ processor specific C-state code names, unrelated to MWAIT extension C-state\r
+ parameters or ACPI C-states.\r
+\r
+ @param ECX MSR_SKYLAKE_PKG_C3_RESIDENCY (0x000003F8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PKG_C3_RESIDENCY);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PKG_C3_RESIDENCY 0x000003F8\r
+\r
+\r
+/**\r
+ Core. Core C1 Residency Counter (R/O). Value since last reset for the Core\r
+ C1 residency. Counter rate is the Max Non-Turbo frequency (same as TSC).\r
+ This counter counts in case both of the core's threads are in an idle state\r
+ and at least one of the core's thread residency is in a C1 state or in one\r
+ of its sub states. The counter is updated only after a core C state exit.\r
+ Note: Always reads 0 if core C1 is unsupported. A value of zero indicates\r
+ that this processor does not support core C1 or never entered core C1 level\r
+ state.\r
+\r
+ @param ECX MSR_SKYLAKE_CORE_C1_RESIDENCY (0x00000660)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C1_RESIDENCY);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_CORE_C1_RESIDENCY 0x00000660\r
+\r
+\r
+/**\r
+ Core. Core C3 Residency Counter (R/O). Will always return 0.\r
+\r
+ @param ECX MSR_SKYLAKE_CORE_C3_RESIDENCY (0x00000662)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_CORE_C3_RESIDENCY);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_CORE_C3_RESIDENCY 0x00000662\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number Enable Control (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_PPIN_CTL (0x0000004E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PPIN_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PPIN_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PPIN_CTL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PPIN_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PPIN_CTL 0x0000004E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PPIN_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
+ ///\r
+ UINT32 LockOut:1;\r
+ ///\r
+ /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
+ ///\r
+ UINT32 Enable_PPIN:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PPIN_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number (R/O). Protected Processor\r
+ Inventory Number (R/O) See Table 2-25.\r
+\r
+ @param ECX MSR_SKYLAKE_PPIN (0x0000004F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PPIN);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PPIN 0x0000004F\r
+\r
+\r
+/**\r
+ Package. Platform Information Contains power management and other model\r
+ specific features enumeration. See http://biosbits.org.\r
+\r
+ @param ECX MSR_SKYLAKE_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 MaximumNon_TurboRatio:8;\r
+ UINT32 Reserved2:7;\r
+ ///\r
+ /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 PPIN_CAP:1;\r
+ UINT32 Reserved3:4;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
+ /// Table 2-25.\r
+ ///\r
+ UINT32 ProgrammableRatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
+ /// Table 2-25.\r
+ ///\r
+ UINT32 ProgrammableTDPLimit:1;\r
+ ///\r
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 ProgrammableTJOFFSET:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved6:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI C-states. `See http://biosbits.org. <http://biosbits.org/>`__.\r
+\r
+ @param ECX MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power) for\r
+ /// the package. The default is set as factory-configured package Cstate\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
+ /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
+ /// supported by the processor are available.\r
+ ///\r
+ UINT32 C_StateLimit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 MWAITRedirectionEnable:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ ///\r
+ /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
+ /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
+ ///\r
+ UINT32 AutomaticC_StateConversionEnable:1;\r
+ UINT32 Reserved3:8;\r
+ ///\r
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C3StateAutoDemotionEnable:1;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C1StateAutoDemotionEnable:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 EnableC3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 EnableC1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Package C State Demotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateDemotionEnable:1;\r
+ ///\r
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateUnDemotionEnable:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Global Machine Check Capability (R/O).\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_MCG_CAP (0x00000179)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_MCG_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_MCG_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_MCG_CAP);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_IA32_MCG_CAP 0x00000179\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_MCG_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Count.\r
+ ///\r
+ UINT32 Count:8;\r
+ ///\r
+ /// [Bit 8] MCG_CTL_P.\r
+ ///\r
+ UINT32 MCG_CTL_P:1;\r
+ ///\r
+ /// [Bit 9] MCG_EXT_P.\r
+ ///\r
+ UINT32 MCG_EXT_P:1;\r
+ ///\r
+ /// [Bit 10] MCP_CMCI_P.\r
+ ///\r
+ UINT32 MCP_CMCI_P:1;\r
+ ///\r
+ /// [Bit 11] MCG_TES_P.\r
+ ///\r
+ UINT32 MCG_TES_P:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 23:16] MCG_EXT_CNT.\r
+ ///\r
+ UINT32 MCG_EXT_CNT:8;\r
+ ///\r
+ /// [Bit 24] MCG_SER_P.\r
+ ///\r
+ UINT32 MCG_SER_P:1;\r
+ ///\r
+ /// [Bit 25] MCG_EM_P.\r
+ ///\r
+ UINT32 MCG_EM_P:1;\r
+ ///\r
+ /// [Bit 26] MCG_ELOG_P.\r
+ ///\r
+ UINT32 MCG_ELOG_P:1;\r
+ UINT32 Reserved2:5;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_MCG_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_SKYLAKE_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and a host-space interface is\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and a host-space interface is\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Temperature Target.\r
+\r
+ @param ECX MSR_SKYLAKE_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ ///\r
+ /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
+ ///\r
+ UINT32 TCCActivationOffset:4;\r
+ UINT32 Reserved2:4;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_TEMPERATURE_TARGET_REGISTER;\r
+\r
+/**\r
+ Package. This register defines the active core ranges for each frequency\r
+ point. NUMCORE[0:7] must be populated in ascending order. NUMCORE[i+1] must\r
+ be greater than NUMCORE[i]. Entries with NUMCORE[i] == 0 will be ignored.\r
+ The last valid entry must have NUMCORE >= the number of cores in the SKU. If\r
+ any of the rules above are broken, the configuration is silently rejected.\r
+\r
+ @param ECX MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES (0x000001AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES 0x000001AE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] NUMCORE_0 Defines the active core ranges for each frequency\r
+ /// point.\r
+ ///\r
+ UINT32 NUMCORE_0:8;\r
+ ///\r
+ /// [Bits 15:8] NUMCORE_1 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_1:8;\r
+ ///\r
+ /// [Bits 23:16] NUMCORE_2 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_2:8;\r
+ ///\r
+ /// [Bits 31:24] NUMCORE_3 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_3:8;\r
+ ///\r
+ /// [Bits 39:32] NUMCORE_4 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_4:8;\r
+ ///\r
+ /// [Bits 47:40] NUMCORE_5 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_5:8;\r
+ ///\r
+ /// [Bits 55:48] NUMCORE_6 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_6:8;\r
+ ///\r
+ /// [Bits 63:56] NUMCORE_7 Defines the active core ranges for each\r
+ /// frequency point.\r
+ ///\r
+ UINT32 NUMCORE_7:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_TURBO_RATIO_LIMIT_CORES_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers Used in RAPL Interfaces (R/O).\r
+\r
+ @param ECX MSR_SKYLAKE_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_RAPL_POWER_UNIT);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Package. Energy Status Units Energy related information\r
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
+ /// micro-joules).\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
+ /// Interfaces.".\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_SKYLAKE_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
+\r
+ @param ECX MSR_SKYLAKE_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_DRAM_ENERGY_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
+ /// to enable DRAM RAPL mode 0 (Direct VR).\r
+ ///\r
+ UINT32 Energy:32;\r
+ UINT32 Reserved:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_DRAM_ENERGY_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_SKYLAKE_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_PERF_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_SKYLAKE_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
+ fields represent the widest possible range of uncore frequencies. Writing to\r
+ these fields allows software to control the minimum and the maximum\r
+ frequency that hardware will select.\r
+\r
+ @param ECX MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT 0x00000620\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
+ /// LLC/Ring.\r
+ ///\r
+ UINT32 MAX_RATIO:7;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
+ /// possible ratio of the LLC/Ring.\r
+ ///\r
+ UINT32 MIN_RATIO:7;\r
+ UINT32 Reserved2:17;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Reserved (R/O) Reads return 0.\r
+\r
+ @param ECX MSR_SKYLAKE_PP0_ENERGY_STATUS (0x00000639)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_SKYLAKE_PP0_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_PP0_ENERGY_STATUS 0x00000639\r
+\r
+\r
+/**\r
+ THREAD. Monitoring Event Select Register (R/W) If CPUID.(EAX=07H,\r
+ ECX=0):EBX.RDT-M[bit 12] = 1.\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_QM_EVTSEL (0x00000C8D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_QM_EVTSEL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_IA32_QM_EVTSEL 0x00000C8D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_QM_EVTSEL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] EventID (RW) Event encoding: 0x00: No monitoring. 0x01: L3\r
+ /// occupancy monitoring. 0x02: Total memory bandwidth monitoring. 0x03:\r
+ /// Local memory bandwidth monitoring. All other encoding reserved.\r
+ ///\r
+ UINT32 EventID:8;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bits 41:32] RMID (RW).\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved2:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_QM_EVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Resource Association Register (R/W).\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_PQR_ASSOC (0x00000C8F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_PQR_ASSOC, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_IA32_PQR_ASSOC 0x00000C8F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_PQR_ASSOC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] RMID.\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved1:22;\r
+ ///\r
+ /// [Bits 51:32] COS (R/W).\r
+ ///\r
+ UINT32 COS:20;\r
+ UINT32 Reserved2:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_PQR_ASSOC_REGISTER;\r
+\r
+\r
+/**\r
+ Package. L3 Class Of Service Mask - COS N (R/W) If CPUID.(EAX=10H,\r
+ ECX=1):EDX.COS_MAX[15:0] >=0.\r
+\r
+ @param ECX MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N);\r
+ AsmWriteMsr64 (MSR_SKYLAKE_IA32_L3_QOS_MASK_N, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_0 0x00000C90\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_1 0x00000C91\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_2 0x00000C92\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_3 0x00000C93\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_4 0x00000C94\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_5 0x00000C95\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_6 0x00000C96\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_7 0x00000C97\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_8 0x00000C98\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_9 0x00000C99\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_10 0x00000C9A\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_11 0x00000C9B\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_12 0x00000C9C\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_13 0x00000C9D\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_14 0x00000C9E\r
+#define MSR_SKYLAKE_IA32_L3_QOS_MASK_15 0x00000C9F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_SKYLAKE_IA32_L3_QOS_MASK_N\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 19:0] CBM: Bit vector of available L3 ways for COS N enforcement.\r
+ ///\r
+ UINT32 CBM:20;\r
+ UINT32 Reserved2:12;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_SKYLAKE_IA32_L3_QOS_MASK_REGISTER;\r
+\r
+\r
#endif\r
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