To prevent the initial MMU->GCD memory space map synchronization from
stripping permissions attributes [which we cannot use in the GCD memory
space map, unfortunately], implement the same approach as x86, and ignore
SetMemoryAttributes() calls during the time SyncCacheConfig() is in
progress. This is a horrible hack, but is currently the only way we can
implement strict permissions on arbitrary memory regions [as opposed to
PE/COFF text/data sections only]
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
\r
#include <Guid/IdleLoopEvent.h>\r
\r
+BOOLEAN mIsFlushingGCD;\r
\r
/**\r
This function flushes the range of addresses from Start to Start+Length\r
// and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r
// after the protocol is installed\r
//\r
+ mIsFlushingGCD = TRUE;\r
SyncCacheConfig (&mCpu);\r
+ mIsFlushingGCD = FALSE;\r
\r
// If the platform is a MPCore system then install the Configuration Table describing the\r
// secondary core states\r
#include <Protocol/DebugSupportPeriodicCallback.h>\r
#include <Protocol/LoadedImage.h>\r
\r
+extern BOOLEAN mIsFlushingGCD;\r
\r
/**\r
This function registers and enables the handler specified by InterruptHandler for a processor\r
UINTN RegionLength;\r
UINTN RegionArmAttributes;\r
\r
+ if (mIsFlushingGCD) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
if ((BaseAddress & (SIZE_4KB - 1)) != 0) {\r
// Minimum granularity is SIZE_4KB (4KB on ARM)\r
DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes));\r