ArmPkg/CpuDxe: ignore attribute changes during SyncCacheConfig()

To prevent the initial MMU->GCD memory space map synchronization from
stripping permissions attributes [which we cannot use in the GCD memory
space map, unfortunately], implement the same approach as x86, and ignore
SetMemoryAttributes() calls during the time SyncCacheConfig() is in
progress. This is a horrible hack, but is currently the only way we can
implement strict permissions on arbitrary memory regions [as opposed to
PE/COFF text/data sections only]

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>

diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.c b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
index 5aa5b874144ac08ac80da3503fe4756d832b6ba1..5e923d45b71531ba5947135f161024228a27b5e6 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.c
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.c
@@ -17,6 +17,7 @@
 \r
 #include <Guid/IdleLoopEvent.h>\r
 \r
+BOOLEAN                   mIsFlushingGCD;\r
 \r
 /**\r
   This function flushes the range of addresses from Start to Start+Length\r
@@ -261,7 +262,9 @@ CpuDxeInitialize (
   // and that calls EFI_CPU_ARCH_PROTOCOL.SetMemoryAttributes, so this code needs to go\r
   // after the protocol is installed\r
   //\r
+  mIsFlushingGCD = TRUE;\r
   SyncCacheConfig (&mCpu);\r
+  mIsFlushingGCD = FALSE;\r
 \r
   // If the platform is a MPCore system then install the Configuration Table describing the\r
   // secondary core states\r

diff --git a/ArmPkg/Drivers/CpuDxe/CpuDxe.h b/ArmPkg/Drivers/CpuDxe/CpuDxe.h
index a00fc3064362de158fb757ab498087218a302889..a46db8d2575452c004f1c4d922ea9e10cf37764b 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/CpuDxe.h
+++ b/ArmPkg/Drivers/CpuDxe/CpuDxe.h
@@ -37,6 +37,7 @@
 #include <Protocol/DebugSupportPeriodicCallback.h>\r
 #include <Protocol/LoadedImage.h>\r
 \r
+extern BOOLEAN mIsFlushingGCD;\r
 \r
 /**\r
   This function registers and enables the handler specified by InterruptHandler for a processor\r

diff --git a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
index ebe593d1c325d9e70dfba18e7a078371219b2561..0f36a058407afb1cdc0b82f434956a22e324d0f0 100644 (file)
--- a/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
+++ b/ArmPkg/Drivers/CpuDxe/CpuMmuCommon.c
@@ -188,6 +188,10 @@ CpuSetMemoryAttributes (
   UINTN       RegionLength;\r
   UINTN       RegionArmAttributes;\r
 \r
+  if (mIsFlushingGCD) {\r
+    return EFI_SUCCESS;\r
+  }\r
+\r
   if ((BaseAddress & (SIZE_4KB - 1)) != 0) {\r
     // Minimum granularity is SIZE_4KB (4KB on ARM)\r
     DEBUG ((EFI_D_PAGE, "CpuSetMemoryAttributes(%lx, %lx, %lx): Minimum ganularity is SIZE_4KB\n", BaseAddress, Length, EfiAttributes));\r