Fix the bug which incorrectly programs the 64bit base address register in the PCI...

Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Elvin Li <elvin.li@intel.com>
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@14318 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
index e17f4bae4466b3af40f391630d8c40bc12a14e8b..d8d988cbfc270b223503d34aad5ef50bcb589bef 100644 (file)
--- a/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
+++ b/MdeModulePkg/Bus/Pci/PciBusDxe/PciResourceSupport.c
@@ -1,7 +1,7 @@
 /** @file\r
   PCI resouces support functions implemntation for PCI Bus module.\r
 \r
-Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.<BR>\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -1472,7 +1472,14 @@ ProgramPpbApperture (
 \r
   case PPB_BAR_0:\r
   case PPB_BAR_1:\r
-    PciIo->Pci.Write (\r
+    switch ((Node->PciDev->PciBar[Node->Bar]).BarType) {\r
+\r
+      case PciBarTypeIo16:\r
+      case PciBarTypeIo32:\r
+      case PciBarTypeMem32:\r
+      case PciBarTypePMem32:\r
+\r
+        PciIo->Pci.Write (\r
                  PciIo,\r
                  EfiPciIoWidthUint32,\r
                  (Node->PciDev->PciBar[Node->Bar]).Offset,\r
@@ -1480,9 +1487,40 @@ ProgramPpbApperture (
                  &Address\r
                  );\r
 \r
-    Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
-    Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+        Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+        Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+        break;\r
+\r
+      case PciBarTypeMem64:\r
+      case PciBarTypePMem64:\r
 \r
+        Address32 = (UINT32) (Address & 0x00000000FFFFFFFF);\r
+\r
+        PciIo->Pci.Write (\r
+                 PciIo,\r
+                 EfiPciIoWidthUint32,\r
+                 (Node->PciDev->PciBar[Node->Bar]).Offset,\r
+                 1,\r
+                 &Address32\r
+                 );\r
+\r
+        Address32 = (UINT32) RShiftU64 (Address, 32);\r
+\r
+        PciIo->Pci.Write (\r
+                 PciIo,\r
+                 EfiPciIoWidthUint32,\r
+                 (UINT8) ((Node->PciDev->PciBar[Node->Bar]).Offset + 4),\r
+                 1,\r
+                 &Address32\r
+                 );\r
+\r
+        Node->PciDev->PciBar[Node->Bar].BaseAddress = Address;\r
+        Node->PciDev->PciBar[Node->Bar].Length      = Node->Length;\r
+        break;\r
+\r
+      default:\r
+        break;\r
+    }\r
     break;\r
 \r
   case PPB_IO_RANGE:\r