--- /dev/null
+/** @file\r
+ This PPI opens or closes an I/O aperture in a ISA HOST controller.\r
+\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ @par Revision Reference:\r
+ This PPI is from PI Version 1.2.1.\r
+\r
+**/\r
+\r
+#ifndef __ISA_HC_PPI_H__\r
+#define __ISA_HC_PPI_H__\r
+\r
+#define EFI_ISA_HC_PPI_GUID \\r
+ { \\r
+ 0x8d48bd70, 0xc8a3, 0x4c06, {0x90, 0x1b, 0x74, 0x79, 0x46, 0xaa, 0xc3, 0x58} \\r
+ }\r
+\r
+typedef struct _EFI_ISA_HC_PPI EFI_ISA_HC_PPI;\r
+typedef struct _EFI_ISA_HC_PPI *PEFI_ISA_HC_PPI;\r
+\r
+/**\r
+ Open I/O aperture.\r
+\r
+ This function opens an I/O aperture in a ISA Host Controller for the I/O\r
+ addresses specified by IoAddress to IoAddress + IoLength - 1. It is possible\r
+ that more than one caller may be assigned to the same aperture.\r
+ It may be possible that a single hardware aperture may be used for more than\r
+ one device. This function tracks the number of times that each aperture is \r
+ referenced, and doesa not close the hardware aperture (via CloseIoAperture())\r
+ until there are no more references to it.\r
+ \r
+ @param This A pointer to this instance of the EFI_ISA_HC_PPI.\r
+ @param IoAddress An unsigned integer that specifies the first byte of\r
+ the I/O space required.\r
+ @param IoLength An unsigned integer that specifies the number of\r
+ bytes of the I/O space required.\r
+ @param IoApertureHandle A pointer to the returned I/O aperture handle.\r
+ This value can be used on subsequent calls to CloseIoAperture().\r
+\r
+ @retval EFI_SUCCESS The I/O aperture was opened successfully.\r
+ @retval EFI_UNSUPPORTED The ISA Host Controller is a subtractive-decode controller.\r
+ @retval EFI_OUT_OF_RESOURCES There is no available I/O aperture.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_ISA_HC_OPEN_IO) (\r
+ IN CONST EFI_ISA_HC_PPI *This,\r
+ IN UINT16 IoAddress,\r
+ IN UINT16 IoLength,\r
+ OUT UINT64 *IoApertureHandle\r
+ );\r
+\r
+/**\r
+ Close I/O aperture.\r
+\r
+ This function closes a previously opened I/O aperture handle. If there are no\r
+ more I/O aperture handles that refer to the hardware I/O aperture resource,\r
+ then the hardware I/O aperture is closed.\r
+ It may be possible that a single hardware aperture may be used for more than\r
+ one device. This function tracks the number of times that each aperture is\r
+ referenced, and does not close the hardware aperture (via CloseIoAperture())\r
+ until there are no more references to it.\r
+\r
+ @param This A pointer to this instance of the EFI_ISA_HC_PPI.\r
+ @param IoApertureHandle The I/O aperture handle previously returned from a\r
+ call to OpenIoAperture().\r
+\r
+ @retval EFI_SUCCESS The I/O aperture was closed successfully.\r
+**/ \r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_ISA_HC_CLOSE_IO) (\r
+ IN CONST EFI_ISA_HC_PPI *This,\r
+ IN UINT64 IoApertureHandle\r
+ );\r
+\r
+///\r
+/// This PPI provides functions for opening or closing an I/O aperture.\r
+///\r
+struct _EFI_ISA_HC_PPI {\r
+ ///\r
+ /// An unsigned integer that specifies the version of the PPI structure.\r
+ ///\r
+ UINT32 Version;\r
+ ///\r
+ /// The address of the ISA/LPC Bridge device.\r
+ /// For PCI, this is the segment, bus, device and function of the a ISA/LPC\r
+ /// Bridge device.\r
+ ///\r
+ /// If bits 24-31 are 0, then the definition is:\r
+ /// Bits 0:2 - Function\r
+ /// Bits 3-7 - Device\r
+ /// Bits 8:15 - Bus\r
+ /// Bits 16-23 - Segment\r
+ /// Bits 24-31 - Bus Type\r
+ /// If bits 24-31 are 0xff, then the definition is platform-specific.\r
+ ///\r
+ UINT32 Address;\r
+ ///\r
+ /// Opens an aperture on a positive-decode ISA Host Controller.\r
+ ///\r
+ EFI_PEI_ISA_HC_OPEN_IO OpenIoAperture;\r
+ ///\r
+ /// Closes an aperture on a positive-decode ISA Host Controller.\r
+ ///\r
+ EFI_PEI_ISA_HC_CLOSE_IO CloseIoAperture;\r
+};\r
+\r
+extern EFI_GUID gEfiIsaHcPpiGuid;\r
+\r
+#endif \r
--- /dev/null
+/** @file\r
+ This PPI provides the super I/O register access functionality.\r
+\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ @par Revision Reference:\r
+ This PPI is from PI Version 1.2.1.\r
+\r
+**/\r
+\r
+#ifndef __EFI_SUPER_IO_PPI_H__\r
+#define __EFI_SUPER_IO_PPI_H__\r
+\r
+#include <Protocol/SuperIo.h>\r
+\r
+#define EFI_SIO_PPI_GUID \\r
+ { \\r
+ 0x23a464ad, 0xcb83, 0x48b8, {0x94, 0xab, 0x1a, 0x6f, 0xef, 0xcf, 0xe5, 0x22} \\r
+ }\r
+\r
+typedef struct _EFI_SIO_PPI EFI_SIO_PPI;\r
+typedef struct _EFI_SIO_PPI *PEFI_SIO_PPI;\r
+\r
+typedef UINT16 EFI_SIO_REGISTER;\r
+#define EFI_SIO_REG(ldn,reg) (EFI_SIO_REGISTER) (((ldn) << 8) | reg)\r
+#define EFI_SIO_LDN_GLOBAL 0xFF\r
+\r
+/**\r
+ Read a Super I/O register.\r
+ \r
+ The register is specified as an 8-bit logical device number and an 8-bit\r
+ register value. The logical device numbers for specific SIO devices can be\r
+ determined using the Info member of the PPI structure.\r
+ \r
+ @param This A pointer to this instance of the EFI_SIO_PPI.\r
+ @param ExitCfgMode A boolean specifying whether the driver should turn on\r
+ configuration mode (FALSE) or turn off configuration mode\r
+ (TRUE) after completing the read operation. The driver must\r
+ track the current state of the configuration mode (if any)\r
+ and turn on configuration mode (if necessary) prior to\r
+ register access.\r
+ @param Register A value specifying the logical device number (bits 15:8) \r
+ and the register to read (bits 7:0). The logical device \r
+ number of EFI_SIO_LDN_GLOBAL indicates that global\r
+ registers will be used.\r
+ @param IoData A pointer to the returned register value.\r
+\r
+ @retval EFI_SUCCESS Success.\r
+ @regval EFI_TIMEOUT The register could not be read in the a reasonable\r
+ amount of time. The exact time is device-specific.\r
+ @retval EFI_INVALID_PARAMETERS Register was out of range for this device.\r
+ @retval EFI_INVALID_PARAMETERS IoData was NULL\r
+ @retval EFI_DEVICE_ERROR There was a device fault or the device was not present.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_SIO_REGISTER_READ)(\r
+ IN CONST EFI_SIO_PPI *This,\r
+ IN BOOLEAN ExitCfgMode,\r
+ IN EFI_SIO_REGISTER Register,\r
+ OUT UINT8 *IoData\r
+ );\r
+\r
+/**\r
+ Write a Super I/O register.\r
+\r
+ The register is specified as an 8-bit logical device number and an 8-bit register\r
+ value. The logical device numbers for specific SIO devices can be determined\r
+ using the Info member of the PPI structure.\r
+\r
+ @param This A pointer to this instance of the EFI_SIO_PPI.\r
+ @param ExitCfgMode A boolean specifying whether the driver should turn on\r
+ configuration mode (FALSE) or turn off configuration mode\r
+ (TRUE) after completing the read operation. The driver must\r
+ track the current state of the configuration mode (if any)\r
+ and turn on configuration mode (if necessary) prior to\r
+ register access.\r
+ @param Register A value specifying the logical device number (bits 15:8) \r
+ and the register to read (bits 7:0). The logical device \r
+ number of EFI_SIO_LDN_GLOBAL indicates that global\r
+ registers will be used.\r
+ @param IoData A pointer to the returned register value.\r
+\r
+ @retval EFI_SUCCESS Success.\r
+ @regval EFI_TIMEOUT The register could not be read in the a reasonable\r
+ amount of time. The exact time is device-specific.\r
+ @retval EFI_INVALID_PARAMETERS Register was out of range for this device.\r
+ @retval EFI_INVALID_PARAMETERS IoData was NULL\r
+ @retval EFI_DEVICE_ERROR There was a device fault or the device was not present.\r
+**/ \r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_SIO_REGISTER_WRITE)(\r
+ IN CONST EFI_SIO_PPI *This,\r
+ IN BOOLEAN ExitCfgMode,\r
+ IN EFI_SIO_REGISTER Register,\r
+ IN UINT8 IoData\r
+ );\r
+\r
+/**\r
+ Provides an interface for a table based programming of the Super I/O registers.\r
+\r
+ The Modify() function provides an interface for table based programming of the\r
+ Super I/O registers. This function can be used to perform programming of\r
+ multiple Super I/O registers with a single function call. For each table entry,\r
+ the Register is read, its content is bitwise ANDed with AndMask, and then ORed\r
+ with OrMask before being written back to the Register. The Super I/O driver\r
+ must track the current state of the Super I/O and enable the configuration mode\r
+ of Super I/O if necessary prior to table processing. Once the table is processed,\r
+ the Super I/O device must be returned to the original state.\r
+ \r
+ @param This A pointer to this instance of the EFI_SIO_PPI.\r
+ @param Command A pointer to an array of NumberOfCommands EFI_SIO_REGISTER_MODIFY\r
+ structures. Each structure specifies a single Super I/O register\r
+ modify operation.\r
+ @param NumberOfCommands The number of elements in the Command array.\r
+\r
+ @retval EFI_SUCCESS The operation completed successfully.\r
+ @retval EFI_INVALID_PARAMETERS Command is NULL.\r
+**/ \r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_PEI_SIO_REGISTER_MODIFY)(\r
+ IN CONST EFI_SIO_PPI *This,\r
+ IN CONST EFI_SIO_REGISTER_MODIFY *Command,\r
+ IN UINTN NumberOfCommands\r
+ );\r
+\r
+///\r
+/// Specifies the end of the information list.\r
+///\r
+#define EFI_ACPI_PNP_HID_END 0\r
+\r
+typedef UINT32 EFI_ACPI_HID;\r
+typedef UINT32 EFI_ACPI_UID;\r
+#pragma pack(1)\r
+typedef struct _EFI_SIO_INFO {\r
+ EFI_ACPI_HID Hid;\r
+ EFI_ACPI_UID Uid;\r
+ UINT8 Ldn;\r
+} EFI_SIO_INFO, *PEFI_SIO_INFO;\r
+#pragma pack()\r
+\r
+///\r
+/// This PPI provides low-level access to Super I/O registers using Read() and\r
+/// Write(). It also uniquely identifies this Super I/O controller using a GUID\r
+/// and provides mappings between ACPI style PNP IDs and the logical device numbers.\r
+/// There is one instance of this PPI per Super I/O device.\r
+///\r
+struct _EFI_SIO_PPI {\r
+ ///\r
+ /// This function reads a register's value from the Super I/O controller.\r
+ ///\r
+ EFI_PEI_SIO_REGISTER_READ Read;\r
+ ///\r
+ /// This function writes a value to a register in the Super I/O controller.\r
+ ///\r
+ EFI_PEI_SIO_REGISTER_WRITE Write;\r
+ ///\r
+ /// This function modifies zero or more registers in the Super I/O controller\r
+ /// using a table.\r
+ ///\r
+ EFI_PEI_SIO_REGISTER_MODIFY Modify;\r
+ ///\r
+ /// This GUID uniquely identifies the Super I/O controller.\r
+ ///\r
+ EFI_GUID SioGuid;\r
+ ///\r
+ /// This pointer is to an array which maps EISA identifiers to logical devices numbers.\r
+ ///\r
+ PEFI_SIO_INFO Info;\r
+};\r
+\r
+extern EFI_GUID gEfiSioPpiGuid;\r
+\r
+#endif \r
--- /dev/null
+/** @file\r
+ ISA HC Protocol as defined in the PI 1.2.1 specification.\r
+\r
+ This protocol provides registration for ISA devices on a positive- or\r
+ subtractive-decode ISA bus. It allows devices to be registered and also\r
+ handles opening and closing the apertures which are positively-decoded.\r
+\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ @par Revision Reference:\r
+ This protocol is from PI Version 1.2.1.\r
+\r
+**/\r
+\r
+#ifndef __ISA_HC_PROTOCOL_H__\r
+#define __ISA_HC_PROTOCOL_H__\r
+\r
+#define EFI_ISA_HC_PROTOCOL_GUID \\r
+ { \\r
+ 0xbcdaf080, 0x1bde, 0x4e22, {0xae, 0x6a, 0x43, 0x54, 0x1e, 0x12, 0x8e, 0xc4} \\r
+ }\r
+\r
+#define EFI_ISA_HC_SERVICE_BINDING_PROTOCOL_GUID \\r
+ { \\r
+ 0xfad7933a, 0x6c21, 0x4234, {0xa4, 0x34, 0x0a, 0x8a, 0x0d, 0x2b, 0x07, 0x81} \\r
+ }\r
+\r
+typedef struct _EFI_ISA_HC_PROTOCOL EFI_ISA_HC_PROTOCOL;\r
+typedef struct _EFI_ISA_HC_PROTOCOL *PEFI_ISA_HC_PROTOCOL;\r
+\r
+/**\r
+ Open I/O aperture.\r
+\r
+ This function opens an I/O aperture in a ISA Host Controller for the I/O addresses\r
+ specified by IoAddress to IoAddress + IoLength - 1. It may be possible that a\r
+ single hardware aperture may be used for more than one device. This function\r
+ tracks the number of times that each aperture is referenced, and does not close\r
+ the hardware aperture (via CloseIoAperture()) until there are no more references to it.\r
+\r
+ @param This A pointer to this instance of the EFI_ISA_HC_PROTOCOL.\r
+ @param IoAddress An unsigned integer that specifies the first byte of the\r
+ I/O space required.\r
+ @param IoLength An unsigned integer that specifies the number of bytes\r
+ of the I/O space required.\r
+ @param IoApertureHandle A pointer to the returned I/O aperture handle. This\r
+ value can be used on subsequent calls to CloseIoAperture().\r
+\r
+ @retval EFI_SUCCESS The I/O aperture was opened successfully.\r
+ @retval EFI_UNSUPPORTED The ISA Host Controller is a subtractive-decode controller.\r
+ @retval EFI_OUT_OF_RESOURCES There is no available I/O aperture.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_ISA_HC_OPEN_IO) (\r
+ IN CONST EFI_ISA_HC_PROTOCOL *This,\r
+ IN UINT16 IoAddress,\r
+ IN UINT16 IoLength,\r
+ OUT UINT64 *IoApertureHandle\r
+ );\r
+\r
+/**\r
+ Close I/O aperture.\r
+\r
+ This function closes a previously opened I/O aperture handle. If there are no\r
+ more I/O aperture handles that refer to the hardware I/O aperture resource,\r
+ then the hardware I/O aperture is closed. It may be possible that a single\r
+ hardware aperture may be used for more than one device. This function tracks\r
+ the number of times that each aperture is referenced, and does not close the\r
+ hardware aperture (via CloseIoAperture()) until there are no more references to it.\r
+\r
+ @param This A pointer to this instance of the EFI_ISA_HC_PROTOCOL.\r
+ @param IoApertureHandle The I/O aperture handle previously returned from a \r
+ call to OpenIoAperture().\r
+\r
+ @retval EFI_SUCCESS The IO aperture was closed successfully.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_ISA_HC_CLOSE_IO) (\r
+ IN CONST EFI_ISA_HC_PROTOCOL *This,\r
+ IN UINT64 IoApertureHandle\r
+ );\r
+\r
+///\r
+/// ISA HC Protocol\r
+///\r
+struct _EFI_ISA_HC_PROTOCOL {\r
+ ///\r
+ /// The version of this protocol. Higher version numbers are backward\r
+ /// compatible with lower version numbers.\r
+ ///\r
+ UINT32 Version;\r
+ ///\r
+ /// Open an I/O aperture.\r
+ ///\r
+ EFI_ISA_HC_OPEN_IO OpenIoAperture;\r
+ ///\r
+ /// Close an I/O aperture.\r
+ ///\r
+ EFI_ISA_HC_CLOSE_IO CloseIoAperture;\r
+};\r
+\r
+///\r
+/// Reference to variable defined in the .DEC file\r
+///\r
+extern EFI_GUID gEfiIsaHcProtocolGuid;\r
+extern EFI_GUID gEfiIsaHcServiceBindingProtocolGuid;\r
+\r
+#endif // __ISA_HC_H__\r
--- /dev/null
+/** @file\r
+ The Super I/O Control Protocol is installed by the Super I/O driver. It provides\r
+ the low-level services for SIO devices that enable them to be used in the UEFI\r
+ driver model.\r
+\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+ @par Revision Reference:\r
+ This protocol is from PI Version 1.2.1.\r
+\r
+**/\r
+\r
+#ifndef __EFI_SUPER_IO_CONTROL_PROTOCOL_H__\r
+#define __EFI_SUPER_IO_CONTROL_PROTOCOL_H__\r
+\r
+#define EFI_SIO_CONTROL_PROTOCOL_GUID \\r
+ { \\r
+ 0xb91978df, 0x9fc1, 0x427d, { 0xbb, 0x5, 0x4c, 0x82, 0x84, 0x55, 0xca, 0x27 } \\r
+ }\r
+\r
+typedef struct _EFI_SIO_CONTROL_PROTOCOL EFI_SIO_CONTROL_PROTOCOL;\r
+typedef struct _EFI_SIO_CONTROL_PROTOCOL *PEFI_SIO_CONTROL_PROTOCOL;\r
+\r
+/**\r
+ Enable an ISA-style device.\r
+\r
+ This function enables a logical ISA device and, if necessary, configures it\r
+ to default settings, including memory, I/O, DMA and IRQ resources.\r
+\r
+ @param This A pointer to this instance of the EFI_SIO_CONTROL_PROTOCOL.\r
+\r
+ @retval EFI_SUCCESS The device is enabled successfully.\r
+ @retval EFI_OUT_OF_RESOURCES The device could not be enabled because there\r
+ were insufficient resources either for the device \r
+ itself or for the records needed to track the device.\r
+ @retval EFI_ALREADY_STARTED The device is already enabled.\r
+ @retval EFI_UNSUPPORTED The device cannot be enabled.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SIO_CONTROL_ENABLE)(\r
+ IN CONST EFI_SIO_CONTROL_PROTOCOL *This\r
+ );\r
+\r
+/**\r
+ Disable a logical ISA device.\r
+\r
+ This function disables a logical ISA device so that it no longer consumes\r
+ system resources, such as memory, I/O, DMA and IRQ resources. Enough information\r
+ must be available so that subsequent Enable() calls would properly reconfigure\r
+ the device.\r
+\r
+ @param This A pointer to this instance of the EFI_SIO_CONTROL_PROTOCOL.\r
+\r
+ @retval EFI_SUCCESS The device is disabled successfully.\r
+ @retval EFI_OUT_OF_RESOURCES The device could not be disabled because there\r
+ were insufficient resources either for the device \r
+ itself or for the records needed to track the device.\r
+ @retval EFI_ALREADY_STARTED The device is already disabled.\r
+ @retval EFI_UNSUPPORTED The device cannot be disabled.\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI *EFI_SIO_CONTROL_DISABLE)(\r
+ IN CONST EFI_SIO_CONTROL_PROTOCOL *This\r
+ );\r
+\r
+struct _EFI_SIO_CONTROL_PROTOCOL {\r
+ ///\r
+ /// The version of this protocol.\r
+ ///\r
+ UINT32 Version;\r
+ ///\r
+ /// Enable a device.\r
+ ///\r
+ EFI_SIO_CONTROL_ENABLE EnableDevice;\r
+ ///\r
+ /// Disable a device.\r
+ ///\r
+ EFI_SIO_CONTROL_DISABLE DisableDevice;\r
+};\r
+\r
+extern EFI_GUID gEfiSioControlProtocolGuid;\r
+\r
+#endif // __EFI_SUPER_IO_CONTROL_PROTOCOL_H__\r
## Include/Ppi/VectorHandoffInfo.h\r
gEfiVectorHandoffInfoPpiGuid = { 0x3cd652b4, 0x6d33, 0x4dce, { 0x89, 0xdb, 0x83, 0xdf, 0x97, 0x66, 0xfc, 0xca }}\r
\r
+ ## Include/Ppi/IsaHc.h\r
+ gEfiIsaHcPpiGuid = { 0x8d48bd70, 0xc8a3, 0x4c06, {0x90, 0x1b, 0x74, 0x79, 0x46, 0xaa, 0xc3, 0x58 } }\r
+\r
+ ## Include/Ppi/SuperIo.h\r
+ gEfiSioPpiGuid = { 0x23a464ad, 0xcb83, 0x48b8, {0x94, 0xab, 0x1a, 0x6f, 0xef, 0xcf, 0xe5, 0x22 } }\r
+\r
#\r
# PPIs defined in PI 1.3.\r
#\r
## Include/Protocol/SmmEndOfDxe.h\r
gEfiSmmEndOfDxeProtocolGuid = { 0x24e70042, 0xd5c5, 0x4260, { 0x8c, 0x39, 0xa, 0xd3, 0xaa, 0x32, 0xe9, 0x3d }}\r
\r
+ ## Include/Protocol/IsaHc.h\r
+ gEfiIsaHcProtocolGuid = { 0xbcdaf080, 0x1bde, 0x4e22, {0xae, 0x6a, 0x43, 0x54, 0x1e, 0x12, 0x8e, 0xc4 } }\r
+ gEfiIsaHcServiceBindingProtocolGuid = { 0xfad7933a, 0x6c21, 0x4234, {0xa4, 0x34, 0x0a, 0x8a, 0x0d, 0x2b, 0x07, 0x81 } }\r
+\r
+ ## Include/Protocol/SuperIoControl.h\r
+ gEfiSioControlProtocolGuid = { 0xb91978df, 0x9fc1, 0x427d, { 0xbb, 0x5, 0x4c, 0x82, 0x84, 0x55, 0xca, 0x27 } }\r
+\r
## Include/Protocol/PiPcdInfo.h\r
gEfiGetPcdInfoProtocolGuid = { 0xfd0f4478, 0xefd, 0x461d, { 0xba, 0x2d, 0xe5, 0x8c, 0x45, 0xfd, 0x5f, 0x5e } }\r
\r
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