UefiCpuPkg/Include/Register/ArchitecturalMsr.h: Change structure definition.

V3 changes include:
  1. Keep ReservedX not change if bit info not changed for this field.

V2 changes include:
  1. Use X in ReservedX fields from totally new value if MSR structure definition changed.
     For example, if in current structure, the max reserved variable is Reserved2, in new
     definition, reserved variable is begin with Reserved3.

V1 Changes includes:
  1. Change fields which is reserved in old version: MSR_IA32_RTIT_CTL_REGISTER

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>

diff --git a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
index b467ffaf2664cc0316b846aee6db2f0a81d89901..22d64e995b449eeb90fe5278acae5c7e68a4e261 100644 (file)
--- a/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
+++ b/UefiCpuPkg/Include/Register/ArchitecturalMsr.h
@@ -4647,7 +4647,14 @@ typedef union {
     /// [Bit 3] User.\r
     ///\r
     UINT32  User:1;\r
-    UINT32  Reserved1:2;\r
+    ///\r
+    /// [Bit 4] PwrEvtEn.\r
+    ///\r
+    UINT32  PwrEvtEn:1;\r
+    ///\r
+    /// [Bit 5] FUPonPTW.\r
+    ///\r
+    UINT32  FUPonPTW:1;\r
     ///\r
     /// [Bit 6] FabricEn. If (CPUID.(EAX=07H, ECX=0):ECX[3] = 1).\r
     ///\r
@@ -4672,7 +4679,10 @@ typedef union {
     /// [Bit 11] DisRETC.\r
     ///\r
     UINT32  DisRETC:1;\r
-    UINT32  Reserved2:1;\r
+    ///\r
+    /// [Bit 12] PTWEn.\r
+    ///\r
+    UINT32  PTWEn:1;\r
     ///\r
     /// [Bit 13] BranchEn.\r
     ///\r