# ARM processor package.\r
#\r
# Copyright (c) 2009 - 2010, Apple Inc. All rights reserved.<BR>\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
#\r
# This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
[Guids.common]\r
gArmTokenSpaceGuid = { 0xBB11ECFE, 0x820F, 0x4968, { 0xBB, 0xA6, 0xF7, 0x6A, 0xFE, 0x30, 0x25, 0x96 } }\r
\r
+ ## ARM MPCore table\r
+ # Include/Guid/ArmMpCoreInfo.h\r
+ gArmMpCoreInfoGuid = { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
+\r
+[Ppis]\r
+ ## Include/Ppi/ArmMpCoreInfo.h\r
+ gArmMpCoreInfoPpiGuid = { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
+\r
[Protocols.common]\r
gVirtualUncachedPagesProtocolGuid = { 0xAD651C7D, 0x3C22, 0x4DBF, { 0x92, 0xe8, 0x38, 0xa7, 0xcd, 0xae, 0x87, 0xb2 } }\r
\r
//\r
SyncCacheConfig (&mCpu);\r
\r
+ // If the platform is a MPCore system then install the Configuration Table describing the\r
+ // secondary core states\r
+ if (ArmIsMPCore()) {\r
+ PublishArmProcessorTable();\r
+ }\r
+\r
//\r
// Setup a callback for idle events\r
//\r
IN EFI_PHYSICAL_ADDRESS BaseAddress\r
);\r
\r
+/**\r
+ * Publish ARM Processor Data table in UEFI SYSTEM Table.\r
+ * @param HobStart Pointer to the beginning of the HOB List from PEI.\r
+ *\r
+ * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.\r
+ * If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory\r
+ * and a pointer is assigned to it in ARM processor table. Then the ARM processor table is\r
+ * installed in EFI configuration table.\r
+**/\r
+VOID\r
+EFIAPI\r
+PublishArmProcessorTable(\r
+ VOID\r
+ );\r
\r
extern VIRTUAL_UNCACHED_PAGES_PROTOCOL gVirtualUncachedPages;\r
\r
[Sources.ARM]\r
CpuDxe.c\r
CpuDxe.h\r
+ CpuMpCore.c\r
Exception.c\r
\r
#\r
#\r
ExceptionSupport.ARMv6.asm | RVCT\r
ExceptionSupport.ARMv6.S | GCC\r
- Mmu.c\r
+ Mmu.c \r
\r
\r
[Packages]\r
MdeModulePkg/MdeModulePkg.dec\r
\r
[LibraryClasses]\r
+ ArmLib\r
BaseMemoryLib\r
CacheMaintenanceLib\r
CpuLib\r
DebugLib\r
DefaultExceptionHandlerLib\r
DxeServicesTableLib\r
+ HobLib\r
PeCoffGetEntryPointLib\r
+ UefiDriverEntryPoint\r
UefiLib\r
\r
[Protocols]\r
\r
[Guids]\r
gEfiDebugImageInfoTableGuid\r
+ gArmMpCoreInfoGuid\r
gIdleLoopEventGuid\r
\r
[Pcd.common]\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+\r
+#include <Guid/ArmMpCoreInfo.h>\r
+\r
+ARM_PROCESSOR_TABLE mArmProcessorTableTemplate = {\r
+ {\r
+ EFI_ARM_PROCESSOR_TABLE_SIGNATURE,\r
+ 0,\r
+ EFI_ARM_PROCESSOR_TABLE_REVISION,\r
+ EFI_ARM_PROCESSOR_TABLE_OEM_ID,\r
+ EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID,\r
+ EFI_ARM_PROCESSOR_TABLE_OEM_REVISION,\r
+ EFI_ARM_PROCESSOR_TABLE_CREATOR_ID,\r
+ EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION,\r
+ 0,\r
+ 0\r
+ }, //ARM Processor table header\r
+ 0, // Number of entries in ARM processor Table\r
+ NULL // ARM Processor Table\r
+};\r
+\r
+/** Publish ARM Processor Data table in UEFI SYSTEM Table.\r
+ * @param: HobStart Pointer to the beginning of the HOB List from PEI.\r
+ *\r
+ * Description : This function iterates through HOB list and finds ARM processor Table Entry HOB.\r
+ * If the ARM processor Table Entry HOB is found, the HOB data is copied to run-time memory\r
+ * and a pointer is assigned to it in ARM processor table. Then the ARM processor table is\r
+ * installed in EFI configuration table.\r
+**/\r
+VOID\r
+EFIAPI\r
+PublishArmProcessorTable (\r
+ VOID\r
+ )\r
+{\r
+ EFI_PEI_HOB_POINTERS Hob;\r
+\r
+ Hob.Raw = GetHobList ();\r
+\r
+ // Iterate through the HOBs and find if there is ARM PROCESSOR ENTRY HOB\r
+ for (; !END_OF_HOB_LIST(Hob); Hob.Raw = GET_NEXT_HOB(Hob)) {\r
+ // Check for Correct HOB type\r
+ if ((GET_HOB_TYPE (Hob)) == EFI_HOB_TYPE_GUID_EXTENSION) {\r
+ // Check for correct GUID type\r
+ if (CompareGuid(&(Hob.Guid->Name), &gArmMpCoreInfoGuid)) {\r
+ ARM_PROCESSOR_TABLE *ArmProcessorTable;\r
+ EFI_STATUS Status;\r
+\r
+ // Allocate Runtime memory for ARM processor table\r
+ ArmProcessorTable = (ARM_PROCESSOR_TABLE*)AllocateRuntimePool(sizeof(ARM_PROCESSOR_TABLE));\r
+\r
+ // Check if the memory allocation is succesful or not\r
+ ASSERT(NULL != ArmProcessorTable);\r
+\r
+ // Set ARM processor table to default values\r
+ CopyMem(ArmProcessorTable,&mArmProcessorTableTemplate,sizeof(ARM_PROCESSOR_TABLE));\r
+\r
+ // Fill in Length fields of ARM processor table\r
+ ArmProcessorTable->Header.Length = sizeof(ARM_PROCESSOR_TABLE);\r
+ ArmProcessorTable->Header.DataLen = GET_GUID_HOB_DATA_SIZE(Hob);\r
+\r
+ // Fill in Identifier(ARM processor table GUID)\r
+ ArmProcessorTable->Header.Identifier = gArmMpCoreInfoGuid;\r
+\r
+ // Set Number of ARM core entries in the Table\r
+ ArmProcessorTable->NumberOfEntries = GET_GUID_HOB_DATA_SIZE(Hob)/sizeof(ARM_CORE_INFO);\r
+\r
+ // Allocate runtime memory for ARM processor Table entries\r
+ ArmProcessorTable->ArmCpus = (ARM_CORE_INFO*)AllocateRuntimePool (\r
+ ArmProcessorTable->NumberOfEntries * sizeof(ARM_CORE_INFO));\r
+\r
+ // Check if the memory allocation is succesful or not\r
+ ASSERT(NULL != ArmProcessorTable->ArmCpus);\r
+\r
+ // Copy ARM Processor Table data from HOB list to newly allocated memory\r
+ CopyMem(ArmProcessorTable->ArmCpus,GET_GUID_HOB_DATA(Hob), ArmProcessorTable->Header.DataLen);\r
+\r
+ // Install the ARM Processor table into EFI system configuration table\r
+ Status = gBS->InstallConfigurationTable (&gArmMpCoreInfoGuid, ArmProcessorTable);\r
+\r
+ ASSERT_EFI_ERROR (Status);\r
+ }\r
+ }\r
+ }\r
+}\r
\r
Copyright (c) 2006, Intel Corporation. All rights reserved.<BR>\r
Copyright (c) 2011 Hewlett Packard Corporation. All rights reserved.<BR>\r
+Copyright (c) 2011, ARM Limited. All rights reserved.<BR>\r
+\r
This program and the accompanying materials \r
are licensed and made available under the terms and conditions of the BSD License \r
which accompanies this distribution. The full text of the license may be found at \r
//\r
// The protocols, PPI and GUID defintions for this module\r
//\r
+#include <Ppi/ArmMpCoreInfo.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/DebugLib.h>\r
#include <Library/PeimEntryPoint.h>\r
+#include <Library/PeiServicesLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/ArmLib.h>\r
{\r
EFI_PEI_HOB_POINTERS NextHob;\r
\r
- // look at the resource descriptor hobs, choose the first system memory one\r
+ // Look at the resource descriptor hobs, choose the first system memory one\r
NextHob.Raw = GetHobList ();\r
while ((NextHob.Raw = GetNextHob (EFI_HOB_TYPE_RESOURCE_DESCRIPTOR, NextHob.Raw)) != NULL) {\r
if(NextHob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY)\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
UINTN Idx;\r
UINT32 CacheAttributes;\r
UINT32 SystemMemoryBase;\r
\r
SystemMemoryLastAddress = SystemMemoryBase + (SystemMemoryLength-1);\r
\r
- // if system memory does not begin at 0\r
+ // If system memory does not begin at 0\r
if(SystemMemoryBase > 0) {\r
MemoryTable[Idx].PhysicalBase = 0;\r
MemoryTable[Idx].VirtualBase = 0;\r
MemoryTable[Idx].Attributes = (ARM_MEMORY_REGION_ATTRIBUTES)CacheAttributes;\r
Idx++;\r
\r
- // if system memory does not go to the last address (0xFFFFFFFF)\r
+ // If system memory does not go to the last address (0xFFFFFFFF)\r
if( SystemMemoryLastAddress < MAX_ADDRESS ) {\r
MemoryTable[Idx].PhysicalBase = SystemMemoryLastAddress + 1;\r
MemoryTable[Idx].VirtualBase = MemoryTable[Idx].PhysicalBase;\r
BuildMemoryAllocationHob((EFI_PHYSICAL_ADDRESS)(UINTN)TranslationTableBase, TranslationTableSize, EfiBootServicesData);\r
}\r
\r
-\r
-EFI_STATUS\r
-EFIAPI\r
-InitializeCpuPeim (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
- )\r
/*++\r
\r
Routine Description:\r
Status - EFI_SUCCESS if the boot mode could be set\r
\r
--*/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeCpuPeim (\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
{\r
+ EFI_STATUS Status;\r
+ ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r
+ UINTN ArmCoreCount;\r
+ ARM_CORE_INFO *ArmCoreInfoTable;\r
+\r
// Enable program flow prediction, if supported.\r
ArmEnableBranchPrediction ();\r
\r
- // publish the CPU memory and io spaces sizes\r
+ // Publish the CPU memory and io spaces sizes\r
BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
\r
- ConfigureMmu();\r
+ //ConfigureMmu();\r
+\r
+ // Only MP Core platform need to produce gArmMpCoreInfoPpiGuid\r
+ Status = PeiServicesLocatePpi (&gArmMpCoreInfoPpiGuid, 0, NULL, (VOID**)&ArmMpCoreInfoPpi);\r
+ if (!EFI_ERROR(Status)) {\r
+ // Build the MP Core Info Table\r
+ ArmCoreCount = 0;\r
+ Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
+ if (!EFI_ERROR(Status) && (ArmCoreCount > 0)) {\r
+ // Build MPCore Info HOB\r
+ BuildGuidDataHob (&gArmMpCoreInfoGuid, ArmCoreInfoTable, sizeof (ARM_CORE_INFO) * ArmCoreCount);\r
+ }\r
+ }\r
\r
return EFI_SUCCESS;\r
}\r
ArmLib\r
\r
[Ppis]\r
+ gArmMpCoreInfoPpiGuid\r
+ \r
+[Guids]\r
+ gArmMpCoreInfoGuid\r
\r
[FixedPcd]\r
gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#ifndef __ARM_MP_CORE_INFO_GUID_H_\r
+#define __ARM_MP_CORE_INFO_GUID_H_\r
+\r
+#define MAX_CPUS_PER_MPCORE_SYSTEM 0x04\r
+#define SCU_CONFIG_REG_OFFSET 0x04\r
+#define MPIDR_U_BIT_MASK 0x40000000\r
+\r
+typedef struct {\r
+ UINT32 ClusterId;\r
+ UINT32 CoreId;\r
+\r
+ // MP Core Mailbox\r
+ EFI_PHYSICAL_ADDRESS MailboxSetAddress;\r
+ EFI_PHYSICAL_ADDRESS MailboxGetAddress;\r
+ EFI_PHYSICAL_ADDRESS MailboxClearAddress;\r
+ UINT64 MailboxClearValue;\r
+} ARM_CORE_INFO;\r
+\r
+typedef struct{\r
+ UINT64 Signature;\r
+ UINT32 Length;\r
+ UINT32 Revision;\r
+ UINT64 OemId;\r
+ UINT64 OemTableId;\r
+ UINTN OemRevision;\r
+ UINTN CreatorId;\r
+ UINTN CreatorRevision;\r
+ EFI_GUID Identifier;\r
+ UINTN DataLen;\r
+} ARM_PROCESSOR_TABLE_HEADER;\r
+\r
+typedef struct {\r
+ ARM_PROCESSOR_TABLE_HEADER Header;\r
+ UINTN NumberOfEntries;\r
+ ARM_CORE_INFO *ArmCpus;\r
+} ARM_PROCESSOR_TABLE;\r
+\r
+\r
+#define ARM_MP_CORE_INFO_GUID \\r
+ { 0xa4ee0728, 0xe5d7, 0x4ac5, {0xb2, 0x1e, 0x65, 0x8e, 0xd8, 0x57, 0xe8, 0x34} }\r
+\r
+#define EFI_ARM_PROCESSOR_TABLE_SIGNATURE SIGNATURE_64 ('C', 'P', 'U', 'T', 'A', 'B', 'L', 'E')\r
+#define EFI_ARM_PROCESSOR_TABLE_REVISION 0x00010000 //1.0\r
+#define EFI_ARM_PROCESSOR_TABLE_OEM_ID SIGNATURE_64('A','R','M',' ', 'L', 't', 'd', ' ')\r
+#define EFI_ARM_PROCESSOR_TABLE_OEM_TABLE_ID SIGNATURE_64('V', 'E', 'R', 'S', 'A', 'T', 'I', 'L')\r
+#define EFI_ARM_PROCESSOR_TABLE_OEM_REVISION 0x00000001\r
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_ID 0xA5A5A5A5\r
+#define EFI_ARM_PROCESSOR_TABLE_CREATOR_REVISION 0x01000001\r
+\r
+extern EFI_GUID gArmMpCoreInfoGuid;\r
+\r
+#endif /* MPCOREINFO_H_ */\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __ARM_MP_CORE_INFO_PPI_H__\r
+#define __ARM_MP_CORE_INFO_PPI_H_\r
+\r
+#include <Guid/ArmMpCoreInfo.h>\r
+\r
+#define ARM_MP_CORE_INFO_PPI_GUID \\r
+ { 0x6847cc74, 0xe9ec, 0x4f8f, {0xa2, 0x9d, 0xab, 0x44, 0xe7, 0x54, 0xa8, 0xfc} }\r
+\r
+/**\r
+ This service of the EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI that migrates temporary RAM into\r
+ permanent memory.\r
+\r
+ @param PeiServices Pointer to the PEI Services Table.\r
+ @param TemporaryMemoryBase Source Address in temporary memory from which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param PermanentMemoryBase Destination Address in permanent memory into which the SEC or PEIM will copy the\r
+ Temporary RAM contents.\r
+ @param CopySize Amount of memory to migrate from temporary to permanent memory.\r
+\r
+ @retval EFI_SUCCESS The data was successfully returned.\r
+ @retval EFI_INVALID_PARAMETER PermanentMemoryBase + CopySize > TemporaryMemoryBase when\r
+ TemporaryMemoryBase > PermanentMemoryBase.\r
+\r
+**/\r
+typedef\r
+EFI_STATUS\r
+(EFIAPI * ARM_MP_CORE_INFO_GET) (\r
+ OUT UINTN *ArmCoreCount,\r
+ OUT ARM_CORE_INFO **ArmCoreTable\r
+);\r
+\r
+///\r
+/// This service abstracts the ability to migrate contents of the platform early memory store.\r
+/// Note: The name EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI is different from the current PI 1.2 spec.\r
+/// This PPI was optional.\r
+///\r
+typedef struct {\r
+ ARM_MP_CORE_INFO_GET GetMpCoreInfo;\r
+} ARM_MP_CORE_INFO_PPI;\r
+\r
+extern EFI_GUID gArmMpCoreInfoPpiGuid;\r
+extern EFI_GUID gArmMpCoreInfoGuid;\r
+\r
+#endif\r
}\r
ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
+ ArmPkg/Drivers/CpuPei/CpuPei.inf\r
IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
Nt32Pkg/BootModePei/BootModePei.inf\r
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
}\r
ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
+ ArmPkg/Drivers/CpuPei/CpuPei.inf\r
IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
Nt32Pkg/BootModePei/BootModePei.inf\r
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
INF MdeModulePkg/Core/Pei/PeiMain.inf
INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
INF MdeModulePkg/Core/Pei/PeiMain.inf\r
INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf\r
INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf\r
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf\r
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf\r
// L2x0 Cache Controller Base Address\r
//#define ARM_EB_L2x0_CTLR_BASE 0x1E00A000*/\r
\r
+#define ARM_EB_SYS_PROC_ID_MASK (0xFF << 24)\r
+#define ARM_EB_SYS_PROC_ID_CORTEX_A8 (0x0E << 24)\r
+#define ARM_EB_SYS_PROC_ID_CORTEX_A9 (0x0C << 24)\r
\r
/*******************************************\r
// EFI Memory Map in Permanent Memory (DRAM)\r
#include <Drivers/PL341Dmc.h>
#include <Drivers/SP804Timer.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
#include <ArmPlatform.h>
+ARM_CORE_INFO mRealViewEbMpCoreInfoTable[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 1
+ 0x0, 0x1,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_EB_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
/**
Return if Trustzone is supported by your platform
{
// We do not need to initialize the System Memory on RTSM
}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ if ((MmioRead32 (ARM_EB_SYS_PROCID0_REG) & ARM_EB_SYS_PROC_ID_MASK) == ARM_EB_SYS_PROC_ID_CORTEX_A9) {
+ *CoreCount = sizeof(mRealViewEbMpCoreInfoTable) / sizeof(ARM_CORE_INFO);
+ *ArmCoreTable = mRealViewEbMpCoreInfoTable;
+ return EFI_SUCCESS;
+ } else {
+ return EFI_UNSUPPORTED;
+ }
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &mArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
- *PpiListSize = 0;
- *PpiList = NULL;
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
}
}
ArmPlatformPkg/PlatformPei/PlatformPeim.inf
ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ ArmPkg/Drivers/CpuPei/CpuPei.inf
IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
Nt32Pkg/BootModePei/BootModePei.inf
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
INF MdeModulePkg/Core/Pei/PeiMain.inf
INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
INF ArmPlatformPkg/MemoryInitPei/MemoryInitPeim.inf
+ INF ArmPkg/Drivers/CpuPei/CpuPei.inf
INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
// VRAM offset for the PL111 Colour LCD Controller on the motherboard\r
#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)\r
\r
-#define SYS_PROC_ID_UNSUPPORTED 0xFF\r
-#define SYS_PROC_ID_CORTEX_A9 0x0C\r
+#define ARM_VE_SYS_PROC_ID_MASK (0xFF << 24)\r
+#define ARM_VE_SYS_PROC_ID_UNSUPPORTED (0xFF << 24)\r
+#define ARM_VE_SYS_PROC_ID_CORTEX_A9 (0x0C << 24)\r
+#define ARM_VE_SYS_PROC_ID_CORTEX_A5 (0x12 << 24)\r
+#define ARM_VE_SYS_PROC_ID_CORTEX_A15 (0x14 << 24)\r
\r
//\r
// Sites where the peripheral is fitted\r
#include <Drivers/PL301Axi.h>
#include <Drivers/SP804Timer.h>
+#include <Ppi/ArmMpCoreInfo.h>
+
#include <ArmPlatform.h>
#define SerialPrint(txt) SerialPortWrite ((UINT8*)(txt), AsciiStrLen(txt)+1);
+ARM_CORE_INFO mVersatileExpressMpCoreInfoCTA9x4[] = {
+ {
+ // Cluster 0, Core 0
+ 0x0, 0x0,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 1
+ 0x0, 0x1,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 2
+ 0x0, 0x2,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ },
+ {
+ // Cluster 0, Core 3
+ 0x0, 0x3,
+
+ // MP Core MailBox Set/Get/Clear Addresses and Clear Value
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_SET_REG,
+ (EFI_PHYSICAL_ADDRESS)ARM_VE_SYS_FLAGS_CLR_REG,
+ (UINT64)0xFFFFFFFF
+ }
+};
+
// DDR2 timings
PL341_DMC_CONFIG DDRTimings = {
.MaxChip = 1,
PL341DmcInit(ARM_VE_DMC_BASE, &DDRTimings);
PL301AxiInit(ARM_VE_FAXI_BASE);
}
+
+EFI_STATUS
+PrePeiCoreGetMpCoreInfo (
+ OUT UINTN *CoreCount,
+ OUT ARM_CORE_INFO **ArmCoreTable
+ )
+{
+ *CoreCount = sizeof(mVersatileExpressMpCoreInfoCTA9x4) / sizeof(ARM_CORE_INFO);
+ *ArmCoreTable = mVersatileExpressMpCoreInfoCTA9x4;
+
+ return EFI_SUCCESS;
+}
+
+// Needs to be declared in the file. Otherwise gArmMpCoreInfoPpiGuid is undefined in the contect of PrePeiCore
+EFI_GUID mArmMpCoreInfoPpiGuid = ARM_MP_CORE_INFO_PPI_GUID;
+ARM_MP_CORE_INFO_PPI mMpCoreInfoPpi = { PrePeiCoreGetMpCoreInfo };
+
+EFI_PEI_PPI_DESCRIPTOR gPlatformPpiTable[] = {
+ {
+ EFI_PEI_PPI_DESCRIPTOR_PPI,
+ &mArmMpCoreInfoPpiGuid,
+ &mMpCoreInfoPpi
+ }
+};
+
VOID
ArmPlatformGetPlatformPpiList (
OUT UINTN *PpiListSize,
OUT EFI_PEI_PPI_DESCRIPTOR **PpiList
)
{
- *PpiListSize = 0;
- *PpiList = NULL;
+ *PpiListSize = sizeof(gPlatformPpiTable);
+ *PpiList = gPlatformPpiTable;
}
// Initialize the platform specific controllers\r
ArmPlatformNormalInitialize ();\r
\r
- BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
-\r
BuildFvHob (PcdGet32(PcdFvBaseAddress), PcdGet32(PcdFvSize));\r
\r
return EFI_SUCCESS;\r
**/\r
\r
#include <Library/ArmGicLib.h>\r
-#include <Library/ArmMPCoreMailBoxLib.h>\r
+\r
+#include <Ppi/ArmMpCoreInfo.h>\r
+\r
#include <Chipset/ArmV7.h>\r
\r
#include "PrePeiCore.h"\r
IN UINTN MpId\r
)\r
{\r
- // Function pointer to Secondary Core entry point\r
- VOID (*secondary_start)(VOID);\r
- UINTN secondary_entry_addr=0;\r
+ EFI_STATUS Status;\r
+ UINTN PpiListSize;\r
+ UINTN PpiListCount;\r
+ EFI_PEI_PPI_DESCRIPTOR *PpiList;\r
+ ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r
+ UINTN Index;\r
+ UINTN ArmCoreCount;\r
+ ARM_CORE_INFO *ArmCoreInfoTable;\r
+ UINT32 ClusterId;\r
+ UINT32 CoreId;\r
+ VOID (*SecondaryStart)(VOID);\r
+ UINTN SecondaryEntryAddr;\r
+\r
+ ClusterId = GET_CLUSTER_ID(MpId);\r
+ CoreId = GET_CORE_ID(MpId);\r
+\r
+ // Get the gArmMpCoreInfoPpiGuid\r
+ PpiListSize = 0;\r
+ ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
+ PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
+ for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
+ if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ // On MP Core Platform we must implement the ARM MP Core Info PPI\r
+ ASSERT (Index != PpiListCount);\r
+\r
+ ArmMpCoreInfoPpi = PpiList->Ppi;\r
+ ArmCoreCount = 0;\r
+ Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ // Find the core in the ArmCoreTable\r
+ for (Index = 0; Index < ArmCoreCount; Index++) {\r
+ if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ // The ARM Core Info Table must define every core\r
+ ASSERT (Index != ArmCoreCount);\r
\r
// Clear Secondary cores MailBox\r
- ArmClearMPCoreMailbox();\r
+ MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
\r
- while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
- ArmCallWFI();\r
+ SecondaryEntryAddr = 0;\r
+ while (SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress), SecondaryEntryAddr == 0) {\r
+ ArmCallWFI ();\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);\r
}\r
\r
- secondary_start = (VOID (*)())secondary_entry_addr;\r
-\r
// Jump to secondary core entry point.\r
- secondary_start();\r
+ SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
+ SecondaryStart();\r
\r
// The secondaries shouldn't reach here\r
ASSERT(FALSE);\r
[Ppis]\r
gEfiTemporaryRamSupportPpiGuid\r
gArmGlobalVariablePpiGuid\r
+ gArmMpCoreInfoPpiGuid\r
\r
[FeaturePcd]\r
gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores\r
// Declare the Global Variable HOB\r
BuildGlobalVariableHob (GlobalVariableBase, FixedPcdGet32 (PcdPeiGlobalVariableSize));\r
\r
+ //TODO: Call CpuPei as a library\r
+ BuildCpuHob (PcdGet8 (PcdPrePiCpuMemorySize), PcdGet8 (PcdPrePiCpuIoSize));\r
+\r
// Set the Boot Mode\r
SetBootMode (ArmPlatformGetBootMode ());\r
\r
projects / mirror_edk2.git / commitdiff