EmbeddedPkg/MmcDxe: Add non-DDR timing mode support
authorJun Nie <jun.nie@linaro.org>
Mon, 12 Jun 2017 02:18:05 +0000 (10:18 +0800)
committerLeif Lindholm <leif.lindholm@linaro.org>
Thu, 29 Jun 2017 15:54:37 +0000 (16:54 +0100)
Only DDR mode is support for 8bit mode currently. Add
non-DDR case when configuring ECSD.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jun Nie <jun.nie@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
EmbeddedPkg/Universal/MmcDxe/MmcIdentification.c

index 574a77e..4ce0ddd 100644 (file)
@@ -254,7 +254,7 @@ InitializeEmmcDevice (
   EFI_MMC_HOST_PROTOCOL *Host;\r
   EFI_STATUS Status = EFI_SUCCESS;\r
   ECSD       *ECSDData;\r
-  UINT32     BusClockFreq, Idx;\r
+  UINT32     BusClockFreq, Idx, BusMode;\r
   UINT32     TimingMode[4] = {EMMCHS52DDR1V2, EMMCHS52DDR1V8, EMMCHS52, EMMCHS26};\r
 \r
   Host  = MmcHostInstance->MmcHost;\r
@@ -286,7 +286,19 @@ InitializeEmmcDevice (
     }\r
     Status = Host->SetIos (Host, BusClockFreq, 8, TimingMode[Idx]);\r
     if (!EFI_ERROR (Status)) {\r
-      Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, EMMC_BUS_WIDTH_DDR_8BIT);\r
+      switch (TimingMode[Idx]) {\r
+      case EMMCHS52DDR1V2:\r
+      case EMMCHS52DDR1V8:\r
+        BusMode = EMMC_BUS_WIDTH_DDR_8BIT;\r
+        break;\r
+      case EMMCHS52:\r
+      case EMMCHS26:\r
+        BusMode = EMMC_BUS_WIDTH_8BIT;\r
+        break;\r
+      default:\r
+        return EFI_UNSUPPORTED;\r
+      }\r
+      Status = EmmcSetEXTCSD (MmcHostInstance, EXTCSD_BUS_WIDTH, BusMode);\r
       if (EFI_ERROR (Status)) {\r
         DEBUG ((DEBUG_ERROR, "InitializeEmmcDevice(): Failed to set EXTCSD bus width, Status:%r\n", Status));\r
       }\r