+++ /dev/null
-Copyright (c) 2011-2013 ARM Limited\r
-All rights reserved.\r
-\r
-Redistribution and use in source and binary forms, with or without\r
-modification, are permitted provided that the following conditions are\r
-met:\r
-\r
- * Redistributions of source code must retain the above copyright\r
- notice, this list of conditions and the following disclaimer.\r
- * Redistributions in binary form must reproduce the above copyright\r
- notice, this list of conditions and the following disclaimer in\r
- the documentation and/or other materials provided with the\r
- distribution.\r
- * Neither the name of ARM nor the names of its contributors may be\r
- used to endorse or promote products derived from this software\r
- without specific prior written permission.\r
-\r
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS\r
-IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\r
-TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
-PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
-HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\r
-TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
-PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
-LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
-NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
+++ /dev/null
-#\r
-# Makefile - build a UEFI boot image for booting from different exception levels.\r
-#\r
-# Copyright (C) 2011-2013 ARM Limited.\r
-# All rights reserved.\r
-#\r
-# Redistribution and use in source and binary forms, with or without\r
-# modification, are permitted provided that the following conditions are\r
-# met:\r
-#\r
-# * Redistributions of source code must retain the above copyright\r
-# notice, this list of conditions and the following disclaimer.\r
-# * Redistributions in binary form must reproduce the above copyright\r
-# notice, this list of conditions and the following disclaimer in\r
-# the documentation and/or other materials provided with the\r
-# distribution.\r
-# * Neither the name of ARM nor the names of its contributors may be\r
-# used to endorse or promote products derived from this software\r
-# without specific prior written permission.\r
-#\r
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS\r
-# IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\r
-# TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
-# PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
-# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\r
-# TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
-# PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
-# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
-# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
-# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
-#\r
-# This license can also be found in the LICENSE.TXT file.\r
-\r
-\r
-# VE\r
-PHYS_OFFSET := 0x80000000\r
-UART_BASE := 0x1c090000\r
-GIC_DIST_BASE := 0x2c001000\r
-GIC_CPU_BASE := 0x2c002000\r
-CNTFRQ := 0x01800000 # 24Mhz\r
-\r
-BOOTLOADER := boot.S\r
-LD_SCRIPT := model.lds.S\r
-IMAGE_1 := uefi-bootstrap-el1.axf\r
-IMAGE_2 := uefi-bootstrap-el2.axf\r
-IMAGE_3 := uefi-bootstrap-el3.axf\r
-IMAGE_3F := uefi-bootstrap-el3-foundation.axf\r
-\r
-\r
-CROSS_COMPILE ?= aarch64-none-elf-\r
-CC := $(CROSS_COMPILE)gcc\r
-LD := $(CROSS_COMPILE)ld\r
-\r
-all: $(IMAGE_1) $(IMAGE_2) $(IMAGE_3) $(IMAGE_3F)\r
-\r
-clean:\r
- rm -f *.axf *.o *.lds\r
-\r
-$(IMAGE_1): boot1.o model1.lds\r
- $(LD) -o $@ --script=model1.lds\r
-\r
-$(IMAGE_2): boot2.o model2.lds\r
- $(LD) -o $@ --script=model2.lds\r
-\r
-$(IMAGE_3): boot3.o model3.lds\r
- $(LD) -o $@ --script=model3.lds\r
-\r
-$(IMAGE_3F): boot3f.o model3f.lds\r
- $(LD) -o $@ --script=model3f.lds\r
-\r
-boot1.o: $(BOOTLOADER) Makefile\r
- $(CC) $(CPPFLAGS) -DUART_BASE=$(UART_BASE) -DCNTFRQ=$(CNTFRQ) -DGIC_DIST_BASE=$(GIC_DIST_BASE) -DGIC_CPU_BASE=$(GIC_CPU_BASE) -DSTART_EL2=1 -DSTART_EL1=1 -c -o $@ $(BOOTLOADER)\r
-\r
-boot2.o: $(BOOTLOADER) Makefile\r
- $(CC) $(CPPFLAGS) -DUART_BASE=$(UART_BASE) -DCNTFRQ=$(CNTFRQ) -DGIC_DIST_BASE=$(GIC_DIST_BASE) -DGIC_CPU_BASE=$(GIC_CPU_BASE) -DSTART_EL2=1 -c -o $@ $(BOOTLOADER)\r
-\r
-boot3.o: $(BOOTLOADER) Makefile\r
- $(CC) $(CPPFLAGS) -DUART_BASE=$(UART_BASE) -DCNTFRQ=$(CNTFRQ) -DGIC_DIST_BASE=$(GIC_DIST_BASE) -DGIC_CPU_BASE=$(GIC_CPU_BASE) -c -o $@ $(BOOTLOADER)\r
-\r
-boot3f.o: $(BOOTLOADER) Makefile\r
- $(CC) $(CPPFLAGS) -DUART_BASE=$(UART_BASE) -DCNTFRQ=$(CNTFRQ) -DGIC_DIST_BASE=$(GIC_DIST_BASE) -DGIC_CPU_BASE=$(GIC_CPU_BASE) -DFOUNDATION_MODEL=1 -c -o $@ $(BOOTLOADER)\r
-\r
-model1.lds: $(LD_SCRIPT) Makefile boot1.o\r
- $(CC) $(CPPFLAGS) -DPHYS_OFFSET=$(PHYS_OFFSET) -DBOOT1 -E -P -C -o $@ $<\r
-\r
-model2.lds: $(LD_SCRIPT) Makefile boot2.o\r
- $(CC) $(CPPFLAGS) -DPHYS_OFFSET=$(PHYS_OFFSET) -DBOOT2 -E -P -C -o $@ $<\r
-\r
-model3.lds: $(LD_SCRIPT) Makefile boot3.o\r
- $(CC) $(CPPFLAGS) -DPHYS_OFFSET=$(PHYS_OFFSET) -DBOOT3 -E -P -C -o $@ $<\r
-\r
-model3f.lds: $(LD_SCRIPT) Makefile boot3f.o\r
- $(CC) $(CPPFLAGS) -DPHYS_OFFSET=$(PHYS_OFFSET) -DBOOT3F -E -P -C -o $@ $<\r
-\r
-.PHONY: all clean\r
+++ /dev/null
-/*\r
- * boot.S - simple register setup code for junping to a second stage bootloader\r
- *\r
- * Copyright (C) 2011-2013 ARM Limited.\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- *\r
- * * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in\r
- * the documentation and/or other materials provided with the\r
- * distribution.\r
- * * Neither the name of ARM nor the names of its contributors may be\r
- * used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS\r
- * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\r
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\r
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * This license can also be found in the LICENSE.TXT file.\r
- */\r
-\r
- .text\r
-\r
- .globl _start\r
-\r
-.set LED_ADDR, 0x1c010008\r
-\r
-_start:\r
- /*\r
- * EL3 initialisation\r
- */\r
-\r
- // Set LED to show progress.\r
- ldr x1, =LED_ADDR\r
- mov w0, #0x1\r
- str w0, [x1]\r
- dsb sy\r
-\r
-#if defined START_EL2\r
-\r
- mrs x0, CurrentEL\r
- cmp x0, #0xc // EL3?\r
- b.ne start_ns // skip EL3 initialisation\r
-\r
- mov x0, #0x30 // RES1\r
- orr x0, x0, #(1 << 0) // Non-secure bit\r
- orr x0, x0, #(1 << 8) // HVC enable\r
- orr x0, x0, #(1 << 10) // 64-bit EL2\r
- msr scr_el3, x0\r
-\r
- msr cptr_el3, xzr // Disable copro. traps to EL3\r
-\r
- ldr x0, =CNTFRQ\r
- msr cntfrq_el0, x0\r
-\r
- /*\r
- * Check for the primary CPU to avoid a race on the distributor\r
- * registers.\r
- */\r
- mrs x0, mpidr_el1\r
- tst x0, #15\r
- b.ne 1f // secondary CPU\r
-\r
- ldr x1, =GIC_DIST_BASE // GICD_CTLR\r
- mov w0, #3 // EnableGrp0 | EnableGrp1\r
- str w0, [x1]\r
-\r
-1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR\r
- mov w0, #~0 // Grp1 interrupts\r
- str w0, [x1], #4\r
- b.ne 2f // Only local interrupts for secondary CPUs\r
- str w0, [x1], #4\r
- str w0, [x1], #4\r
-\r
-2: ldr x1, =GIC_CPU_BASE // GICC_CTLR\r
- ldr w0, [x1]\r
- orr w0, w0, #3 // EnableGrp0 | EnableGrp1\r
- str w0, [x1]\r
-\r
- mov w0, #1 << 7 // allow NS access to GICC_PMR\r
- str w0, [x1, #4] // GICC_PMR\r
-\r
- msr sctlr_el2, xzr\r
-\r
-#if defined START_EL1\r
-\r
- /* Now setup our EL1. Controlled by EL2 config on Model */\r
- mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
- orr x0, x0, #(1 << 31) // Set EL1 to be 64bit\r
-\r
- // Send all interrupts to their respective Exception levels for EL2\r
- bic x0, x0, #(1 << 3) // Disable virtual FIQ\r
- bic x0, x0, #(1 << 4) // Disable virtual IRQ\r
- bic x0, x0, #(1 << 5) // Disable virtual SError and Abort\r
- msr hcr_el2, x0 // Write back our settings\r
-\r
- /*\r
- * Enable architected timer access\r
- */\r
- mrs x0, cnthctl_el2\r
- orr x0, x0, #3 // Enable EL1 access to timers\r
- msr cnthctl_el2, x0\r
-\r
- mrs x0, cntkctl_el1\r
- orr x0, x0, #3 // EL0 access to counters\r
- msr cntkctl_el1, x0\r
-\r
- /* Set ID regs */\r
- mrs x0, midr_el1\r
- mrs x1, mpidr_el1\r
- msr vpidr_el2, x0\r
- msr vmpidr_el2, x1\r
-\r
- /* Coprocessor traps. */\r
- mov x0, #0x33ff\r
- msr cptr_el2, x0 // Disable copro. traps to EL2\r
-\r
- msr hstr_el2, xzr // Disable CP15 traps to EL2\r
-\r
-#endif // START_EL1\r
-\r
- /* Configure UART. Primary CPU only */\r
- mrs x4, mpidr_el1\r
- tst x4, #15\r
- b.ne 1f\r
-\r
- /*\r
- * UART initialisation (38400 8N1)\r
- */\r
- ldr x4, =UART_BASE // UART base\r
- mov w5, #0x10 // ibrd\r
- str w5, [x4, #0x24]\r
- mov w5, #0xc300\r
- orr w5, w5, #0x0001 // cr\r
- str w5, [x4, #0x30]\r
-\r
- /*\r
- * Prepare the switch to the EL2_SP2 mode from EL3\r
- */\r
-1: ldr x0, =start_ns // Return after mode switch\r
-#if defined START_EL1\r
- mov x1, #0x3c5 // EL1_SP1 | D | A | I | F\r
-#else\r
- mov x1, #0x3c9 // EL2_SP2 | D | A | I | F\r
-#endif\r
-\r
- msr elr_el3, x0\r
- msr spsr_el3, x1\r
- eret\r
-\r
-#endif // START_EL2\r
-\r
-\r
-start_ns:\r
-\r
-/*\r
- * We do not have NOR flash on the Foundation model. So run UEFI from RAM.\r
- * On the full model we use the NOR FLASH to store UEFI, so start there.\r
- */\r
-#if defined FOUNDATION_MODEL\r
- mov x0, #0xa0000000\r
-#else\r
- mov x0, #0x0\r
-#endif\r
- br x0\r
-\r
- .ltorg\r
-\r
- .org 0x200\r
+++ /dev/null
-/*\r
- * model.lds.S - simple linker script for stand-alone Linux booting\r
- *\r
- * Copyright (C) 2011, 2012 ARM Limited.\r
- * All rights reserved.\r
- *\r
- * Redistribution and use in source and binary forms, with or without\r
- * modification, are permitted provided that the following conditions are\r
- * met:\r
- *\r
- * * Redistributions of source code must retain the above copyright\r
- * notice, this list of conditions and the following disclaimer.\r
- * * Redistributions in binary form must reproduce the above copyright\r
- * notice, this list of conditions and the following disclaimer in\r
- * the documentation and/or other materials provided with the\r
- * distribution.\r
- * * Neither the name of ARM nor the names of its contributors may be\r
- * used to endorse or promote products derived from this software\r
- * without specific prior written permission.\r
- *\r
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS\r
- * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED\r
- * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A\r
- * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT\r
- * HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,\r
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED\r
- * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR\r
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF\r
- * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING\r
- * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS\r
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.\r
- *\r
- * This license can also be found in the LICENSE.TXT file.\r
- */\r
-\r
-OUTPUT_FORMAT("elf64-littleaarch64")\r
-OUTPUT_ARCH(aarch64)\r
-TARGET(binary)\r
-\r
-#ifdef BOOT1\r
-INPUT(./boot1.o)\r
-#endif\r
-\r
-#ifdef BOOT2\r
-INPUT(./boot2.o)\r
-#endif\r
-\r
-#ifdef BOOT3\r
-INPUT(./boot3.o)\r
-#endif\r
-\r
-#ifdef BOOT3F\r
-INPUT(./boot3f.o)\r
-#endif\r
-\r
-SECTIONS\r
-{\r
- . = PHYS_OFFSET;\r
-#ifdef BOOT1\r
- .text : { boot1.o }\r
-#endif\r
-\r
-#ifdef BOOT2\r
- .text : { boot2.o }\r
-#endif\r
-\r
-#ifdef BOOT3\r
- .text : { boot3.o }\r
-#endif\r
-\r
-#ifdef BOOT3F\r
- .text : { boot3f.o }\r
-#endif\r
-\r
- .data : { *(.data) }\r
- .bss : { *(.bss) }\r
-}\r
+++ /dev/null
-<h1>AArch64 UEFI bootstraps</h1>\r
-\r
-<p>Copyright (c) 2011-2013 ARM Limited. All rights reserved.\r
-See the <code>LICENSE.TXT</code> file for more information.</p>\r
-\r
-<p>Contents:</p>\r
-\r
-<ul>\r
-<li>Introduction</li>\r
-<li>Build</li>\r
-<li>Use on ARMv8 RTSM and FVP models</li>\r
-<li>Use on ARMv8 Foundation model</li>\r
-</ul>\r
-\r
-<h2>Introduction</h2>\r
-\r
-<p>A bootstrap can be used to change the model state, like the Exception\r
-Level (EL), before executing the UEFI binary.</p>\r
-\r
-<p>For the ARMv8 RTSM and FVP models this can be used to show/test the UEFI binary\r
-starting at different exception levels. The ARMv8 models start at EL3 by\r
-default.</p>\r
-\r
-<p>In the case of the Foundation model a bootstrap is required to jump to the\r
-UEFI binary as loaded in RAM. This is required as the Foundation model cannot\r
-load and execute UEFI binaries directly. The Foundation model can only load and\r
-execute ELF binaries.</p>\r
-\r
-<h2>Build</h2>\r
-\r
-<p>Build the bootstraps using a AArch64 GCC cross-compiler. By default the\r
-<code>Makefile</code> is configured to assume a GCC bare-metal toolchain:</p>\r
-\r
-<pre><code>PATH=$PATH:<path/to/baremetal-tools/bin/> make clean\r
-PATH=$PATH:<path/to/baremetal-tools/bin/> make\r
-</code></pre>\r
-\r
-<p>To build the bootstraps with a Linux GCC toolchain use the following\r
-commands:</p>\r
-\r
-<pre><code>PATH=$PATH:<path/to/aarch64-linux-gnu-tools/bin/> make clean\r
-PATH=$PATH:<path/to/aarch64-linux-gnu-tools/bin/> CROSS_COMPILE=<gcc-prefix> make\r
-</code></pre>\r
-\r
-<p>The <code>gcc-prefix</code> depends on the specific toolchain distribution used. It can be\r
-"aarch64-linux-gnu-" for example.</p>\r
-\r
-<p>This will result in four <code>axf</code> files:</p>\r
-\r
-<ul>\r
-<li><p>uefi-bootstrap-el3 : The bootstrap jumps to the UEFI code in FLASH without\r
- changing anything.</p></li>\r
-<li><p>uefi-bootstrap-el2 : Setup EL3 and switch the model to EL2 before jumping to the\r
- UEFI code in FLASH.</p></li>\r
-<li><p>uefi-bootstrap-el1 : Setup EL3 and prepare to run at non-secure EL1. Switch to\r
- non-secure EL1 and run the UEFI code in FLASH.</p></li>\r
-<li><p>uefi-bootstrap-el3-foundation : The bootstrap jumps to the UEFI code in RAM\r
- without changing anything. Only to be used with the\r
- Foundation model. The Foundation model does not have\r
- non-secure memory at address <code>0x0</code> and thus the UEFI image\r
- should be pre-loaded into non-secure RAM at address\r
- <code>0xA0000000</code>.</p></li>\r
-</ul>\r
-\r
-<h2>Use on ARMv8 RTSM and FVP models</h2>\r
-\r
-<p>Add the '-a' option to the model start script and point to the required\r
-bootstrap:</p>\r
-\r
-<pre><code>< ... model start script as described in top-level readme file ... >\r
- -a <path/to/bootstrap-binary-file>\r
-</code></pre>\r
-\r
-<p>NOTE: The Foundation model bootstrap should not be used with these models.</p>\r
-\r
-<h2>Use on ARMv8 Foundation model</h2>\r
-\r
-<p>The Foundation model takes an option for an ELF file to be loaded as well as an\r
-option to load a binary data blob into RAM. This can be used to run UEFI in the\r
-following manner:</p>\r
-\r
-<pre><code><PATH_TO_INSTALLED_FOUNDATION_MODEL>/Foundation_v8 --cores=2 --visualization\r
- --image=uefi-bootstrap-el3-foundation.axf --nsdata=RTSM_VE_FOUNDATIONV8_EFI.fd@0xA0000000\r
-</code></pre>\r
-\r
-<p>NOTE: The RTSM version of the bootstraps and UEFI image will not work as\r
- expected on the Foundation model. Foundation model specific versions\r
- should be used.</p>\r
+++ /dev/null
-AArch64 UEFI bootstraps\r
-=======================\r
-\r
-Copyright (c) 2011-2013 ARM Limited. All rights reserved.\r
-See the `LICENSE.TXT` file for more information.\r
-\r
-Contents:\r
-\r
-* Introduction\r
-* Build\r
-* Use on ARMv8 RTSM and FVP models\r
-* Use on ARMv8 Foundation model\r
-\r
-\r
-Introduction\r
-------------\r
-\r
-A bootstrap can be used to change the model state, like the Exception\r
-Level (EL), before executing the UEFI binary.\r
-\r
-For the ARMv8 RTSM and FVP models this can be used to show/test the UEFI binary\r
-starting at different exception levels. The ARMv8 models start at EL3 by\r
-default.\r
-\r
-In the case of the Foundation model a bootstrap is required to jump to the\r
-UEFI binary as loaded in RAM. This is required as the Foundation model cannot\r
-load and execute UEFI binaries directly. The Foundation model can only load and\r
-execute ELF binaries.\r
-\r
-\r
-Build\r
------\r
-\r
-Build the bootstraps using a AArch64 GCC cross-compiler. By default the\r
-`Makefile` is configured to assume a GCC bare-metal toolchain:\r
-\r
- PATH=$PATH:<path/to/baremetal-tools/bin/> make clean\r
- PATH=$PATH:<path/to/baremetal-tools/bin/> make\r
-\r
-To build the bootstraps with a Linux GCC toolchain use the following\r
-commands:\r
-\r
- PATH=$PATH:<path/to/aarch64-linux-gnu-tools/bin/> make clean\r
- PATH=$PATH:<path/to/aarch64-linux-gnu-tools/bin/> CROSS_COMPILE=<gcc-prefix> make\r
-\r
-The `gcc-prefix` depends on the specific toolchain distribution used. It can be\r
-"aarch64-linux-gnu-" for example.\r
-\r
-This will result in four `axf` files:\r
-\r
-* uefi-bootstrap-el3 : The bootstrap jumps to the UEFI code in FLASH without\r
- changing anything.\r
-\r
-* uefi-bootstrap-el2 : Setup EL3 and switch the model to EL2 before jumping to the\r
- UEFI code in FLASH.\r
-\r
-* uefi-bootstrap-el1 : Setup EL3 and prepare to run at non-secure EL1. Switch to\r
- non-secure EL1 and run the UEFI code in FLASH.\r
-\r
-* uefi-bootstrap-el3-foundation : The bootstrap jumps to the UEFI code in RAM\r
- without changing anything. Only to be used with the\r
- Foundation model. The Foundation model does not have\r
- non-secure memory at address `0x0` and thus the UEFI image\r
- should be pre-loaded into non-secure RAM at address\r
- `0xA0000000`.\r
-\r
-\r
-Use on ARMv8 RTSM and FVP models\r
---------------------------------\r
-\r
-Add the '-a' option to the model start script and point to the required\r
-bootstrap:\r
-\r
- < ... model start script as described in top-level readme file ... >\r
- -a <path/to/bootstrap-binary-file>\r
-\r
-NOTE: The Foundation model bootstrap should not be used with these models.\r
-\r
-\r
-Use on ARMv8 Foundation model\r
------------------------------\r
-\r
-The Foundation model takes an option for an ELF file to be loaded as well as an\r
-option to load a binary data blob into RAM. This can be used to run UEFI in the\r
-following manner:\r
-\r
- <PATH_TO_INSTALLED_FOUNDATION_MODEL>/Foundation_v8 --cores=2 --visualization\r
- --image=uefi-bootstrap-el3-foundation.axf --nsdata=RTSM_VE_FOUNDATIONV8_EFI.fd@0xA0000000\r
-\r
-NOTE: The RTSM version of the bootstraps and UEFI image will not work as\r
- expected on the Foundation model. Foundation model specific versions\r
- should be used.\r
projects / mirror_edk2.git / commitdiff