// [PcdPciExpressBaseAddress, 4GB) range require a very small number of\r
// variable MTRRs (preferably 1 or 2).\r
//\r
- ASSERT (FixedPcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);\r
- PlatformInfoHob->Uc32Base = (UINT32)FixedPcdGet64 (PcdPciExpressBaseAddress);\r
+ ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);\r
+ PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress);\r
return;\r
}\r
\r
// The MMCONFIG area is expected to fall between the top of low RAM and\r
// the base of the 32-bit PCI host aperture.\r
//\r
- PciExBarBase = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
+ PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress);\r
ASSERT (TopOfLowRam <= PciExBarBase);\r
ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
// determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r
// for DXE's page tables to cover the MMCONFIG area.\r
//\r
- PciExBarBase.Uint64 = FixedPcdGet64 (PcdPciExpressBaseAddress);\r
+ PciExBarBase.Uint64 = PcdGet64 (PcdPciExpressBaseAddress);\r
ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r
ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r
\r
[LibraryClasses.X64]\r
TdxLib\r
\r
-[FixedPcd]\r
+[Pcd]\r
gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
+\r
+[FixedPcd]\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaBase\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfWorkAreaSize\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase\r
gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtr\r
gUefiOvmfPkgTokenSpaceGuid.PcdXenPvhStartOfDayStructPtrSize\r
gEfiMdePkgTokenSpaceGuid.PcdGuidedExtractHandlerTableAddress\r
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
gEfiMdeModulePkgTokenSpaceGuid.PcdEmuVariableNvStoreReserved\r
[FixedPcd]\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidBase\r
gUefiOvmfPkgTokenSpaceGuid.PcdOvmfCpuidSize\r
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress\r
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIMemoryNVS\r
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiACPIReclaimMemory\r
gEmbeddedTokenSpaceGuid.PcdMemoryTypeEfiReservedMemoryType\r