UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h: Add new MSR.

Changes includes:
  1. Add new MSR: MSR_SILVERMONT_PLATFORM_INFO

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Eric Dong <eric.dong@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>

diff --git a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
index 03bbd0af7c882b1a790c18ebb4ed679d86162789..c3d0f8c208bab8fccd2c933d6de60ab850543388 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/SilvermontMsr.h
@@ -375,6 +375,54 @@ typedef union {
 } MSR_SILVERMONT_FSB_FREQ_REGISTER;\r
 \r
 \r
+/**\r
+  Package. Platform Information: Contains power management and other model\r
+  specific features enumeration. See http://biosbits.org.\r
+\r
+  @param  ECX  MSR_SILVERMONT_PLATFORM_INFO (0x000000CE)\r
+  @param  EAX  Lower 32-bits of MSR value.\r
+               Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.\r
+  @param  EDX  Upper 32-bits of MSR value.\r
+               Described by the type MSR_SILVERMONT_PLATFORM_INFO_REGISTER.\r
+\r
+  <b>Example usage</b>\r
+  @code\r
+  MSR_SILVERMONT_PLATFORM_INFO_REGISTER  Msr;\r
+\r
+  Msr.Uint64 = AsmReadMsr64 (MSR_SILVERMONT_PLATFORM_INFO);\r
+  AsmWriteMsr64 (MSR_SILVERMONT_PLATFORM_INFO, Msr.Uint64);\r
+  @endcode\r
+**/\r
+#define MSR_SILVERMONT_PLATFORM_INFO             0x000000CE\r
+\r
+/**\r
+  MSR information returned for MSR index #MSR_SILVERMONT_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+  ///\r
+  /// Individual bit fields\r
+  ///\r
+  struct {\r
+    UINT32  Reserved1:8;\r
+    ///\r
+    /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) This is the ratio\r
+    /// of the maximum frequency that does not require turbo. Frequency =\r
+    /// ratio * Scalable Bus Frequency.\r
+    ///\r
+    UINT32  MaximumNon_TurboRatio:8;\r
+    UINT32  Reserved2:16;\r
+    UINT32  Reserved3:32;\r
+  } Bits;\r
+  ///\r
+  /// All bit fields as a 32-bit value\r
+  ///\r
+  UINT32  Uint32;\r
+  ///\r
+  /// All bit fields as a 64-bit value\r
+  ///\r
+  UINT64  Uint64;\r
+} MSR_SILVERMONT_PLATFORM_INFO_REGISTER;\r
+\r
 /**\r
   Module. C-State Configuration Control (R/W)  Note: C-state values are\r
   processor specific C-state code names, unrelated to MWAIT extension C-state\r