--- /dev/null
+#/** @file\r
+# Component description file for PlatformAcpiTables module.\r
+#\r
+# ACPI table data and ASL sources required to boot the platform.\r
+#\r
+# Copyright (c) 2008, Intel Corporation. <BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformAcpiTables\r
+ FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+ Platform.h\r
+ Madt.aslc\r
+ Facp.aslc\r
+ Facs.aslc\r
+ Dsdt.asl\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
--- /dev/null
+/** @file\r
+ Contains root level name space objects for the platform\r
+ \r
+ Copyright (c) 2008, Intel Corporation<BR> All rights\r
+ reserved. This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/ \r
+\r
+DefinitionBlock ("Dsdt.aml", "DSDT", 1, "INTEL ", "OVMF ", 3) {\r
+ //\r
+ // System Sleep States\r
+ //\r
+ Name (\_S0, Package () {5, 0, 0, 0})\r
+ Name (\_S4, Package () {1, 0, 0, 0})\r
+ Name (\_S5, Package () {0, 0, 0, 0})\r
+\r
+ //\r
+ // System Bus\r
+ //\r
+ Scope (\_SB) {\r
+ //\r
+ // PCI Root Bridge\r
+ //\r
+ Device (PCI0) {\r
+ Name (_HID, EISAID ("PNP0A03"))\r
+ Name (_ADR, 0x00000000)\r
+ Name (_BBN, 0x00)\r
+ Name (_UID, 0x00)\r
+\r
+ //\r
+ // BUS, I/O, and MMIO resources\r
+ //\r
+ Name (_CRS, ResourceTemplate () {\r
+ WORDBusNumber ( // Bus number resource (0); the bridge produces bus numbers for its subsequent buses\r
+ ResourceProducer, // bit 0 of general flags is 1\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode, // PosDecode\r
+ 0x0000, // Granularity\r
+ 0x0000, // Min\r
+ 0x00FF, // Max\r
+ 0x0000, // Translation\r
+ 0x0100 // Range Length = Max-Min+1\r
+ )\r
+\r
+ IO (Decode16, 0xCF8, 0xCF8, 0x01, 0x08) //Consumed resource (0xCF8-0xCFF)\r
+\r
+ WORDIO ( // Consumed-and-produced resource (all I/O below CF8)\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode, \r
+ EntireRange,\r
+ 0x0000, // Granularity\r
+ 0x0000, // Min\r
+ 0x0CF7, // Max\r
+ 0x0000, // Translation\r
+ 0x0CF8 // Range Length\r
+ )\r
+\r
+ WORDIO ( // Consumed-and-produced resource (all I/O above CFF)\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is fixed\r
+ PosDecode, \r
+ EntireRange,\r
+ 0x0000, // Granularity\r
+ 0x0D00, // Min\r
+ 0xFFFF, // Max\r
+ 0x0000, // Translation\r
+ 0xF300 // Range Length\r
+ )\r
+\r
+ DWORDMEMORY ( // Descriptor for legacy VGA video RAM\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is Fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0x000A0000, // Min\r
+ 0x000BFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x00020000 // Range Length\r
+ )\r
+\r
+ DWORDMEMORY ( // Descriptor for linear frame buffer video RAM\r
+ ResourceProducer, // bit 0 of general flags is 0\r
+ PosDecode,\r
+ MinFixed, // Range is fixed\r
+ MaxFixed, // Range is Fixed\r
+ Cacheable,\r
+ ReadWrite,\r
+ 0x00000000, // Granularity\r
+ 0xF8000000, // Min\r
+ 0xFFFBFFFF, // Max\r
+ 0x00000000, // Translation\r
+ 0x07FC0000 // Range Length\r
+ )\r
+ })\r
+\r
+ //\r
+ // PCI Interrupt Routing Table - PIC Mode Only\r
+ //\r
+ Method (_PRT, 0, NotSerialized) {\r
+ Return (\r
+ Package () {\r
+ //\r
+ // Bus 0, Device 1\r
+ //\r
+ Package () {0x0001FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0001FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x0001FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x0001FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ //\r
+ // Bus 0, Device 3\r
+ //\r
+ Package () {0x0003FFFF, 0x00, \_SB.PCI0.LPC.LNKA, 0x00},\r
+ Package () {0x0003FFFF, 0x01, \_SB.PCI0.LPC.LNKB, 0x00},\r
+ Package () {0x0003FFFF, 0x02, \_SB.PCI0.LPC.LNKC, 0x00},\r
+ Package () {0x0003FFFF, 0x03, \_SB.PCI0.LPC.LNKD, 0x00},\r
+ }\r
+ )\r
+ }\r
+\r
+ //\r
+ // PCI to ISA Bridge (Bus 0, Device 1, Function 0)\r
+ //\r
+ Device (LPC) {\r
+ Name (_ADR, 0x00010000)\r
+\r
+ //\r
+ // PCI Interrupt Routing Configuration Registers\r
+ //\r
+ OperationRegion (PRR0, PCI_Config, 0x60, 0x04)\r
+ Field (PRR0, ANYACC, NOLOCK, PRESERVE) {\r
+ PIRA, 8,\r
+ PIRB, 8,\r
+ PIRC, 8,\r
+ PIRD, 8\r
+ }\r
+\r
+ //\r
+ // _STA method for LNKA, LNKB, LNKC, LNKD\r
+ //\r
+ Method (PSTA, 1, NotSerialized) {\r
+ If (And (Arg0, 0x80)) {\r
+ Return (0x9)\r
+ } Else {\r
+ Return (0xB)\r
+ }\r
+ }\r
+\r
+ //\r
+ // _DIS method for LNKA, LNKB, LNKC, LNKD\r
+ //\r
+ Method (PDIS, 1, NotSerialized) {\r
+ Or (Arg0, 0x80, Arg0)\r
+ }\r
+\r
+ //\r
+ // _CRS method for LNKA, LNKB, LNKC, LNKD\r
+ //\r
+ Method (PCRS, 1, NotSerialized) {\r
+ Name (BUF0, ResourceTemplate () {IRQ (Level, ActiveLow, Shared){0}})\r
+ //\r
+ // Define references to buffer elements\r
+ //\r
+ CreateWordField (BUF0, 0x01, IRQW) // IRQ low\r
+ //\r
+ // Write current settings into IRQ descriptor\r
+ //\r
+ If (And (Arg0, 0x80)) {\r
+ Store (Zero, Local0)\r
+ } Else {\r
+ Store (One, Local0)\r
+ }\r
+ //\r
+ // Shift 1 by value in register 70\r
+ //\r
+ ShiftLeft (Local0, And (Arg0, 0x0F), IRQW) // Save in buffer\r
+ Return (BUF0) // Return Buf0 \r
+ }\r
+\r
+ //\r
+ // _PRS resource for LNKA, LNKB, LNKC, LNKD\r
+ //\r
+ Name (PPRS, ResourceTemplate () {\r
+ IRQ (Level, ActiveLow, Shared) {3, 4, 5, 7, 9, 10, 11, 12, 14, 15}\r
+ })\r
+\r
+ //\r
+ // _SRS method for LNKA, LNKB, LNKC, LNKD\r
+ //\r
+ Method (PSRS, 2, NotSerialized) {\r
+ CreateWordField (Arg1, 0x01, IRQW) // IRQ low\r
+ FindSetRightBit (IRQW, Local0) // Set IRQ\r
+ If (LNotEqual (IRQW, Zero)) {\r
+ And (Local0, 0x7F, Local0)\r
+ Decrement (Local0)\r
+ } Else {\r
+ Or (Local0, 0x80, Local0)\r
+ }\r
+ Store (Local0, Arg0)\r
+ }\r
+\r
+ //\r
+ // PCI IRQ Link A\r
+ //\r
+ Device (LNKA) {\r
+ Name (_HID, EISAID("PNP0C0F"))\r
+ Name (_UID, 1)\r
+\r
+ Method (_STA, 0, NotSerialized) { Return (PSTA (PIRA)) }\r
+ Method (_DIS, 0, NotSerialized) { PDIS (PIRA) }\r
+ Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRA)) }\r
+ Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
+ Method (_SRS, 1, NotSerialized) { PSRS (PIRA, Arg0) } \r
+ }\r
+\r
+ //\r
+ // PCI IRQ Link B\r
+ //\r
+ Device (LNKB) {\r
+ Name (_HID, EISAID("PNP0C0F"))\r
+ Name (_UID, 2)\r
+\r
+ Method (_STA, 0, NotSerialized) { Return (PSTA (PIRB)) }\r
+ Method (_DIS, 0, NotSerialized) { PDIS (PIRB) }\r
+ Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRB)) }\r
+ Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
+ Method (_SRS, 1, NotSerialized) { PSRS (PIRB, Arg0) } \r
+ }\r
+\r
+ //\r
+ // PCI IRQ Link C\r
+ //\r
+ Device (LNKC) {\r
+ Name (_HID, EISAID("PNP0C0F"))\r
+ Name (_UID, 3)\r
+\r
+ Method (_STA, 0, NotSerialized) { Return (PSTA (PIRC)) }\r
+ Method (_DIS, 0, NotSerialized) { PDIS (PIRC) }\r
+ Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRC)) }\r
+ Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
+ Method (_SRS, 1, NotSerialized) { PSRS (PIRC, Arg0) } \r
+ }\r
+\r
+ //\r
+ // PCI IRQ Link D\r
+ //\r
+ Device (LNKD) {\r
+ Name (_HID, EISAID("PNP0C0F"))\r
+ Name (_UID, 1)\r
+\r
+ Method (_STA, 0, NotSerialized) { Return (PSTA (PIRD)) }\r
+ Method (_DIS, 0, NotSerialized) { PDIS (PIRD) }\r
+ Method (_CRS, 0, NotSerialized) { Return (PCRS (PIRD)) }\r
+ Method (_PRS, 0, NotSerialized) { Return (PPRS) }\r
+ Method (_SRS, 1, NotSerialized) { PSRS (PIRD, Arg0) } \r
+ }\r
+ \r
+ //\r
+ // Programmable Interrupt Controller (PIC)\r
+ //\r
+ Device(PIC) {\r
+ Name (_HID, EISAID ("PNP0000"))\r
+ Name (_CRS, ResourceTemplate () {\r
+ IO (Decode16, 0x020, 0x020, 0x00, 0x02)\r
+ IO (Decode16, 0x0A0, 0x0A0, 0x00, 0x02)\r
+ IO (Decode16, 0x4D0, 0x4D0, 0x00, 0x02)\r
+ IRQNoFlags () {2}\r
+ })\r
+ }\r
+\r
+ //\r
+ // ISA DMA \r
+ //\r
+ Device (DMAC) {\r
+ Name (_HID, EISAID ("PNP0200")) \r
+ Name (_CRS, ResourceTemplate () {\r
+ IO (Decode16, 0x00, 0x00, 0, 0x10)\r
+ IO (Decode16, 0x81, 0x81, 0, 0x03)\r
+ IO (Decode16, 0x87, 0x87, 0, 0x01)\r
+ IO (Decode16, 0x89, 0x89, 0, 0x03)\r
+ IO (Decode16, 0x8f, 0x8f, 0, 0x01)\r
+ IO (Decode16, 0xc0, 0xc0, 0, 0x20)\r
+ DMA (Compatibility, NotBusMaster, Transfer8) {4}\r
+ })\r
+ }\r
+\r
+ //\r
+ // 8254 Timer\r
+ //\r
+ Device(TMR) {\r
+ Name(_HID,EISAID("PNP0100"))\r
+ Name(_CRS, ResourceTemplate () {\r
+ IO (Decode16, 0x40, 0x40, 0x00, 0x04)\r
+ IRQNoFlags () {0}\r
+ })\r
+ }\r
+\r
+ //\r
+ // Real Time Clock\r
+ //\r
+ Device (RTC) {\r
+ Name (_HID, EISAID ("PNP0B00"))\r
+ Name (_CRS, ResourceTemplate () {\r
+ IO (Decode16, 0x70, 0x70, 0x00, 0x02)\r
+ IRQNoFlags () {8}\r
+ })\r
+ }\r
+\r
+ //\r
+ // PCAT Speaker\r
+ //\r
+ Device(SPKR) {\r
+ Name (_HID, EISAID("PNP0800"))\r
+ Name (_CRS, ResourceTemplate () {\r
+ IO (Decode16, 0x61, 0x61, 0x01, 0x01)\r
+ })\r
+ }\r
+\r
+ //\r
+ // Floating Point Coprocessor\r
+ //\r
+ Device(FPU) {\r
+ Name (_HID, EISAID("PNP0C04"))\r
+ Name (_CRS, ResourceTemplate () {\r
+ IO (Decode16, 0xF0, 0xF0, 0x00, 0x10)\r
+ IRQNoFlags () {13}\r
+ })\r
+ }\r
+\r
+ //\r
+ // Generic motherboard devices and pieces that don't fit anywhere else\r
+ //\r
+ Device(XTRA) {\r
+ Name (_HID, EISAID ("PNP0C02"))\r
+ Name (_UID, 0x01)\r
+ Name (_CRS, ResourceTemplate () {\r
+ IO (Decode16, 0x010, 0x010, 0x00, 0x10)\r
+ IO (Decode16, 0x022, 0x022, 0x00, 0x1E)\r
+ IO (Decode16, 0x044, 0x044, 0x00, 0x1C)\r
+ IO (Decode16, 0x062, 0x062, 0x00, 0x02)\r
+ IO (Decode16, 0x065, 0x065, 0x00, 0x0B)\r
+ IO (Decode16, 0x072, 0x072, 0x00, 0x0E)\r
+ IO (Decode16, 0x080, 0x080, 0x00, 0x01)\r
+ IO (Decode16, 0x084, 0x084, 0x00, 0x03)\r
+ IO (Decode16, 0x088, 0x088, 0x00, 0x01)\r
+ IO (Decode16, 0x08c, 0x08c, 0x00, 0x03)\r
+ IO (Decode16, 0x090, 0x090, 0x00, 0x10)\r
+ IO (Decode16, 0x0A2, 0x0A2, 0x00, 0x1E)\r
+ IO (Decode16, 0x0E0, 0x0E0, 0x00, 0x10)\r
+ IO (Decode16, 0x1E0, 0x1E0, 0x00, 0x10)\r
+ IO (Decode16, 0x160, 0x160, 0x00, 0x10)\r
+ IO (Decode16, 0x278, 0x278, 0x00, 0x08)\r
+ IO (Decode16, 0x370, 0x370, 0x00, 0x02)\r
+ IO (Decode16, 0x378, 0x378, 0x00, 0x08)\r
+ IO (Decode16, 0x400, 0x400, 0x00, 0x40) // PMBLK1\r
+ IO (Decode16, 0x440, 0x440, 0x00, 0x10)\r
+ IO (Decode16, 0x678, 0x678, 0x00, 0x08)\r
+ IO (Decode16, 0x778, 0x778, 0x00, 0x08)\r
+ Memory32Fixed (ReadOnly, 0xFEC00000, 0x1000) // IO APIC\r
+ Memory32Fixed (ReadOnly, 0xFEE00000, 0x1000)\r
+ })\r
+ }\r
+\r
+ //\r
+ // PS/2 Keyboard and PC/AT Enhanced Keyboard 101/102\r
+ //\r
+ Device (PS2K) { \r
+ Name (_HID, EISAID ("PNP0303"))\r
+ Name (_CID, EISAID ("PNP030B"))\r
+ Name(_CRS,ResourceTemplate() {\r
+ IO (Decode16, 0x60, 0x60, 0x00, 0x01)\r
+ IO (Decode16, 0x64, 0x64, 0x00, 0x01)\r
+ IRQNoFlags () {1}\r
+ })\r
+ }\r
+\r
+ //\r
+ // PS/2 Mouse and Microsoft Mouse\r
+ //\r
+ Device (PS2M) { // PS/2 stype mouse port\r
+ Name (_HID, EISAID ("PNP0F03"))\r
+ Name (_CID, EISAID ("PNP0F13"))\r
+ Name (_CRS, ResourceTemplate() {\r
+ IRQNoFlags () {12}\r
+ })\r
+ }\r
+\r
+ //\r
+ // UART Serial Port - COM1\r
+ //\r
+ Device (UAR1) {\r
+ Name (_HID, EISAID ("PNP0501"))\r
+ Name (_DDN, "COM1")\r
+ Name (_UID, 0x01)\r
+ Name(_CRS,ResourceTemplate() {\r
+ IO (Decode16, 0x3F8, 0x3F8, 0x01, 0x08)\r
+ IRQ (Edge, ActiveHigh, Exclusive, ) {4}\r
+ })\r
+ }\r
+\r
+ //\r
+ // UART Serial Port - COM2\r
+ //\r
+ Device (UAR2) {\r
+ Name (_HID, EISAID ("PNP0501"))\r
+ Name (_DDN, "COM2")\r
+ Name (_UID, 0x02)\r
+ Name(_CRS,ResourceTemplate() {\r
+ IO (Decode16, 0x2F8, 0x2F8, 0x01, 0x08)\r
+ IRQ (Edge, ActiveHigh, Exclusive, ) {3}\r
+ })\r
+ }\r
+\r
+ //\r
+ // Floppy Disk Controller\r
+ //\r
+ Device (FDC) {\r
+ Name (_HID, EISAID ("PNP0700"))\r
+ Name (_CRS,ResourceTemplate() {\r
+ IO (Decode16, 0x3F0, 0x3F0, 0x01, 0x06)\r
+ IO (Decode16, 0x3F7, 0x3F7, 0x01, 0x01)\r
+ IRQNoFlags () {6}\r
+ DMA (Compatibility, NotBusMaster, Transfer8) {2}\r
+ })\r
+ }\r
+ }\r
+ }\r
+ }\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ FACP Table\r
+ \r
+ Copyright (c) 2008 - 2009, Intel Corporation<BR> All rights\r
+ reserved. This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/ \r
+ \r
+#include "Platform.h"\r
+\r
+EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r
+ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r
+ sizeof (EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE),\r
+ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r
+ 0, // to make sum of entire table == 0\r
+ EFI_ACPI_OEM_ID, // OEMID is a 6 bytes long field\r
+ EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r
+ EFI_ACPI_OEM_REVISION, // OEM revision number\r
+ EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r
+ EFI_ACPI_CREATOR_REVISION, // ASL compiler revision number\r
+ 0, // Physical addesss of FACS\r
+ 0, // Physical address of DSDT\r
+ INT_MODEL, // System Interrupt Model\r
+ RESERVED, // reserved\r
+ SCI_INT_VECTOR, // System vector of SCI interrupt\r
+ SMI_CMD_IO_PORT, // Port address of SMI command port\r
+ ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r
+ ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r
+ S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r
+ 0xE2, // PState control\r
+ PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk\r
+ PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk\r
+ PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk\r
+ PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk\r
+ PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk\r
+ PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk\r
+ GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk\r
+ GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk\r
+ PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r
+ PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r
+ PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r
+ PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r
+ GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r
+ GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r
+ GPE1_BASE, // offset in gpe model where gpe1 events start\r
+ 0xE3, // _CST support\r
+ P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r
+ P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r
+ FLUSH_SIZE, // Size of area read to flush caches\r
+ FLUSH_STRIDE, // Stride used in flushing caches\r
+ DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r
+ DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r
+ DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r
+ MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r
+ CENTURY, // index to century in RTC CMOS RAM\r
+ 0x03, // Boot architecture flag\r
+ 0x00, // Boot architecture flag\r
+ RESERVED, // reserved \r
+ FLAG\r
+};\r
+\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from removing the \r
+ // data structure from the exeutable\r
+ //\r
+ return (VOID*)&FACP;\r
+}\r
--- /dev/null
+/** @file\r
+ FACS Table\r
+ \r
+ Copyright (c) 2008 - 2009, Intel Corporation<BR> All rights\r
+ reserved. This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/ \r
+\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE FACS = {\r
+ EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE,\r
+ sizeof (EFI_ACPI_1_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),\r
+\r
+ //\r
+ // Hardware Signature will be updated at runtime\r
+ //\r
+ 0x00000000,\r
+ 0x00,\r
+ 0x00,\r
+ 0x00,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE,\r
+ EFI_ACPI_RESERVED_BYTE\r
+};\r
+\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from removing the \r
+ // data structure from the exeutable\r
+ //\r
+ return (VOID*)&FACS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ MADT Table\r
+\r
+ This file contains a structure definition for the ACPI 1.0 Multiple APIC \r
+ Description Table (MADT). \r
+ \r
+ Copyright (c) 2008 - 2009, Intel Corporation<BR> All rights\r
+ reserved. This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/ \r
+\r
+#include <IndustryStandard/Acpi.h>\r
+\r
+//\r
+// MADT Definitions\r
+//\r
+#define EFI_ACPI_OEM_MADT_REVISION 0x00000000 // TBD\r
+\r
+//\r
+// Local APIC address\r
+//\r
+#define EFI_ACPI_LOCAL_APIC_ADDRESS 0xFEE00000 // TBD\r
+\r
+//\r
+// Multiple APIC Flags are defined in AcpiX.0.h\r
+//\r
+#define EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS (EFI_ACPI_1_0_PCAT_COMPAT)\r
+\r
+//\r
+// Define the number of each table type.\r
+// This is where the table layout is modified.\r
+//\r
+#define EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT 1\r
+#define EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT 2\r
+#define EFI_ACPI_IO_APIC_COUNT 1\r
+\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack (1)\r
+\r
+//\r
+// ACPI 1.0 MADT structure\r
+//\r
+typedef struct {\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;\r
+\r
+#if EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT > 0\r
+ EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE LocalApic[EFI_ACPI_PROCESSOR_LOCAL_APIC_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT > 0\r
+ EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE Iso[EFI_ACPI_INTERRUPT_SOURCE_OVERRIDE_COUNT];\r
+#endif\r
+\r
+#if EFI_ACPI_IO_APIC_COUNT > 0\r
+ EFI_ACPI_1_0_IO_APIC_STRUCTURE IoApic[EFI_ACPI_IO_APIC_COUNT];\r
+#endif\r
+\r
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;\r
+\r
+#pragma pack ()\r
+\r
+//\r
+// Multiple APIC Description Table\r
+//\r
+EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {\r
+ EFI_ACPI_1_0_APIC_SIGNATURE,\r
+ sizeof (EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE),\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,\r
+\r
+ //\r
+ // Checksum will be updated at runtime\r
+ //\r
+ 0x00,\r
+ \r
+ //\r
+ // It is expected that these values will be programmed at runtime\r
+ //\r
+ ' ', ' ', ' ', ' ', ' ', ' ',\r
+ \r
+ 0,\r
+ EFI_ACPI_OEM_MADT_REVISION,\r
+ 0,\r
+ 0,\r
+\r
+ //\r
+ // MADT specific fields\r
+ //\r
+ EFI_ACPI_LOCAL_APIC_ADDRESS,\r
+ EFI_ACPI_1_0_MULTIPLE_APIC_FLAGS,\r
+ \r
+ //\r
+ // Processor Local APIC Structure\r
+ //\r
+\r
+ EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC, // Type\r
+ sizeof (EFI_ACPI_1_0_PROCESSOR_LOCAL_APIC_STRUCTURE), // Length\r
+ 0x01, // Processor ID\r
+ 0x00, // Local APIC ID\r
+ 0x00000001, // Flags - Enabled by default\r
+\r
+ //\r
+ // Interrupt Source Override Structure\r
+ //\r
+\r
+ //\r
+ // IRQ0=>IRQ2 Interrupt Source Override Structure\r
+ //\r
+ EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE, // Type\r
+ sizeof (EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length\r
+ 0x00, // Bus - ISA\r
+ 0x00, // Source - IRQ0\r
+ 0x00000002, // Global System Interrupt - IRQ2\r
+ 0x0000, // Flags - Conforms to specifications of the bus\r
+\r
+ //\r
+ // ISO (SCI Active High) Interrupt Source Override Structure\r
+ //\r
+ EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE, // Type\r
+ sizeof (EFI_ACPI_1_0_INTERRUPT_SOURCE_OVERRIDE_STRUCTURE),// Length\r
+ 0x00, // Bus - ISA\r
+ 0x09, // Source - IRQ0\r
+ 0x00000009, // Global System Interrupt - IRQ2\r
+ 0x000D, // Flags - Level-tiggered, Active High\r
+\r
+ //\r
+ // IO APIC Structure\r
+ //\r
+ EFI_ACPI_1_0_IO_APIC, // Type\r
+ sizeof (EFI_ACPI_1_0_IO_APIC_STRUCTURE), // Length\r
+ 0x02, // IO APIC ID\r
+ EFI_ACPI_RESERVED_BYTE, // Reserved\r
+ 0xFEC00000, // IO APIC Address (physical)\r
+ 0x00000000 // Global System Interrupt Base\r
+};\r
+\r
+\r
+VOID*\r
+ReferenceAcpiTable (\r
+ VOID\r
+ )\r
+{\r
+ //\r
+ // Reference the table being generated to prevent the optimizer from removing the \r
+ // data structure from the exeutable\r
+ //\r
+ return (VOID*)&Madt;\r
+}\r
--- /dev/null
+/** @file\r
+ Platform specific defines for constructing ACPI tables\r
+\r
+ Copyright (c) 2008, Intel Corporation<BR> All rights\r
+ reserved. This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/ \r
+\r
+#ifndef _Platform_h_INCLUDED_\r
+#define _Platform_h_INCLUDED_\r
+\r
+#include <PiDxe.h> \r
+#include <IndustryStandard/Acpi.h>\r
+\r
+//\r
+// ACPI table information used to initialize tables.\r
+//\r
+#define EFI_ACPI_OEM_ID 'O','V','M','F',' ',' ' // OEMID 6 bytes long\r
+#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('O','V','M','F','E','D','K','2') // OEM table id 8 bytes long\r
+#define EFI_ACPI_OEM_REVISION 0x02000820\r
+#define EFI_ACPI_CREATOR_ID SIGNATURE_32('O','V','M','F')\r
+#define EFI_ACPI_CREATOR_REVISION 0x00000097\r
+\r
+#define INT_MODEL 0x01\r
+#define SCI_INT_VECTOR 0x0009 \r
+#define SMI_CMD_IO_PORT 0x000000B2\r
+#define ACPI_ENABLE 0x0E1\r
+#define ACPI_DISABLE 0x01E\r
+#define S4BIOS_REQ 0x00\r
+#define PM1a_EVT_BLK 0x00000400\r
+#define PM1b_EVT_BLK 0x00000000\r
+#define PM1a_CNT_BLK 0x00000404\r
+#define PM1b_CNT_BLK 0x00000000\r
+#define PM2_CNT_BLK 0x00000022\r
+#define PM_TMR_BLK 0x00000408\r
+#define GPE0_BLK 0x0000040C\r
+#define GPE1_BLK 0x00000000\r
+#define PM1_EVT_LEN 0x04\r
+#define PM1_CNT_LEN 0x02\r
+#define PM2_CNT_LEN 0x01\r
+#define PM_TM_LEN 0x04\r
+#define GPE0_BLK_LEN 0x04\r
+#define GPE1_BLK_LEN 0x00\r
+#define GPE1_BASE 0x00\r
+#define RESERVED 0x00\r
+#define P_LVL2_LAT 0x0065\r
+#define P_LVL3_LAT 0x03E9\r
+#define FLUSH_SIZE 0x0400\r
+#define FLUSH_STRIDE 0x0010\r
+#define DUTY_OFFSET 0x00\r
+#define DUTY_WIDTH 0x00\r
+#define DAY_ALRM 0x0D\r
+#define MON_ALRM 0x00\r
+#define CENTURY 0x00\r
+#define FLAG EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | EFI_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_RTC_S4 | EFI_ACPI_1_0_TMR_VAL_EXT\r
+\r
+#endif\r
+\r
--- /dev/null
+/** @file\r
+ ACPI Timer implements one instance of Timer Library.\r
+\r
+ Copyright (c) 2008, Intel Corporation<BR> All rights\r
+ reserved. This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+ \r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/ \r
+\r
+#include <Base.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+\r
+#define ACPI_TIMER_FREQUENCY 3579545\r
+#define ACPI_TIMER_COUNT_SIZE 0x01000000\r
+\r
+/**\r
+ The constructor function enables ACPI IO space.\r
+\r
+ If ACPI I/O space not enabled, this function will enable it.\r
+ It will always return RETURN_SUCCESS.\r
+\r
+ @retval EFI_SUCCESS The constructor always returns RETURN_SUCCESS.\r
+\r
+**/\r
+RETURN_STATUS\r
+EFIAPI\r
+AcpiTimerLibConstructor (\r
+ VOID\r
+ )\r
+{\r
+ UINT8 Device;\r
+\r
+ Device = 1;\r
+ // Device = 7;\r
+\r
+ //\r
+ // ACPI Timer enable is in Bus 0, Device ?, Function 3\r
+ //\r
+ PciOr8 (PCI_LIB_ADDRESS (0,Device,3,0x04), 0x01);\r
+ PciAndThenOr32 (PCI_LIB_ADDRESS (0,Device,3,0x40), (UINT32) ~0xfc0, 0x400);\r
+ PciOr8 (PCI_LIB_ADDRESS (0,Device,3,0x80), 0x01); return RETURN_SUCCESS;\r
+}\r
+\r
+/**\r
+ Internal function to read the current tick counter of ACPI.\r
+\r
+ Internal function to read the current tick counter of ACPI.\r
+\r
+ @return The tick counter read.\r
+\r
+**/\r
+STATIC\r
+UINT32\r
+InternalAcpiGetTimerTick (\r
+ VOID\r
+ )\r
+{\r
+ return IoRead32 (0x408);\r
+}\r
+\r
+/**\r
+ Stalls the CPU for at least the given number of ticks.\r
+\r
+ Stalls the CPU for at least the given number of ticks. It's invoked by\r
+ MicroSecondDelay() and NanoSecondDelay().\r
+\r
+ @param Delay A period of time to delay in ticks.\r
+\r
+**/\r
+STATIC\r
+VOID\r
+InternalAcpiDelay (\r
+ IN UINT32 Delay\r
+ )\r
+{\r
+ UINT32 Ticks;\r
+ UINT32 Times;\r
+\r
+ Times = Delay >> 22;\r
+ Delay &= BIT22 - 1;\r
+ do {\r
+ //\r
+ // The target timer count is calculated here\r
+ //\r
+ Ticks = InternalAcpiGetTimerTick () + Delay;\r
+ Delay = BIT22;\r
+ //\r
+ // Wait until time out\r
+ // Delay >= 2^23 could not be handled by this function\r
+ // Timer wrap-arounds are handled correctly by this function\r
+ //\r
+ while (((Ticks - InternalAcpiGetTimerTick ()) & BIT23) == 0) {\r
+ CpuPause ();\r
+ }\r
+ } while (Times-- > 0);\r
+}\r
+\r
+/**\r
+ Stalls the CPU for at least the given number of microseconds.\r
+\r
+ Stalls the CPU for the number of microseconds specified by MicroSeconds.\r
+\r
+ @param MicroSeconds The minimum number of microseconds to delay.\r
+\r
+ @return MicroSeconds\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+MicroSecondDelay (\r
+ IN UINTN MicroSeconds\r
+ )\r
+{\r
+ InternalAcpiDelay (\r
+ (UINT32)DivU64x32 (\r
+ MultU64x32 (\r
+ MicroSeconds,\r
+ ACPI_TIMER_FREQUENCY\r
+ ),\r
+ 1000000u\r
+ )\r
+ );\r
+ return MicroSeconds;\r
+}\r
+\r
+/**\r
+ Stalls the CPU for at least the given number of nanoseconds.\r
+\r
+ Stalls the CPU for the number of nanoseconds specified by NanoSeconds.\r
+\r
+ @param NanoSeconds The minimum number of nanoseconds to delay.\r
+\r
+ @return NanoSeconds\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+NanoSecondDelay (\r
+ IN UINTN NanoSeconds\r
+ )\r
+{\r
+ InternalAcpiDelay (\r
+ (UINT32)DivU64x32 (\r
+ MultU64x32 (\r
+ NanoSeconds,\r
+ ACPI_TIMER_FREQUENCY\r
+ ),\r
+ 1000000000u\r
+ )\r
+ );\r
+ return NanoSeconds;\r
+}\r
+\r
+/**\r
+ Retrieves the current value of a 64-bit free running performance counter.\r
+\r
+ Retrieves the current value of a 64-bit free running performance counter. The\r
+ counter can either count up by 1 or count down by 1. If the physical\r
+ performance counter counts by a larger increment, then the counter values\r
+ must be translated. The properties of the counter can be retrieved from\r
+ GetPerformanceCounterProperties().\r
+\r
+ @return The current value of the free running performance counter.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetPerformanceCounter (\r
+ VOID\r
+ )\r
+{\r
+ return (UINT64)InternalAcpiGetTimerTick ();\r
+}\r
+\r
+/**\r
+ Retrieves the 64-bit frequency in Hz and the range of performance counter\r
+ values.\r
+\r
+ If StartValue is not NULL, then the value that the performance counter starts\r
+ with immediately after is it rolls over is returned in StartValue. If\r
+ EndValue is not NULL, then the value that the performance counter end with\r
+ immediately before it rolls over is returned in EndValue. The 64-bit\r
+ frequency of the performance counter in Hz is always returned. If StartValue\r
+ is less than EndValue, then the performance counter counts up. If StartValue\r
+ is greater than EndValue, then the performance counter counts down. For\r
+ example, a 64-bit free running counter that counts up would have a StartValue\r
+ of 0 and an EndValue of 0xFFFFFFFFFFFFFFFF. A 24-bit free running counter\r
+ that counts down would have a StartValue of 0xFFFFFF and an EndValue of 0.\r
+\r
+ @param StartValue The value the performance counter starts with when it\r
+ rolls over.\r
+ @param EndValue The value that the performance counter ends with before\r
+ it rolls over.\r
+\r
+ @return The frequency in Hz.\r
+\r
+**/\r
+UINT64\r
+EFIAPI\r
+GetPerformanceCounterProperties (\r
+ OUT UINT64 *StartValue, OPTIONAL\r
+ OUT UINT64 *EndValue OPTIONAL\r
+ )\r
+{\r
+ if (StartValue != NULL) {\r
+ *StartValue = 0;\r
+ }\r
+\r
+ if (EndValue != NULL) {\r
+ *EndValue = ACPI_TIMER_COUNT_SIZE - 1;\r
+ }\r
+\r
+ return ACPI_TIMER_FREQUENCY;\r
+}\r
--- /dev/null
+#/** @file\r
+# ACPI Timer Library Instance.\r
+#\r
+# Copyright (c) 2008, Intel Corporation. <BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = AcpiTimerLib\r
+ FILE_GUID = c300b1d9-31d4-4868-9de9-2f3551ff2c69\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = TimerLib\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+ CONSTRUCTOR = AcpiTimerLibConstructor\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+ AcpiTimerLib.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ PciLib\r
+ IoLib\r
+\r
--- /dev/null
+/** @file\r
+ Platform BDS customizations.\r
+\r
+ Copyright (c) 2004 - 2008, Intel Corporation. <BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BdsPlatform.h"\r
+\r
+\r
+//\r
+// BDS Platform Functions\r
+//\r
+VOID\r
+EFIAPI\r
+PlatformBdsInit (\r
+ IN EFI_BDS_ARCH_PROTOCOL_INSTANCE *PrivateData\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Platform Bds init. Incude the platform firmware vendor, revision\r
+ and so crc check.\r
+\r
+Arguments:\r
+\r
+ PrivateData - The EFI_BDS_ARCH_PROTOCOL_INSTANCE instance\r
+\r
+Returns:\r
+\r
+ None.\r
+\r
+--*/\r
+{\r
+ DEBUG ((EFI_D_INFO, "PlatformBdsInit\n"));\r
+}\r
+\r
+\r
+EFI_STATUS\r
+ConnectRootBridge (\r
+ VOID\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Connect RootBridge\r
+\r
+Arguments:\r
+\r
+ None.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Connect RootBridge successfully.\r
+ EFI_STATUS - Connect RootBridge fail.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE RootHandle;\r
+\r
+ //\r
+ // Make all the PCI_IO protocols on PCI Seg 0 show up\r
+ //\r
+ BdsLibConnectDevicePath (gPlatformRootBridges[0]);\r
+\r
+ Status = gBS->LocateDevicePath (\r
+ &gEfiDevicePathProtocolGuid,\r
+ &gPlatformRootBridges[0],\r
+ &RootHandle\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = gBS->ConnectController (RootHandle, NULL, NULL, FALSE);\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PrepareLpcBridgeDevicePath (\r
+ IN EFI_HANDLE DeviceHandle\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Add IsaKeyboard to ConIn,\r
+ add IsaSerial to ConOut, ConIn, ErrOut.\r
+ LPC Bridge: 06 01 00\r
+\r
+Arguments:\r
+\r
+ DeviceHandle - Handle of PCIIO protocol.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - LPC bridge is added to ConOut, ConIn, and ErrOut.\r
+ EFI_STATUS - No LPC bridge is added.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;\r
+ CHAR16 *DevPathStr;\r
+\r
+ DevicePath = NULL;\r
+ Status = gBS->HandleProtocol (\r
+ DeviceHandle,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID*)&DevicePath\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+ TempDevicePath = DevicePath;\r
+\r
+ //\r
+ // Register Keyboard\r
+ //\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gPnpPs2KeyboardDeviceNode);\r
+\r
+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL);\r
+\r
+ //\r
+ // Register COM1\r
+ //\r
+ DevicePath = TempDevicePath;\r
+ gPnp16550ComPortDeviceNode.UID = 0;\r
+\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gPnp16550ComPortDeviceNode);\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);\r
+\r
+ //\r
+ // Print Device Path\r
+ //\r
+ DevPathStr = DevicePathToStr(DevicePath);\r
+ DEBUG((\r
+ EFI_D_INFO,\r
+ "BdsPlatform.c+%d: COM%d DevPath: %s\n",\r
+ __LINE__,\r
+ gPnp16550ComPortDeviceNode.UID + 1,\r
+ DevPathStr\r
+ ));\r
+ FreePool(DevPathStr);\r
+\r
+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL);\r
+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL);\r
+ BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL);\r
+\r
+ //\r
+ // Register COM2\r
+ //\r
+ DevicePath = TempDevicePath;\r
+ gPnp16550ComPortDeviceNode.UID = 1;\r
+\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gPnp16550ComPortDeviceNode);\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);\r
+\r
+ //\r
+ // Print Device Path\r
+ //\r
+ DevPathStr = DevicePathToStr(DevicePath);\r
+ DEBUG((\r
+ EFI_D_INFO,\r
+ "BdsPlatform.c+%d: COM%d DevPath: %s\n",\r
+ __LINE__,\r
+ gPnp16550ComPortDeviceNode.UID + 1,\r
+ DevPathStr\r
+ ));\r
+ FreePool(DevPathStr);\r
+\r
+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL);\r
+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL);\r
+ BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+GetGopDevicePath (\r
+ IN EFI_DEVICE_PATH_PROTOCOL *PciDevicePath,\r
+ OUT EFI_DEVICE_PATH_PROTOCOL **GopDevicePath\r
+ )\r
+{\r
+ UINTN Index;\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE PciDeviceHandle;\r
+ EFI_DEVICE_PATH_PROTOCOL *TempDevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *TempPciDevicePath;\r
+ UINTN GopHandleCount;\r
+ EFI_HANDLE *GopHandleBuffer;\r
+\r
+ if (PciDevicePath == NULL || GopDevicePath == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ //\r
+ // Initialize the GopDevicePath to be PciDevicePath\r
+ //\r
+ *GopDevicePath = PciDevicePath;\r
+ TempPciDevicePath = PciDevicePath;\r
+\r
+ Status = gBS->LocateDevicePath (\r
+ &gEfiDevicePathProtocolGuid,\r
+ &TempPciDevicePath,\r
+ &PciDeviceHandle\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ //\r
+ // Try to connect this handle, so that GOP dirver could start on this\r
+ // device and create child handles with GraphicsOutput Protocol installed\r
+ // on them, then we get device paths of these child handles and select\r
+ // them as possible console device.\r
+ //\r
+ gBS->ConnectController (PciDeviceHandle, NULL, NULL, FALSE);\r
+\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ &gEfiGraphicsOutputProtocolGuid,\r
+ NULL,\r
+ &GopHandleCount,\r
+ &GopHandleBuffer\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // Add all the child handles as possible Console Device\r
+ //\r
+ for (Index = 0; Index < GopHandleCount; Index++) {\r
+ Status = gBS->HandleProtocol (GopHandleBuffer[Index], &gEfiDevicePathProtocolGuid, (VOID*)&TempDevicePath);\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+ if (CompareMem (\r
+ PciDevicePath,\r
+ TempDevicePath,\r
+ GetDevicePathSize (PciDevicePath) - END_DEVICE_PATH_LENGTH\r
+ ) == 0) {\r
+ //\r
+ // In current implementation, we only enable one of the child handles\r
+ // as console device, i.e. sotre one of the child handle's device\r
+ // path to variable "ConOut"\r
+ // In futhure, we could select all child handles to be console device\r
+ //\r
+\r
+ *GopDevicePath = TempDevicePath;\r
+\r
+ //\r
+ // Delete the PCI device's path that added by GetPlugInPciVgaDevicePath()\r
+ // Add the integrity GOP device path.\r
+ //\r
+ BdsLibUpdateConsoleVariable (VarConsoleOutDev, NULL, PciDevicePath);\r
+ BdsLibUpdateConsoleVariable (VarConsoleOutDev, TempDevicePath, NULL);\r
+ }\r
+ }\r
+ gBS->FreePool (GopHandleBuffer);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+PreparePciVgaDevicePath (\r
+ IN EFI_HANDLE DeviceHandle\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Add PCI VGA to ConOut.\r
+ PCI VGA: 03 00 00\r
+\r
+Arguments:\r
+\r
+ DeviceHandle - Handle of PCIIO protocol.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - PCI VGA is added to ConOut.\r
+ EFI_STATUS - No PCI VGA device is added.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+ EFI_DEVICE_PATH_PROTOCOL *GopDevicePath;\r
+\r
+ DevicePath = NULL;\r
+ Status = gBS->HandleProtocol (\r
+ DeviceHandle,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID*)&DevicePath\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ GetGopDevicePath (DevicePath, &GopDevicePath);\r
+ DevicePath = GopDevicePath;\r
+\r
+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+PreparePciSerialDevicePath (\r
+ IN EFI_HANDLE DeviceHandle\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Add PCI Serial to ConOut, ConIn, ErrOut.\r
+ PCI Serial: 07 00 02\r
+\r
+Arguments:\r
+\r
+ DeviceHandle - Handle of PCIIO protocol.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - PCI Serial is added to ConOut, ConIn, and ErrOut.\r
+ EFI_STATUS - No PCI Serial device is added.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePath;\r
+\r
+ DevicePath = NULL;\r
+ Status = gBS->HandleProtocol (\r
+ DeviceHandle,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID*)&DevicePath\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gUartDeviceNode);\r
+ DevicePath = AppendDevicePathNode (DevicePath, (EFI_DEVICE_PATH_PROTOCOL *)&gTerminalTypeDeviceNode);\r
+\r
+ BdsLibUpdateConsoleVariable (VarConsoleOut, DevicePath, NULL);\r
+ BdsLibUpdateConsoleVariable (VarConsoleInp, DevicePath, NULL);\r
+ BdsLibUpdateConsoleVariable (VarErrorOut, DevicePath, NULL);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+DetectAndPreparePlatformPciDevicePath (\r
+ BOOLEAN DetectVgaOnly\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut\r
+\r
+Arguments:\r
+\r
+ DetectVgaOnly - Only detect VGA device if it's TRUE.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - PCI Device check and Console variable update successfully.\r
+ EFI_STATUS - PCI Device check or Console variable update fail.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN HandleCount;\r
+ EFI_HANDLE *HandleBuffer;\r
+ UINTN Index;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ PCI_TYPE00 Pci;\r
+\r
+ //\r
+ // Start to check all the PciIo to find all possible device\r
+ //\r
+ HandleCount = 0;\r
+ HandleBuffer = NULL;\r
+ Status = gBS->LocateHandleBuffer (\r
+ ByProtocol,\r
+ &gEfiPciIoProtocolGuid,\r
+ NULL,\r
+ &HandleCount,\r
+ &HandleBuffer\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ for (Index = 0; Index < HandleCount; Index++) {\r
+ Status = gBS->HandleProtocol (HandleBuffer[Index], &gEfiPciIoProtocolGuid, (VOID*)&PciIo);\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+\r
+ //\r
+ // Check for all PCI device\r
+ //\r
+ Status = PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint32,\r
+ 0,\r
+ sizeof (Pci) / sizeof (UINT32),\r
+ &Pci\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ continue;\r
+ }\r
+\r
+ if (!DetectVgaOnly) {\r
+ //\r
+ // Here we decide whether it is LPC Bridge\r
+ //\r
+ if ((IS_PCI_LPC (&Pci)) ||\r
+ ((IS_PCI_ISA_PDECODE (&Pci)) &&\r
+ (Pci.Hdr.VendorId == 0x8086) &&\r
+ (Pci.Hdr.DeviceId == 0x7000)\r
+ )\r
+ ) {\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationEnable,\r
+ EFI_PCI_DEVICE_ENABLE,\r
+ NULL\r
+ );\r
+ //\r
+ // Add IsaKeyboard to ConIn,\r
+ // add IsaSerial to ConOut, ConIn, ErrOut\r
+ //\r
+ DEBUG ((EFI_D_INFO, "Find the LPC Bridge device\n"));\r
+ PrepareLpcBridgeDevicePath (HandleBuffer[Index]);\r
+ continue;\r
+ }\r
+ //\r
+ // Here we decide which Serial device to enable in PCI bus\r
+ //\r
+ if (IS_PCI_16550SERIAL (&Pci)) {\r
+ //\r
+ // Add them to ConOut, ConIn, ErrOut.\r
+ //\r
+ DEBUG ((EFI_D_INFO, "Find the 16550 SERIAL device\n"));\r
+ PreparePciSerialDevicePath (HandleBuffer[Index]);\r
+ continue;\r
+ }\r
+ }\r
+\r
+ if ((Pci.Hdr.VendorId == 0x8086) &&\r
+ (Pci.Hdr.DeviceId == 0x7010)\r
+ ) {\r
+ Status = PciIo->Attributes (\r
+ PciIo,\r
+ EfiPciIoAttributeOperationEnable,\r
+ EFI_PCI_DEVICE_ENABLE,\r
+ NULL\r
+ );\r
+ }\r
+\r
+ //\r
+ // Here we decide which VGA device to enable in PCI bus\r
+ //\r
+ if (IS_PCI_VGA (&Pci)) {\r
+ //\r
+ // Add them to ConOut.\r
+ //\r
+ DEBUG ((EFI_D_INFO, "Find the VGA device\n"));\r
+ PreparePciVgaDevicePath (HandleBuffer[Index]);\r
+ continue;\r
+ }\r
+ }\r
+\r
+ gBS->FreePool (HandleBuffer);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+EFI_STATUS\r
+PlatformBdsConnectConsole (\r
+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Connect the predefined platform default console device. Always try to find\r
+ and enable the vga device if have.\r
+\r
+Arguments:\r
+\r
+ PlatformConsole - Predfined platform default console device array.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Success connect at least one ConIn and ConOut\r
+ device, there must have one ConOut device is\r
+ active vga device.\r
+\r
+ EFI_STATUS - Return the status of\r
+ BdsLibConnectAllDefaultConsoles ()\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN Index;\r
+ EFI_DEVICE_PATH_PROTOCOL *VarConout;\r
+ EFI_DEVICE_PATH_PROTOCOL *VarConin;\r
+ UINTN DevicePathSize;\r
+\r
+ //\r
+ // Connect RootBridge\r
+ //\r
+ ConnectRootBridge ();\r
+\r
+ VarConout = BdsLibGetVariableAndSize (\r
+ VarConsoleOut,\r
+ &gEfiGlobalVariableGuid,\r
+ &DevicePathSize\r
+ );\r
+ VarConin = BdsLibGetVariableAndSize (\r
+ VarConsoleInp,\r
+ &gEfiGlobalVariableGuid,\r
+ &DevicePathSize\r
+ );\r
+\r
+ if (VarConout == NULL || VarConin == NULL) {\r
+ //\r
+ // Do platform specific PCI Device check and add them to ConOut, ConIn, ErrOut\r
+ //\r
+ DetectAndPreparePlatformPciDevicePath (FALSE);\r
+\r
+ //\r
+ // Have chance to connect the platform default console,\r
+ // the platform default console is the minimue device group\r
+ // the platform should support\r
+ //\r
+ for (Index = 0; PlatformConsole[Index].DevicePath != NULL; ++Index) {\r
+ //\r
+ // Update the console variable with the connect type\r
+ //\r
+ if ((PlatformConsole[Index].ConnectType & CONSOLE_IN) == CONSOLE_IN) {\r
+ BdsLibUpdateConsoleVariable (VarConsoleInp, PlatformConsole[Index].DevicePath, NULL);\r
+ }\r
+ if ((PlatformConsole[Index].ConnectType & CONSOLE_OUT) == CONSOLE_OUT) {\r
+ BdsLibUpdateConsoleVariable (VarConsoleOut, PlatformConsole[Index].DevicePath, NULL);\r
+ }\r
+ if ((PlatformConsole[Index].ConnectType & STD_ERROR) == STD_ERROR) {\r
+ BdsLibUpdateConsoleVariable (VarErrorOut, PlatformConsole[Index].DevicePath, NULL);\r
+ }\r
+ }\r
+ } else {\r
+ //\r
+ // Only detect VGA device and add them to ConOut\r
+ //\r
+ DetectAndPreparePlatformPciDevicePath (TRUE);\r
+ }\r
+\r
+ //\r
+ // Connect the all the default console with current cosole variable\r
+ //\r
+ Status = BdsLibConnectAllDefaultConsoles ();\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+VOID\r
+PciInitialization (\r
+ )\r
+{\r
+ //\r
+ // Device 0 Function 0\r
+ //\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,0,0,0x3c), 0x00);\r
+\r
+ //\r
+ // Device 1 Function 0\r
+ //\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,1,0,0x3c), 0x00);\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,1,0,0x60), 0x8b);\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,1,0,0x61), 0x89);\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,1,0,0x62), 0x0a);\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,1,0,0x63), 0x89);\r
+ //PciWrite8 (PCI_LIB_ADDRESS (0,1,0,0x82), 0x02);\r
+\r
+ //\r
+ // Device 1 Function 1\r
+ //\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,1,1,0x3c), 0x00);\r
+\r
+ //\r
+ // Device 1 Function 3\r
+ //\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,1,3,0x3c), 0x0b);\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,1,3,0x3d), 0x01);\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,1,3,0x5f), 0x90);\r
+\r
+ //\r
+ // Device 2 Function 0\r
+ //\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,2,0,0x3c), 0x00);\r
+\r
+ //\r
+ // Device 3 Function 0\r
+ //\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,3,0,0x3c), 0x0b);\r
+ PciWrite8 (PCI_LIB_ADDRESS (0,3,0,0x3d), 0x01);\r
+}\r
+\r
+\r
+VOID\r
+PlatformBdsConnectSequence (\r
+ VOID\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Connect with predeined platform connect sequence,\r
+ the OEM/IBV can customize with their own connect sequence.\r
+\r
+Arguments:\r
+\r
+ None.\r
+\r
+Returns:\r
+\r
+ None.\r
+\r
+--*/\r
+{\r
+ UINTN Index;\r
+\r
+ DEBUG ((EFI_D_INFO, "PlatformBdsConnectSequence\n"));\r
+\r
+ Index = 0;\r
+\r
+ //\r
+ // Here we can get the customized platform connect sequence\r
+ // Notes: we can connect with new variable which record the\r
+ // last time boots connect device path sequence\r
+ //\r
+ while (gPlatformConnectSequence[Index] != NULL) {\r
+ //\r
+ // Build the platform boot option\r
+ //\r
+ BdsLibConnectDevicePath (gPlatformConnectSequence[Index]);\r
+ Index++;\r
+ }\r
+\r
+ //\r
+ // Just use the simple policy to connect all devices\r
+ //\r
+ BdsLibConnectAll ();\r
+\r
+ PciInitialization ();\r
+}\r
+\r
+VOID\r
+PlatformBdsGetDriverOption (\r
+ IN OUT LIST_ENTRY *BdsDriverLists\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Load the predefined driver option, OEM/IBV can customize this\r
+ to load their own drivers\r
+\r
+Arguments:\r
+\r
+ BdsDriverLists - The header of the driver option link list.\r
+\r
+Returns:\r
+\r
+ None.\r
+\r
+--*/\r
+{\r
+ DEBUG ((EFI_D_INFO, "PlatformBdsGetDriverOption\n"));\r
+ return;\r
+}\r
+\r
+VOID\r
+PlatformBdsDiagnostics (\r
+ IN EXTENDMEM_COVERAGE_LEVEL MemoryTestLevel,\r
+ IN BOOLEAN QuietBoot\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Perform the platform diagnostic, such like test memory. OEM/IBV also\r
+ can customize this fuction to support specific platform diagnostic.\r
+\r
+Arguments:\r
+\r
+ MemoryTestLevel - The memory test intensive level\r
+\r
+ QuietBoot - Indicate if need to enable the quiet boot\r
+\r
+Returns:\r
+\r
+ None.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ DEBUG ((EFI_D_INFO, "PlatformBdsDiagnostics\n"));\r
+\r
+ //\r
+ // Here we can decide if we need to show\r
+ // the diagnostics screen\r
+ // Notes: this quiet boot code should be remove\r
+ // from the graphic lib\r
+ //\r
+ if (QuietBoot) {\r
+ EnableQuietBoot (&gEfiDefaultBmpLogoGuid);\r
+ //\r
+ // Perform system diagnostic\r
+ //\r
+ Status = BdsMemoryTest (MemoryTestLevel);\r
+ if (EFI_ERROR (Status)) {\r
+ DisableQuietBoot ();\r
+ }\r
+\r
+ return ;\r
+ }\r
+ //\r
+ // Perform system diagnostic\r
+ //\r
+ Status = BdsMemoryTest (MemoryTestLevel);\r
+}\r
+\r
+\r
+VOID\r
+EFIAPI\r
+PlatformBdsPolicyBehavior (\r
+ IN EFI_BDS_ARCH_PROTOCOL_INSTANCE *PrivateData,\r
+ IN OUT LIST_ENTRY *DriverOptionList,\r
+ IN OUT LIST_ENTRY *BootOptionList\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ The function will excute with as the platform policy, current policy\r
+ is driven by boot mode. IBV/OEM can customize this code for their specific\r
+ policy action.\r
+\r
+Arguments:\r
+\r
+ PrivateData - The EFI_BDS_ARCH_PROTOCOL_INSTANCE instance\r
+\r
+ DriverOptionList - The header of the driver option link list\r
+\r
+ BootOptionList - The header of the boot option link list\r
+\r
+Returns:\r
+\r
+ None.\r
+\r
+--*/\r
+{\r
+ EFI_STATUS Status;\r
+ UINT16 Timeout;\r
+ EFI_EVENT UserInputDurationTime;\r
+ LIST_ENTRY *Link;\r
+ BDS_COMMON_OPTION *BootOption;\r
+ UINTN Index;\r
+ EFI_INPUT_KEY Key;\r
+ EFI_TPL OldTpl;\r
+\r
+ DEBUG ((EFI_D_INFO, "PlatformBdsPolicyBehavior\n"));\r
+\r
+ //\r
+ // Init the time out value\r
+ //\r
+ Timeout = PcdGet16 (PcdPlatformBootTimeOut);\r
+\r
+ //\r
+ // Load the driver option as the driver option list\r
+ //\r
+ PlatformBdsGetDriverOption (DriverOptionList);\r
+\r
+ //\r
+ // Get current Boot Mode\r
+ //\r
+ Status = BdsLibGetBootMode (&PrivateData->BootMode);\r
+ DEBUG ((EFI_D_ERROR, "Boot Mode:%x\n", PrivateData->BootMode));\r
+\r
+ //\r
+ // Go the different platform policy with different boot mode\r
+ // Notes: this part code can be change with the table policy\r
+ //\r
+ ASSERT (PrivateData->BootMode == BOOT_WITH_FULL_CONFIGURATION);\r
+ //\r
+ // Connect platform console\r
+ //\r
+ Status = PlatformBdsConnectConsole (gPlatformConsole);\r
+ if (EFI_ERROR (Status)) {\r
+ //\r
+ // Here OEM/IBV can customize with defined action\r
+ //\r
+ PlatformBdsNoConsoleAction ();\r
+ }\r
+ //\r
+ // Create a 300ms duration event to ensure user has enough input time to enter Setup\r
+ //\r
+ Status = gBS->CreateEvent (\r
+ EVT_TIMER,\r
+ 0,\r
+ NULL,\r
+ NULL,\r
+ &UserInputDurationTime\r
+ );\r
+ ASSERT (Status == EFI_SUCCESS);\r
+ Status = gBS->SetTimer (UserInputDurationTime, TimerRelative, 3000000);\r
+ ASSERT (Status == EFI_SUCCESS);\r
+ //\r
+ // Memory test and Logo show\r
+ //\r
+ PlatformBdsDiagnostics (IGNORE, TRUE);\r
+\r
+ //\r
+ // Perform some platform specific connect sequence\r
+ //\r
+ PlatformBdsConnectSequence ();\r
+\r
+ //\r
+ // Give one chance to enter the setup if we\r
+ // have the time out\r
+ //\r
+ if (Timeout != 0) {\r
+ //PlatformBdsEnterFrontPage (Timeout, FALSE);\r
+ }\r
+\r
+ DEBUG ((EFI_D_INFO, "BdsLibConnectAll\n"));\r
+ BdsLibConnectAll ();\r
+ BdsLibEnumerateAllBootOption (BootOptionList);\r
+\r
+ //\r
+ // Please uncomment above ConnectAll and EnumerateAll code and remove following first boot\r
+ // checking code in real production tip.\r
+ //\r
+ // In BOOT_WITH_FULL_CONFIGURATION boot mode, should always connect every device\r
+ // and do enumerate all the default boot options. But in development system board, the boot mode\r
+ // cannot be BOOT_ASSUMING_NO_CONFIGURATION_CHANGES because the machine box\r
+ // is always open. So the following code only do the ConnectAll and EnumerateAll at first boot.\r
+ //\r
+ Status = BdsLibBuildOptionFromVar (BootOptionList, L"BootOrder");\r
+ if (EFI_ERROR(Status)) {\r
+ //\r
+ // If cannot find "BootOrder" variable, it may be first boot.\r
+ // Try to connect all devices and enumerate all boot options here.\r
+ //\r
+ BdsLibConnectAll ();\r
+ BdsLibEnumerateAllBootOption (BootOptionList);\r
+ }\r
+\r
+ //\r
+ // To give the User a chance to enter Setup here, if user set TimeOut is 0.\r
+ // BDS should still give user a chance to enter Setup\r
+ //\r
+ // Connect first boot option, and then check user input before exit\r
+ //\r
+ for (Link = BootOptionList->ForwardLink; Link != BootOptionList;Link = Link->ForwardLink) {\r
+ BootOption = CR (Link, BDS_COMMON_OPTION, Link, BDS_LOAD_OPTION_SIGNATURE);\r
+ if (!IS_LOAD_OPTION_TYPE (BootOption->Attribute, LOAD_OPTION_ACTIVE)) {\r
+ //\r
+ // skip the header of the link list, becuase it has no boot option\r
+ //\r
+ continue;\r
+ } else {\r
+ //\r
+ // Make sure the boot option device path connected, but ignore the BBS device path\r
+ //\r
+ if (DevicePathType (BootOption->DevicePath) != BBS_DEVICE_PATH) {\r
+ BdsLibConnectDevicePath (BootOption->DevicePath);\r
+ }\r
+ break;\r
+ }\r
+ }\r
+\r
+ //\r
+ // Check whether the user input after the duration time has expired\r
+ //\r
+ OldTpl = EfiGetCurrentTpl();\r
+ gBS->RestoreTPL (TPL_APPLICATION);\r
+ gBS->WaitForEvent (1, &UserInputDurationTime, &Index);\r
+ gBS->CloseEvent (UserInputDurationTime);\r
+ Status = gST->ConIn->ReadKeyStroke (gST->ConIn, &Key);\r
+ gBS->RaiseTPL (OldTpl);\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ //\r
+ // Enter Setup if user input\r
+ //\r
+ Timeout = 0xffff;\r
+ PlatformBdsEnterFrontPage (Timeout, FALSE);\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformBdsBootSuccess (\r
+ IN BDS_COMMON_OPTION *Option\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Hook point after a boot attempt succeeds. We don't expect a boot option to\r
+ return, so the EFI 1.0 specification defines that you will default to an\r
+ interactive mode and stop processing the BootOrder list in this case. This\r
+ is alos a platform implementation and can be customized by IBV/OEM.\r
+\r
+Arguments:\r
+\r
+ Option - Pointer to Boot Option that succeeded to boot.\r
+\r
+Returns:\r
+\r
+ None.\r
+\r
+--*/\r
+{\r
+ CHAR16 *TmpStr;\r
+\r
+ DEBUG ((EFI_D_INFO, "PlatformBdsBootSuccess\n"));\r
+ //\r
+ // If Boot returned with EFI_SUCCESS and there is not in the boot device\r
+ // select loop then we need to pop up a UI and wait for user input.\r
+ //\r
+ TmpStr = Option->StatusString;\r
+ if (TmpStr != NULL) {\r
+ BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL);\r
+ FreePool (TmpStr);\r
+ }\r
+}\r
+\r
+VOID\r
+EFIAPI\r
+PlatformBdsBootFail (\r
+ IN BDS_COMMON_OPTION *Option,\r
+ IN EFI_STATUS Status,\r
+ IN CHAR16 *ExitData,\r
+ IN UINTN ExitDataSize\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ Hook point after a boot attempt fails.\r
+\r
+Arguments:\r
+\r
+ Option - Pointer to Boot Option that failed to boot.\r
+\r
+ Status - Status returned from failed boot.\r
+\r
+ ExitData - Exit data returned from failed boot.\r
+\r
+ ExitDataSize - Exit data size returned from failed boot.\r
+\r
+Returns:\r
+\r
+ None.\r
+\r
+--*/\r
+{\r
+ CHAR16 *TmpStr;\r
+\r
+ DEBUG ((EFI_D_INFO, "PlatformBdsBootFail\n"));\r
+\r
+ //\r
+ // If Boot returned with failed status then we need to pop up a UI and wait\r
+ // for user input.\r
+ //\r
+ TmpStr = Option->StatusString;\r
+ if (TmpStr != NULL) {\r
+ BdsLibOutputStrings (gST->ConOut, TmpStr, Option->Description, L"\n\r", NULL);\r
+ FreePool (TmpStr);\r
+ }\r
+}\r
+\r
+EFI_STATUS\r
+PlatformBdsNoConsoleAction (\r
+ VOID\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ This function is remained for IBV/OEM to do some platform action,\r
+ if there no console device can be connected.\r
+\r
+Arguments:\r
+\r
+ None.\r
+\r
+Returns:\r
+\r
+ EFI_SUCCESS - Direct return success now.\r
+\r
+--*/\r
+{\r
+ DEBUG ((EFI_D_INFO, "PlatformBdsNoConsoleAction\n"));\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+PlatformBdsLockNonUpdatableFlash (\r
+ VOID\r
+ )\r
+{\r
+ DEBUG ((EFI_D_INFO, "PlatformBdsLockNonUpdatableFlash\n"));\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+ Platform BDS customizations include file.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+Module Name:\r
+\r
+ BdsPlatform.h\r
+\r
+Abstract:\r
+\r
+ Head file for BDS Platform specific code\r
+\r
+**/\r
+\r
+#ifndef _PLATFORM_SPECIFIC_BDS_PLATFORM_H_\r
+#define _PLATFORM_SPECIFIC_BDS_PLATFORM_H_\r
+\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+#include <IndustryStandard/Acpi.h>\r
+#include <IndustryStandard/SmBios.h>\r
+//#include <IndustryStandard/LegacyBiosMpTable.h>\r
+\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiRuntimeServicesTableLib.h>\r
+#include <Library/MemoryAllocationLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/GenericBdsLib.h>\r
+#include <Library/PlatformBdsLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/DxeServicesTableLib.h>\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/IoLib.h>\r
+\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/FirmwareVolume2.h>\r
+\r
+#include <Guid/Logo.h>\r
+#include <Guid/Acpi.h>\r
+#include <Guid/SmBios.h>\r
+#include <Guid/Mps.h>\r
+#include <Guid/HobList.h>\r
+//#include <Guid/PciExpressBaseAddress.h>\r
+#include <Guid/GlobalVariable.h>\r
+#include <Guid/ShellFile.h>\r
+\r
+extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[];\r
+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[];\r
+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption[];\r
+extern EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[];\r
+extern ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode;\r
+extern ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode;\r
+extern UART_DEVICE_PATH gUartDeviceNode;\r
+extern VENDOR_DEVICE_PATH gTerminalTypeDeviceNode;\r
+//\r
+//\r
+//\r
+#define VarConsoleInpDev L"ConInDev"\r
+#define VarConsoleInp L"ConIn"\r
+#define VarConsoleOutDev L"ConOutDev"\r
+#define VarConsoleOut L"ConOut"\r
+#define VarErrorOutDev L"ErrOutDev"\r
+#define VarErrorOut L"ErrOut"\r
+\r
+#define PCI_DEVICE_PATH_NODE(Func, Dev) \\r
+ { \\r
+ HARDWARE_DEVICE_PATH, \\r
+ HW_PCI_DP, \\r
+ (UINT8) (sizeof (PCI_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (PCI_DEVICE_PATH)) >> 8), \\r
+ (Func), \\r
+ (Dev) \\r
+ }\r
+\r
+#define PNPID_DEVICE_PATH_NODE(PnpId) \\r
+ { \\r
+ ACPI_DEVICE_PATH, \\r
+ ACPI_DP, \\r
+ (UINT8) (sizeof (ACPI_HID_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (ACPI_HID_DEVICE_PATH)) >> 8), \\r
+ EISA_PNP_ID((PnpId)), \\r
+ 0 \\r
+ }\r
+\r
+#define gPciRootBridge \\r
+ PNPID_DEVICE_PATH_NODE(0x0A03)\r
+\r
+#define gPciIsaBridge \\r
+ PCI_DEVICE_PATH_NODE(0, 0x1f)\r
+\r
+#define gP2PBridge \\r
+ PCI_DEVICE_PATH_NODE(0, 0x1e)\r
+\r
+#define gPnpPs2Keyboard \\r
+ PNPID_DEVICE_PATH_NODE(0x0303)\r
+\r
+#define gPnp16550ComPort \\r
+ PNPID_DEVICE_PATH_NODE(0x0501)\r
+\r
+#define gUart \\r
+ { \\r
+ MESSAGING_DEVICE_PATH, \\r
+ MSG_UART_DP, \\r
+ (UINT8) (sizeof (UART_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (UART_DEVICE_PATH)) >> 8), \\r
+ 0, \\r
+ 115200, \\r
+ 8, \\r
+ 1, \\r
+ 1 \\r
+ }\r
+\r
+#define gPcAnsiTerminal \\r
+ { \\r
+ MESSAGING_DEVICE_PATH, \\r
+ MSG_VENDOR_DP, \\r
+ (UINT8) (sizeof (VENDOR_DEVICE_PATH)), \\r
+ (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8), \\r
+ DEVICE_PATH_MESSAGING_PC_ANSI \\r
+ }\r
+\r
+#define gEndEntire \\r
+ { \\r
+ END_DEVICE_PATH_TYPE, \\r
+ END_ENTIRE_DEVICE_PATH_SUBTYPE, \\r
+ END_DEVICE_PATH_LENGTH, \\r
+ 0 \\r
+ }\r
+\r
+#define PCI_CLASS_SCC 0x07\r
+#define PCI_SUBCLASS_SERIAL 0x00\r
+#define PCI_IF_16550 0x02\r
+#define IS_PCI_16550SERIAL(_p) IS_CLASS3 (_p, PCI_CLASS_SCC, PCI_SUBCLASS_SERIAL, PCI_IF_16550)\r
+\r
+#define EFI_SYSTEM_TABLE_MAX_ADDRESS 0xFFFFFFFF\r
+#define SYS_TABLE_PAD(ptr) (((~ptr) +1) & 0x07 )\r
+\r
+#define IS_PCI_ISA_PDECODE(_p) IS_CLASS3 (_p, PCI_CLASS_BRIDGE, PCI_CLASS_BRIDGE_ISA_PDECODE, 0)\r
+\r
+//\r
+// Platform Root Bridge\r
+//\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH PciRootBridge;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} PLATFORM_ROOT_BRIDGE_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH PciRootBridge;\r
+ PCI_DEVICE_PATH IsaBridge;\r
+ ACPI_HID_DEVICE_PATH Keyboard;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} PLATFORM_DUMMY_ISA_KEYBOARD_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH PciRootBridge;\r
+ PCI_DEVICE_PATH IsaBridge;\r
+ ACPI_HID_DEVICE_PATH IsaSerial;\r
+ UART_DEVICE_PATH Uart;\r
+ VENDOR_DEVICE_PATH TerminalType;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} PLATFORM_DUMMY_ISA_SERIAL_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH PciRootBridge;\r
+ PCI_DEVICE_PATH VgaDevice;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} PLATFORM_DUMMY_PCI_VGA_DEVICE_PATH;\r
+\r
+typedef struct {\r
+ ACPI_HID_DEVICE_PATH PciRootBridge;\r
+ PCI_DEVICE_PATH PciBridge;\r
+ PCI_DEVICE_PATH SerialDevice;\r
+ UART_DEVICE_PATH Uart;\r
+ VENDOR_DEVICE_PATH TerminalType;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} PLATFORM_DUMMY_PCI_SERIAL_DEVICE_PATH;\r
+\r
+//\r
+// the short form device path for Usb keyboard\r
+//\r
+#define CLASS_HID 3\r
+#define SUBCLASS_BOOT 1\r
+#define PROTOCOL_KEYBOARD 1\r
+\r
+typedef struct {\r
+ USB_CLASS_DEVICE_PATH UsbClass;\r
+ EFI_DEVICE_PATH_PROTOCOL End;\r
+} USB_CLASS_FORMAT_DEVICE_PATH; \r
+\r
+extern PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0;\r
+\r
+//\r
+// Platform BDS Functions\r
+//\r
+\r
+VOID\r
+PlatformBdsGetDriverOption (\r
+ IN LIST_ENTRY *BdsDriverLists\r
+ );\r
+\r
+EFI_STATUS\r
+BdsMemoryTest (\r
+ EXTENDMEM_COVERAGE_LEVEL Level\r
+ );\r
+\r
+EFI_STATUS\r
+PlatformBdsShowProgress (\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleForeground,\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL TitleBackground,\r
+ CHAR16 *Title,\r
+ EFI_GRAPHICS_OUTPUT_BLT_PIXEL ProgressColor,\r
+ UINTN Progress,\r
+ UINTN PreviousValue\r
+ );\r
+\r
+VOID\r
+PlatformBdsConnectSequence (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+ProcessCapsules (\r
+ EFI_BOOT_MODE BootMode\r
+ );\r
+\r
+EFI_STATUS\r
+PlatformBdsConnectConsole (\r
+ IN BDS_CONSOLE_CONNECT_ENTRY *PlatformConsole\r
+ );\r
+\r
+EFI_STATUS\r
+PlatformBdsNoConsoleAction (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+ConvertMpsTable (\r
+ IN OUT VOID **Table\r
+ );\r
+ \r
+EFI_STATUS\r
+ConvertSmbiosTable (\r
+ IN OUT VOID **Table\r
+ );\r
+ \r
+EFI_STATUS\r
+ConvertAcpiTable (\r
+ IN UINTN TableLen,\r
+ IN OUT VOID **Table\r
+ );\r
+\r
+EFI_STATUS\r
+ConvertSystemTable (\r
+ IN EFI_GUID *TableGuid,\r
+ IN OUT VOID **Table\r
+ );\r
+\r
+VOID\r
+PlatformBdsEnterFrontPage (\r
+ IN UINT16 TimeoutDefault,\r
+ IN BOOLEAN ConnectAllHappened\r
+ );\r
+\r
+#endif // _PLATFORM_SPECIFIC_BDS_PLATFORM_H_\r
--- /dev/null
+#/** @file\r
+# Platform BDS customizations library.\r
+#\r
+# Copyright (c) 2007 - 2008, Intel Corporation. <BR>\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+# \r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformBdsLib\r
+ FILE_GUID = 143B5044-7C1B-4904-9778-EA16F1F3D554\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PlatformBdsLib|DXE_DRIVER \r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x0002000A\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+ BdsPlatform.c\r
+ PlatformData.c\r
+ BdsPlatform.h\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ IntelFrameworkModulePkg/IntelFrameworkModulePkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ MemoryAllocationLib\r
+ UefiBootServicesTableLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ PcdLib\r
+ GenericBdsLib\r
+ PciLib\r
+\r
+[Guids]\r
+ gEfiDefaultBmpLogoGuid\r
+\r
+[Pcd.common]\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut\r
+\r
+[Pcd.IA32, Pcd.X64]\r
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock\r
+\r
--- /dev/null
+/** @file\r
+ Defined the platform specific device path which will be used by\r
+ platform Bbd to perform the platform policy connect.\r
+\r
+ Copyright (c) 2004 - 2008, Intel Corporation. <BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "BdsPlatform.h"\r
+\r
+//\r
+// Predefined platform default time out value\r
+//\r
+UINT16 gPlatformBootTimeOutDefault = 5;\r
+\r
+ACPI_HID_DEVICE_PATH gPnpPs2KeyboardDeviceNode = gPnpPs2Keyboard;\r
+ACPI_HID_DEVICE_PATH gPnp16550ComPortDeviceNode = gPnp16550ComPort;\r
+UART_DEVICE_PATH gUartDeviceNode = gUart;\r
+VENDOR_DEVICE_PATH gTerminalTypeDeviceNode = gPcAnsiTerminal;\r
+\r
+//\r
+// Predefined platform root bridge\r
+//\r
+PLATFORM_ROOT_BRIDGE_DEVICE_PATH gPlatformRootBridge0 = {\r
+ gPciRootBridge,\r
+ gEndEntire\r
+};\r
+\r
+EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges[] = {\r
+ (EFI_DEVICE_PATH_PROTOCOL *) &gPlatformRootBridge0,\r
+ NULL\r
+};\r
+\r
+//\r
+// Platform specific keyboard device path\r
+//\r
+\r
+//\r
+// Predefined platform default console device path\r
+//\r
+BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = {\r
+ {\r
+ NULL,\r
+ 0\r
+ }\r
+};\r
+\r
+//\r
+// Predefined platform specific driver option\r
+//\r
+EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption[] = { NULL };\r
+\r
+//\r
+// Predefined platform connect sequence\r
+//\r
+EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[] = { NULL };\r
+\r
--- /dev/null
+#/** @file\r
+# EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# \r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ DEC_VERSION = 0x00010005\r
+ PACKAGE_NAME = OvmfPkg\r
+ PACKAGE_GUID = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5\r
+ PACKAGE_VERSION = 0.1\r
+\r
+[Guids.common]\r
+ gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x0000100e\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x0000100f\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoveryBase|0x0|UINT32|0x00001010\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoverySize|0x0|UINT32|0x00001011\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0x00001012\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0x00001013\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0x00001014\r
+\r
+\r
--- /dev/null
+#/** @file\r
+# Open Virtual Machine Firmware: FDF\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+[FD.OVMF]\r
+BaseAddress = 0xFFE00000 # The base address of the FLASH Device.\r
+Size = 0x00200000 # The size in bytes of the FLASH Device\r
+ErasePolarity = 1\r
+BlockSize = 0x10000\r
+NumBlocks = 0x20\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+0x0|0x200000\r
+gEfiUnixPkgTokenSpaceGuid.PcdUnixFlashFvRecoveryBase|gEfiUnixPkgTokenSpaceGuid.PcdUnixFlashFvRecoverySize\r
+FV = MAINFV\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.DXEFV]\r
+BlockSize = 0x1000\r
+FvAlignment = 16 #FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+#\r
+# Files to be placed in DXEFV\r
+#\r
+# This firmware volume will have files placed in it uncompressed,\r
+# and then then entire firmware volume will be compressed in a\r
+# single compression operation in order to achieve better\r
+# overall compression.\r
+#\r
+\r
+APRIORI DXE {\r
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+ INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf\r
+}\r
+\r
+#\r
+# DXE Phase modules\r
+#\r
+INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+\r
+INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+\r
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf\r
+INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf\r
+INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf\r
+INF UefiCpuPkg/CpuIoDxe/CpuIo.inf\r
+INF UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+INF PcAtChipsetPkg/8254TimerDxe/8254Timer.inf\r
+INF PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+INF PcAtChipsetPkg/KbcResetDxe/Reset.inf\r
+INF MdeModulePkg/Universal/Metronome/Metronome.inf\r
+INF PcAtChipsetPkg/PcRtc/RealTimeClock.inf\r
+\r
+INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf\r
+INF PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf\r
+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+\r
+INF OptionRomPkg/CirrusLogic5430Dxe/CirrusLogic5430Dxe.inf\r
+\r
+INF PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf\r
+INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/IsaFloppyDxe.inf\r
+\r
+INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf\r
+INF RuleOverride=ACPITABLE OvmfPkg/AcpiTables/AcpiTables.inf\r
+\r
+INF FatBinPkg/EnhancedFatDxe/Fat.inf\r
+\r
+INF EdkShellBinPkg/FullShell/FullShell.inf\r
+\r
+FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { # LzmaCompress\r
+ SECTION RAW = MdeModulePkg/Logo/Logo.bmp\r
+ }\r
+ }\r
+\r
+################################################################################\r
+\r
+[FV.MAINFV]\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+#\r
+# Files to be placed in MAINFV\r
+#\r
+# This firmware volume will have all the files placed in it which\r
+# must not be compressed at the initial boot phase. The only\r
+# exception to this is the compressed 'DXEFV'.\r
+#\r
+\r
+APRIORI PEI {\r
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+}\r
+\r
+#\r
+# SEC Phase modules\r
+#\r
+INF OvmfPkg/Sec/SecMain.inf\r
+\r
+#\r
+# PEI Phase modules\r
+#\r
+INF MdeModulePkg/Core/Pei/PeiMain.inf\r
+INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+INF OvmfPkg/PlatformPei/PlatformPei.inf\r
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+#\r
+# This file contains the compressed 'DXEFV', which is compressed\r
+# in a single compression operation in order to achieve better\r
+# overall compression.\r
+#\r
+FILE FV_IMAGE = 20bc8ac9-94d1-4208-ab28-5d673fd73486 {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { # LzmaCompress\r
+ SECTION FV_IMAGE = DXEFV\r
+ }\r
+ }\r
+\r
+INF RuleOverride=RESET_VECTOR OvmfPkg/ResetVector/Bin/ResetVector.inf\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.PEIM.TIANOCOMPRESSED]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional |.depex\r
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER.ACPITABLE]\r
+ FILE FREEFORM = $(NAMED_GUID) {\r
+ RAW ACPI |.acpi\r
+ RAW ASL |.aml\r
+ }\r
+\r
+[Rule.Common.SEC.RESET_VECTOR]\r
+ FILE RAW = $(NAMED_GUID) {\r
+ RAW RAW |.raw\r
+ }\r
+\r
--- /dev/null
+#/** @file\r
+# EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = Ovmf\r
+ PLATFORM_GUID = 5a9e7754-d81b-49ea-85ad-69eaa7b1539b\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_ SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/OvmfIa32\r
+ SUPPORTED_ARCHITECTURES = IA32\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = OvmfPkg/OvmfPkg.fdf\r
+\r
+################################################################################\r
+#\r
+# SKU Identification section - list of all SKU IDs supported by this Platform.\r
+#\r
+################################################################################\r
+[SkuIds]\r
+ 0|DEFAULT\r
+\r
+################################################################################\r
+#\r
+# Library Class section - list of all Library Classes needed by this Platform.\r
+#\r
+################################################################################\r
+[LibraryClasses.common]\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf\r
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+ PciIncompatibleDeviceSupportLib|IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf\r
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf\r
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
+ S3Lib|MdeModulePkg/Library/PeiS3LibNull/PeiS3LibNull.inf\r
+ RecoveryLib|MdeModulePkg/Library/PeiRecoveryLibNull/PeiRecoveryLibNull.inf\r
+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+ OemHookStatusCodeLib|IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf\r
+ MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf\r
+\r
+[LibraryClasses.common.SEC]\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+\r
+[LibraryClasses.common.PEI_CORE]\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+\r
+[LibraryClasses.common.PEIM]\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.DXE_CORE]\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/SmmRuntimeDxeReportStatusCodeLibFramework/SmmRuntimeDxeReportStatusCodeLibFramework.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+\r
+[LibraryClasses.common.UEFI_DRIVER]\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf\r
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf\r
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf\r
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf\r
+ PlatformBdsLib|OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.\r
+#\r
+################################################################################\r
+[PcdsFeatureFlag.common]\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseHardSerial|TRUE\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1\r
+ gEfiSioTokenSpaceGuid.PcdSerialRegisterBase|0x3F8\r
+ gEfiSioTokenSpaceGuid.PcdSerialLineControl|0x07\r
+ gEfiSioTokenSpaceGuid.PcdSerialBoudRate|115200\r
+\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x200000\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0x10000\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoveryBase|0xFFE00000\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoverySize|0x00200000\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|6\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|32\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x10000\r
+\r
+ gEfiEdkModulePkgTokenSpaceGuid.PcdDxePcdDatabaseTraverseEnabled|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0\r
+\r
+[PcdsFeatureFlag.common]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE\r
+ gOptionRomPkgTokenSpaceGuid.PcdSupportGop|TRUE\r
+ gOptionRomPkgTokenSpaceGuid.PcdSupportUga|FALSE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F\r
+\r
+[PcdsDynamicDefault.common.DEFAULT]\r
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|0\r
+\r
+################################################################################\r
+#\r
+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsDynamicDefault.common.DEFAULT]\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform.\r
+#\r
+################################################################################\r
+[Components.common]\r
+ #\r
+ # SEC Phase modules\r
+ #\r
+ OvmfPkg/Sec/SecMain.inf\r
+\r
+ #\r
+ # PEI Phase modules\r
+ #\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+ OvmfPkg/PlatformPei/PlatformPei.inf\r
+\r
+ #\r
+ # DXE Phase modules\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+\r
+ IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf\r
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf\r
+ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf\r
+ PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf\r
+ UefiCpuPkg/CpuIoDxe/CpuIo.inf\r
+ UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+ PcAtChipsetPkg/8254TimerDxe/8254Timer.inf\r
+ PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+ PcAtChipsetPkg/KbcResetDxe/Reset.inf\r
+ MdeModulePkg/Universal/Metronome/Metronome.inf {\r
+ <LibraryClasses>\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ }\r
+\r
+ PcAtChipsetPkg/PcRtc/RealTimeClock.inf {\r
+ <LibraryClasses>\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ }\r
+\r
+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf {\r
+ <LibraryClasses>\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ }\r
+\r
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf\r
+ PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+\r
+ OptionRomPkg/CirrusLogic5430Dxe/CirrusLogic5430Dxe.inf\r
+\r
+ #\r
+ # ISA Support\r
+ #\r
+ PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/IsaFloppyDxe.inf\r
+\r
+ #\r
+ # ACPI Support\r
+ #\r
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf\r
+ OvmfPkg/AcpiTables/AcpiTables.inf\r
+\r
--- /dev/null
+#/** @file\r
+# EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = Ovmf\r
+ PLATFORM_GUID = 5a9e7754-d81b-49ea-85ad-69eaa7b1539b\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_ SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/Ovmf3264\r
+ SUPPORTED_ARCHITECTURES = IA32|X64\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = OvmfPkg/OvmfPkgIa32X64.fdf\r
+\r
+################################################################################\r
+#\r
+# SKU Identification section - list of all SKU IDs supported by this Platform.\r
+#\r
+################################################################################\r
+[SkuIds]\r
+ 0|DEFAULT\r
+\r
+################################################################################\r
+#\r
+# Library Class section - list of all Library Classes needed by this Platform.\r
+#\r
+################################################################################\r
+[LibraryClasses.common]\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf\r
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+ PciIncompatibleDeviceSupportLib|IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf\r
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf\r
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
+ S3Lib|MdeModulePkg/Library/PeiS3LibNull/PeiS3LibNull.inf\r
+ RecoveryLib|MdeModulePkg/Library/PeiRecoveryLibNull/PeiRecoveryLibNull.inf\r
+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+ OemHookStatusCodeLib|IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf\r
+ MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf\r
+\r
+[LibraryClasses.common.SEC]\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+\r
+[LibraryClasses.common.PEI_CORE]\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+\r
+[LibraryClasses.common.PEIM]\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.DXE_CORE]\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/SmmRuntimeDxeReportStatusCodeLibFramework/SmmRuntimeDxeReportStatusCodeLibFramework.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+\r
+[LibraryClasses.common.UEFI_DRIVER]\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf\r
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf\r
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf\r
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf\r
+ PlatformBdsLib|OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.\r
+#\r
+################################################################################\r
+[PcdsFeatureFlag.common]\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseHardSerial|TRUE\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1\r
+ gEfiSioTokenSpaceGuid.PcdSerialRegisterBase|0x3F8\r
+ gEfiSioTokenSpaceGuid.PcdSerialLineControl|0x07\r
+ gEfiSioTokenSpaceGuid.PcdSerialBoudRate|115200\r
+\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x200000\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0x10000\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoveryBase|0xFFE00000\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoverySize|0x00200000\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|6\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|32\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x10000\r
+\r
+ gEfiEdkModulePkgTokenSpaceGuid.PcdDxePcdDatabaseTraverseEnabled|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0\r
+\r
+[PcdsFeatureFlag.common]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|TRUE\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE\r
+ gOptionRomPkgTokenSpaceGuid.PcdSupportGop|TRUE\r
+ gOptionRomPkgTokenSpaceGuid.PcdSupportUga|FALSE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F\r
+\r
+[PcdsDynamicDefault.common.DEFAULT]\r
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|0\r
+\r
+################################################################################\r
+#\r
+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsDynamicDefault.common.DEFAULT]\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform.\r
+#\r
+################################################################################\r
+[Components.IA32]\r
+ #\r
+ # SEC Phase modules\r
+ #\r
+ OvmfPkg/Sec/SecMain.inf\r
+\r
+ #\r
+ # PEI Phase modules\r
+ #\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+ OvmfPkg/PlatformPei/PlatformPei.inf\r
+\r
+[Components.X64]\r
+ #\r
+ # DXE Phase modules\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+\r
+ IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf\r
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf\r
+ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf\r
+ PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf\r
+ UefiCpuPkg/CpuIoDxe/CpuIo.inf\r
+ UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+ PcAtChipsetPkg/8254TimerDxe/8254Timer.inf\r
+ PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+ PcAtChipsetPkg/KbcResetDxe/Reset.inf\r
+ MdeModulePkg/Universal/Metronome/Metronome.inf {\r
+ <LibraryClasses>\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ }\r
+\r
+ PcAtChipsetPkg/PcRtc/RealTimeClock.inf {\r
+ <LibraryClasses>\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ }\r
+\r
+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf {\r
+ <LibraryClasses>\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ }\r
+\r
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf\r
+ PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+\r
+ OptionRomPkg/CirrusLogic5430Dxe/CirrusLogic5430Dxe.inf\r
+\r
+ #\r
+ # ISA Support\r
+ #\r
+ PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/IsaFloppyDxe.inf\r
+\r
+ #\r
+ # ACPI Support\r
+ #\r
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf\r
+ OvmfPkg/AcpiTables/AcpiTables.inf\r
+\r
--- /dev/null
+#/** @file\r
+# Open Virtual Machine Firmware: FDF\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+################################################################################\r
+#\r
+# FD Section\r
+# The [FD] Section is made up of the definition statements and a\r
+# description of what goes into the Flash Device Image. Each FD section\r
+# defines one flash "device" image. A flash device image may be one of\r
+# the following: Removable media bootable image (like a boot floppy\r
+# image,) an Option ROM image (that would be "flashed" into an add-in\r
+# card,) a System "Flash" image (that would be burned into a system's\r
+# flash) or an Update ("Capsule") image that will be used to update and\r
+# existing system flash.\r
+#\r
+################################################################################\r
+[FD.OVMF]\r
+BaseAddress = 0xFFE00000 # The base address of the FLASH Device.\r
+Size = 0x00200000 # The size in bytes of the FLASH Device\r
+ErasePolarity = 1\r
+BlockSize = 0x10000\r
+NumBlocks = 0x20\r
+\r
+################################################################################\r
+#\r
+# Following are lists of FD Region layout which correspond to the locations of different\r
+# images within the flash device.\r
+#\r
+# Regions must be defined in ascending order and may not overlap.\r
+#\r
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by\r
+# the pipe "|" character, followed by the size of the region, also in hex with the leading\r
+# "0x" characters. Like:\r
+# Offset|Size\r
+# PcdOffsetCName|PcdSizeCName\r
+# RegionType <FV, DATA, or FILE>\r
+#\r
+################################################################################\r
+0x0|0x200000\r
+gEfiUnixPkgTokenSpaceGuid.PcdUnixFlashFvRecoveryBase|gEfiUnixPkgTokenSpaceGuid.PcdUnixFlashFvRecoverySize\r
+FV = MAINFV\r
+\r
+################################################################################\r
+#\r
+# FV Section\r
+#\r
+# [FV] section is used to define what components or modules are placed within a flash\r
+# device file. This section also defines order the components and modules are positioned\r
+# within the image. The [FV] section consists of define statements, set statements and\r
+# module statements.\r
+#\r
+################################################################################\r
+[FV.DXEFV]\r
+BlockSize = 0x1000\r
+FvAlignment = 16 #FV alignment and FV attributes setting.\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+#\r
+# Files to be placed in DXEFV\r
+#\r
+# This firmware volume will have files placed in it uncompressed,\r
+# and then then entire firmware volume will be compressed in a\r
+# single compression operation in order to achieve better\r
+# overall compression.\r
+#\r
+\r
+APRIORI DXE {\r
+ INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+ INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf\r
+}\r
+\r
+#\r
+# DXE Phase modules\r
+#\r
+INF MdeModulePkg/Core/Dxe/DxeMain.inf\r
+\r
+INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf\r
+\r
+INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+INF IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf\r
+INF MdeModulePkg/Universal/EbcDxe/EbcDxe.inf\r
+INF PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf\r
+INF UefiCpuPkg/CpuIoDxe/CpuIo.inf\r
+INF UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+INF PcAtChipsetPkg/8254TimerDxe/8254Timer.inf\r
+INF PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+INF PcAtChipsetPkg/KbcResetDxe/Reset.inf\r
+INF MdeModulePkg/Universal/Metronome/Metronome.inf\r
+INF PcAtChipsetPkg/PcRtc/RealTimeClock.inf\r
+\r
+INF MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf\r
+INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+INF MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+INF MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf\r
+INF PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf\r
+INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+\r
+INF OptionRomPkg/CirrusLogic5430Dxe/CirrusLogic5430Dxe.inf\r
+\r
+INF PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf\r
+INF IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf\r
+INF IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/IsaFloppyDxe.inf\r
+\r
+INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf\r
+INF RuleOverride=ACPITABLE OvmfPkg/AcpiTables/AcpiTables.inf\r
+\r
+FILE DRIVER = 961578FE-B6B7-44c3-AF35-6BC705CD2B1F {\r
+ SECTION PE32 = FatBinPkg/EnhancedFatDxe/X64/Fat.efi\r
+ }\r
+\r
+FILE APPLICATION = c57ad6b7-0515-40a8-9d21-551652854e37 {\r
+ SECTION PE32 = EdkShellBinPkg/FullShell/X64/Shell_full.efi\r
+ }\r
+\r
+FILE FREEFORM = 7BB28B99-61BB-11D5-9A5D-0090273FC14D {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { # LzmaCompress\r
+ SECTION RAW = MdeModulePkg/Logo/Logo.bmp\r
+ }\r
+ }\r
+\r
+################################################################################\r
+\r
+[FV.MAINFV]\r
+FvAlignment = 16\r
+ERASE_POLARITY = 1\r
+MEMORY_MAPPED = TRUE\r
+STICKY_WRITE = TRUE\r
+LOCK_CAP = TRUE\r
+LOCK_STATUS = TRUE\r
+WRITE_DISABLED_CAP = TRUE\r
+WRITE_ENABLED_CAP = TRUE\r
+WRITE_STATUS = TRUE\r
+WRITE_LOCK_CAP = TRUE\r
+WRITE_LOCK_STATUS = TRUE\r
+READ_DISABLED_CAP = TRUE\r
+READ_ENABLED_CAP = TRUE\r
+READ_STATUS = TRUE\r
+READ_LOCK_CAP = TRUE\r
+READ_LOCK_STATUS = TRUE\r
+\r
+#\r
+# Files to be placed in MAINFV\r
+#\r
+# This firmware volume will have all the files placed in it which\r
+# must not be compressed at the initial boot phase. The only\r
+# exception to this is the compressed 'DXEFV'.\r
+#\r
+\r
+APRIORI PEI {\r
+ INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+}\r
+\r
+#\r
+# SEC Phase modules\r
+#\r
+INF OvmfPkg/Sec/SecMain.inf\r
+\r
+#\r
+# PEI Phase modules\r
+#\r
+INF MdeModulePkg/Core/Pei/PeiMain.inf\r
+INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf\r
+INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+INF OvmfPkg/PlatformPei/PlatformPei.inf\r
+INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf\r
+\r
+#\r
+# This file contains the compressed 'DXEFV', which is compressed\r
+# in a single compression operation in order to achieve better\r
+# overall compression.\r
+#\r
+FILE FV_IMAGE = 20bc8ac9-94d1-4208-ab28-5d673fd73486 {\r
+ SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE { # LzmaCompress\r
+ SECTION FV_IMAGE = DXEFV\r
+ }\r
+ }\r
+\r
+FILE RAW = 1BA0062E-C779-4582-8566-336AE8F78F09 {\r
+ SECTION RAW = OvmfPkg/ResetVector/Bin/ResetVector.ia32.raw\r
+ }\r
+\r
+\r
+################################################################################\r
+#\r
+# Rules are use with the [FV] section's module INF type to define\r
+# how an FFS file is created for a given INF file. The following Rule are the default\r
+# rules for the different module type. User can add the customized rules to define the\r
+# content of the FFS file.\r
+#\r
+################################################################################\r
+\r
+[Rule.Common.PEI_CORE]\r
+ FILE PEI_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.SEC]\r
+ FILE SEC = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING ="$(MODULE_NAME)" Optional\r
+ VERSION STRING ="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.PEIM]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.PEIM.TIANOCOMPRESSED]\r
+ FILE PEIM = $(NAMED_GUID) {\r
+ PEI_DEPEX PEI_DEPEX Optional |.depex\r
+ GUIDED A31280AD-481E-41B6-95E8-127F4C984779 PROCESSING_REQUIRED = TRUE {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+ }\r
+\r
+[Rule.Common.DXE_CORE]\r
+ FILE DXE_CORE = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_RUNTIME_DRIVER]\r
+ FILE DRIVER = $(NAMED_GUID) {\r
+ DXE_DEPEX DXE_DEPEX Optional |.depex\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.UEFI_APPLICATION]\r
+ FILE APPLICATION = $(NAMED_GUID) {\r
+ PE32 PE32 |.efi\r
+ UI STRING="$(MODULE_NAME)" Optional\r
+ VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)\r
+ }\r
+\r
+[Rule.Common.DXE_DRIVER.ACPITABLE]\r
+ FILE FREEFORM = $(NAMED_GUID) {\r
+ RAW ACPI |.acpi\r
+ RAW ASL |.aml\r
+ }\r
+\r
+[Rule.Common.SEC.RESET_VECTOR]\r
+ FILE RAW = $(NAMED_GUID) {\r
+ RAW RAW |.raw\r
+ }\r
+\r
--- /dev/null
+#/** @file\r
+# EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+################################################################################\r
+#\r
+# Defines Section - statements that will be processed to create a Makefile.\r
+#\r
+################################################################################\r
+[Defines]\r
+ PLATFORM_NAME = Ovmf\r
+ PLATFORM_GUID = 5a9e7754-d81b-49ea-85ad-69eaa7b1539b\r
+ PLATFORM_VERSION = 0.1\r
+ DSC_ SPECIFICATION = 0x00010005\r
+ OUTPUT_DIRECTORY = Build/OvmfX64\r
+ SUPPORTED_ARCHITECTURES = X64\r
+ BUILD_TARGETS = DEBUG|RELEASE\r
+ SKUID_IDENTIFIER = DEFAULT\r
+ FLASH_DEFINITION = OvmfPkg/OvmfPkg.fdf\r
+\r
+################################################################################\r
+#\r
+# SKU Identification section - list of all SKU IDs supported by this Platform.\r
+#\r
+################################################################################\r
+[SkuIds]\r
+ 0|DEFAULT\r
+\r
+################################################################################\r
+#\r
+# Library Class section - list of all Library Classes needed by this Platform.\r
+#\r
+################################################################################\r
+[LibraryClasses.common]\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ BaseLib|MdePkg/Library/BaseLib/BaseLib.inf\r
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf\r
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf\r
+ PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf\r
+ PciIncompatibleDeviceSupportLib|IntelFrameworkModulePkg/Library/PciIncompatibleDeviceSupportLib/PciIncompatibleDeviceSupportLib.inf\r
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf\r
+ UefiDecompressLib|MdePkg/Library/BaseUefiDecompressLib/BaseUefiDecompressLib.inf\r
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf\r
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf\r
+ S3Lib|MdeModulePkg/Library/PeiS3LibNull/PeiS3LibNull.inf\r
+ RecoveryLib|MdeModulePkg/Library/PeiRecoveryLibNull/PeiRecoveryLibNull.inf\r
+ GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf\r
+ CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf\r
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf\r
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf\r
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf\r
+ OemHookStatusCodeLib|IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ SerialPortLib|PcAtChipsetPkg/Library/SerialIoLib/SerialIoLib.inf\r
+ MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf\r
+\r
+[LibraryClasses.common.SEC]\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+\r
+[LibraryClasses.common.PEI_CORE]\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+\r
+[LibraryClasses.common.PEIM]\r
+ BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf\r
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf\r
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf\r
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf\r
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf\r
+ OemHookStatusCodeLib|IntelFrameworkModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf\r
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf\r
+ PeiResourcePublicationLib|MdePkg/Library/PeiResourcePublicationLib/PeiResourcePublicationLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.DXE_CORE]\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+\r
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/SmmRuntimeDxeReportStatusCodeLibFramework/SmmRuntimeDxeReportStatusCodeLibFramework.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+\r
+[LibraryClasses.common.UEFI_DRIVER]\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+\r
+[LibraryClasses.common.DXE_DRIVER]\r
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf\r
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf\r
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf\r
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf\r
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf\r
+ ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf\r
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf\r
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf\r
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf\r
+ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf\r
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf\r
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf\r
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf\r
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf\r
+ PlatformBdsLib|OvmfPkg/Library/PlatformBdsLib/PlatformBdsLib.inf\r
+\r
+################################################################################\r
+#\r
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform.\r
+#\r
+################################################################################\r
+[PcdsFeatureFlag.common]\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseHardSerial|TRUE\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdStatusCodeMemorySize|1\r
+ gEfiSioTokenSpaceGuid.PcdSerialRegisterBase|0x3F8\r
+ gEfiSioTokenSpaceGuid.PcdSerialLineControl|0x07\r
+ gEfiSioTokenSpaceGuid.PcdSerialBoudRate|115200\r
+\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x200000\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0x10000\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoveryBase|0xFFE00000\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoverySize|0x00200000\r
+\r
+ gEfiMdePkgTokenSpaceGuid.PcdMaximumGuidedExtractHandler|0x10\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxFvSupported|6\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeimPerFv|32\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x400\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x8000\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize|0x10000\r
+\r
+ gEfiEdkModulePkgTokenSpaceGuid.PcdDxePcdDatabaseTraverseEnabled|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0\r
+\r
+[PcdsFeatureFlag.common]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress|FALSE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE\r
+\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdConOutUgaSupport|FALSE\r
+ gOptionRomPkgTokenSpaceGuid.PcdSupportGop|TRUE\r
+ gOptionRomPkgTokenSpaceGuid.PcdSupportUga|FALSE\r
+\r
+[PcdsFixedAtBuild.common]\r
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x8000004F\r
+ gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F\r
+\r
+[PcdsDynamicDefault.common.DEFAULT]\r
+ gEfiMdePkgTokenSpaceGuid.PcdFSBClock|0\r
+\r
+################################################################################\r
+#\r
+# Pcd Dynamic Section - list of all EDK II PCD Entries defined by this Platform\r
+#\r
+################################################################################\r
+\r
+[PcdsDynamicDefault.common.DEFAULT]\r
+\r
+################################################################################\r
+#\r
+# Components Section - list of all EDK II Modules needed by this Platform.\r
+#\r
+################################################################################\r
+[Components.common]\r
+ #\r
+ # SEC Phase modules\r
+ #\r
+ OvmfPkg/Sec/SecMain.inf\r
+\r
+ #\r
+ # PEI Phase modules\r
+ #\r
+ MdeModulePkg/Core/Pei/PeiMain.inf\r
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+ IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf\r
+ MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+ OvmfPkg/PlatformPei/PlatformPei.inf\r
+\r
+ #\r
+ # DXE Phase modules\r
+ #\r
+ MdeModulePkg/Core/Dxe/DxeMain.inf {\r
+ <LibraryClasses>\r
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf\r
+ }\r
+\r
+ IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf\r
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {\r
+ <LibraryClasses>\r
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
+ }\r
+\r
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf\r
+ MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf\r
+ IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf\r
+ MdeModulePkg/Universal/EbcDxe/EbcDxe.inf\r
+ PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf\r
+ UefiCpuPkg/CpuIoDxe/CpuIo.inf\r
+ UefiCpuPkg/CpuDxe/CpuDxe.inf\r
+ PcAtChipsetPkg/8254TimerDxe/8254Timer.inf\r
+ PcAtChipsetPkg/PciHostBridgeDxe/PciHostBridgeDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf\r
+ PcAtChipsetPkg/KbcResetDxe/Reset.inf\r
+ MdeModulePkg/Universal/Metronome/Metronome.inf {\r
+ <LibraryClasses>\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ }\r
+\r
+ PcAtChipsetPkg/PcRtc/RealTimeClock.inf {\r
+ <LibraryClasses>\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ }\r
+\r
+ IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf {\r
+ <LibraryClasses>\r
+ TimerLib|OvmfPkg/Library/AcpiTimerLib/AcpiTimerLib.inf\r
+ }\r
+\r
+ MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf\r
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf\r
+ MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf\r
+ MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf\r
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf\r
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf\r
+ MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf\r
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf\r
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf\r
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf\r
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf\r
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiBusDxe/ScsiBusDxe.inf\r
+ MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Pci/IdeBusDxe/IdeBusDxe.inf\r
+ PcAtChipsetPkg/Bus/Pci/IdeControllerDxe/IdeControllerDxe.inf\r
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf\r
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf\r
+\r
+ OptionRomPkg/CirrusLogic5430Dxe/CirrusLogic5430Dxe.inf\r
+\r
+ #\r
+ # ISA Support\r
+ #\r
+ PcAtChipsetPkg/IsaAcpiDxe/IsaAcpi.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/IsaBusDxe/IsaBusDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/IsaSerialDxe/IsaSerialDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/Ps2KeyboardDxe/Ps2keyboardDxe.inf\r
+ IntelFrameworkModulePkg/Bus/Isa/IsaFloppyDxe/IsaFloppyDxe.inf\r
+\r
+ #\r
+ # ACPI Support\r
+ #\r
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf\r
+ MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf\r
+ OvmfPkg/AcpiTables/AcpiTables.inf\r
+\r
--- /dev/null
+/** @file\r
+ PC/AT CMOS access routines\r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+\r
+#include "Cmos.h"\r
+#include "Library/IoLib.h"\r
+\r
+/**\r
+ Reads 8-bits of CMOS data.\r
+\r
+ Reads the 8-bits of CMOS data at the location specified by Index.\r
+ The 8-bit read value is returned.\r
+\r
+ @param Index The CMOS location to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+CmosRead8 (\r
+ IN UINTN Index\r
+ )\r
+{\r
+ IoWrite8 (0x70, (UINT8) Index);\r
+ return IoRead8 (0x71);\r
+}\r
+\r
+\r
+/**\r
+ Writes 8-bits of CMOS data.\r
+\r
+ Writes 8-bits of CMOS data to the location specified by Index\r
+ with the value specified by Value and returns Value.\r
+\r
+ @param Index The CMOS location to write.\r
+ @param Value The value to write to CMOS.\r
+\r
+ @return The value written to CMOS.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+CmosWrite8 (\r
+ IN UINTN Index,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ IoWrite8 (0x70, (UINT8) Index);\r
+ IoWrite8 (0x71, Value);\r
+ return Value;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ PC/AT CMOS access routines\r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __CMOS_H__\r
+#define __CMOS_H__\r
+\r
+/**\r
+ Reads 8-bits of CMOS data.\r
+\r
+ Reads the 8-bits of CMOS data at the location specified by Index.\r
+ The 8-bit read value is returned.\r
+\r
+ @param Index The CMOS location to read.\r
+\r
+ @return The value read.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+CmosRead8 (\r
+ IN UINTN Index\r
+ );\r
+\r
+/**\r
+ Writes 8-bits of CMOS data.\r
+\r
+ Writes 8-bits of CMOS data to the location specified by Index\r
+ with the value specified by Value and returns Value.\r
+\r
+ @param Index The CMOS location to write.\r
+ @param Value The value to write to CMOS.\r
+\r
+ @return The value written to CMOS.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+CmosWrite8 (\r
+ IN UINTN Index,\r
+ IN UINT8 Value\r
+ );\r
+\r
+\r
+#endif\r
+\r
--- /dev/null
+/** @file\r
+ Build FV related hobs for platform.\r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PiPei.h"\r
+#include <Library/DebugLib.h>\r
+#include <Library/PeimEntryPoint.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+#include <Library/PeiServicesTablePointerLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+\r
+/**\r
+ Perform a call-back into the SEC simulator to get address of the Firmware Hub\r
+\r
+ @param FfsHeader Ffs Header availible to every PEIM\r
+ @param PeiServices General purpose services available to every PEIM.\r
+\r
+ @retval EFI_SUCCESS Platform PEI FVs were initialized successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+PeiFvInitialization (\r
+ VOID\r
+ )\r
+{\r
+ EFI_PHYSICAL_ADDRESS FdBase;\r
+\r
+ DEBUG ((EFI_D_ERROR, "Platform PEI Firmware Volume Initialization\n"));\r
+\r
+ DEBUG (\r
+ (EFI_D_ERROR, "Firmware Volume HOB: 0x%x 0x%x\n",\r
+ PcdGet32 (PcdOvmfFlashFvRecoveryBase),\r
+ PcdGet32 (PcdOvmfFlashFvRecoverySize)\r
+ )\r
+ );\r
+\r
+ FdBase = PcdGet32 (PcdOvmfFlashFvRecoveryBase) - PcdGet32 (PcdVariableStoreSize) - PcdGet32 (PcdFlashNvStorageFtwSpareSize);\r
+ BuildFvHob (PcdGet32 (PcdOvmfFlashFvRecoveryBase), PcdGet32 (PcdOvmfFlashFvRecoverySize));\r
+\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_FIRMWARE_DEVICE,\r
+ (EFI_RESOURCE_ATTRIBUTE_PRESENT | EFI_RESOURCE_ATTRIBUTE_INITIALIZED | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),\r
+ FdBase,\r
+ PcdGet32 (PcdOvmfFirmwareFdSize)\r
+ );\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/**@file\r
+ Memory Detection for Virtual Machines.\r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+Module Name:\r
+\r
+ MemDetect.c\r
+\r
+**/\r
+\r
+//\r
+// The package level header files this module uses\r
+//\r
+#include <PiPei.h>\r
+\r
+//\r
+// The Library classes this module consumes\r
+//\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PeimEntryPoint.h>\r
+#include <Library/ResourcePublicationLib.h>\r
+\r
+#include "Platform.h"\r
+#include "Cmos.h"\r
+\r
+STATIC\r
+UINTN\r
+GetSystemMemorySize (\r
+ )\r
+{\r
+ UINT8 Cmos0x34;\r
+ UINT8 Cmos0x35;\r
+\r
+ //\r
+ // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r
+ // * CMOS(0x35) is the high byte\r
+ // * CMOS(0x34) is the low byte\r
+ // * The size is specified in 64kb chunks\r
+ // * Since this is memory above 16MB, the 16MB must be added\r
+ // into the calculation to get the total memory size.\r
+ //\r
+\r
+ Cmos0x34 = (UINT8) CmosRead8 (0x34);\r
+ Cmos0x35 = (UINT8) CmosRead8 (0x35);\r
+\r
+ return ((((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
+}\r
+\r
+\r
+/**\r
+ Peform Memory Detection\r
+\r
+ @return EFI_SUCCESS The PEIM initialized successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+MemDetect (\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PHYSICAL_ADDRESS MemoryBase;\r
+ UINT64 MemorySize;\r
+ UINT64 TotalMemorySize;\r
+\r
+ DEBUG ((EFI_D_ERROR, "MemDetect called\n"));\r
+\r
+ //\r
+ // Determine total memory size available\r
+ //\r
+ TotalMemorySize = (UINT64)GetSystemMemorySize ();\r
+\r
+ MemoryBase = 0x800000;\r
+ MemorySize = TotalMemorySize - MemoryBase - 0x100000;\r
+\r
+ //\r
+ // Publish this memory to the PEI Core\r
+ //\r
+ Status = PublishSystemMemory(MemoryBase, MemorySize);\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ //\r
+ // Create memory HOBs\r
+ //\r
+ AddMemoryBaseSizeHob (MemoryBase, MemorySize);\r
+ AddMemoryRangeHob (0x100000, 0x800000);\r
+ AddMemoryRangeHob (0x000000, 0x0A0000);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/**@file\r
+ Platform PEI driver\r
+\r
+ Copyright (c) 2006 - 2009, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// The package level header files this module uses\r
+//\r
+#include <PiPei.h>\r
+\r
+//\r
+// The Library classes this module consumes\r
+//\r
+#include <Library/DebugLib.h>\r
+#include <Library/HobLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/PciLib.h>\r
+#include <Library/PeimEntryPoint.h>\r
+#include <Library/ResourcePublicationLib.h>\r
+#include <Guid/MemoryTypeInformation.h>\r
+\r
+#include "Platform.h"\r
+\r
+EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r
+ { EfiACPIMemoryNVS, 0x004 },\r
+ { EfiACPIReclaimMemory, 0x01C },\r
+ { EfiRuntimeServicesData, 0x050 },\r
+ { EfiRuntimeServicesCode, 0x020 },\r
+ { EfiBootServicesCode, 0x0F0 },\r
+ { EfiBootServicesData, 0xA00 },\r
+ { EfiMaxMemoryType, 0x000 }\r
+};\r
+\r
+\r
+VOID\r
+AddIoMemoryBaseSizeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
+ )\r
+{\r
+ STATIC EFI_RESOURCE_ATTRIBUTE_TYPE Attributes =\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED\r
+ );\r
+\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_MEMORY_MAPPED_IO,\r
+ Attributes,\r
+ MemoryBase,\r
+ MemorySize\r
+ );\r
+}\r
+\r
+\r
+VOID\r
+AddIoMemoryRangeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ EFI_PHYSICAL_ADDRESS MemoryLimit\r
+ )\r
+{\r
+ AddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
+}\r
+\r
+\r
+VOID\r
+AddMemoryBaseSizeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
+ )\r
+{\r
+ STATIC EFI_RESOURCE_ATTRIBUTE_TYPE Attributes =\r
+ (\r
+ EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
+ EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
+ EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
+ EFI_RESOURCE_ATTRIBUTE_TESTED\r
+ );\r
+\r
+ BuildResourceDescriptorHob (\r
+ EFI_RESOURCE_SYSTEM_MEMORY,\r
+ Attributes,\r
+ MemoryBase,\r
+ MemorySize\r
+ );\r
+}\r
+\r
+\r
+VOID\r
+AddMemoryRangeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ EFI_PHYSICAL_ADDRESS MemoryLimit\r
+ )\r
+{\r
+ AddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
+}\r
+\r
+\r
+VOID\r
+MemMapInitialization (\r
+ )\r
+{\r
+ //\r
+ // Create Memory Type Information HOB\r
+ //\r
+ BuildGuidDataHob (\r
+ &gEfiMemoryTypeInformationGuid,\r
+ mDefaultMemoryTypeInformation,\r
+ sizeof(mDefaultMemoryTypeInformation)\r
+ );\r
+\r
+ //\r
+ // Local APIC range\r
+ //\r
+ AddIoMemoryBaseSizeHob (0xFEC80000, 0x80000);\r
+\r
+ //\r
+ // I/O APIC range\r
+ //\r
+ AddIoMemoryBaseSizeHob (0xFEC00000, 0x80000);\r
+\r
+ //\r
+ // Video memory + Legacy BIOS region\r
+ //\r
+ AddMemoryRangeHob (0x0A0000, 0x0B0000);\r
+ AddIoMemoryRangeHob (0x0B0000, 0x100000);\r
+}\r
+\r
+\r
+VOID\r
+MiscInitialization (\r
+ )\r
+{\r
+ //\r
+ // Disable A20 Mask\r
+ //\r
+ IoWrite8 (0x92, (UINT8) (IoRead8 (0x92) | 0x02));\r
+\r
+ //\r
+ // Build the CPU hob with 36-bit addressing and 16-bits of IO space.\r
+ //\r
+ BuildCpuHob (36, 16);\r
+}\r
+\r
+\r
+/**\r
+ Perform Platform PEI initialization.\r
+\r
+ @param FileHandle Handle of the file being invoked.\r
+ @param PeiServices Describes the list of possible PEI Services.\r
+\r
+ @return EFI_SUCCESS The PEIM initialized successfully.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializePlatform (\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
+ )\r
+{\r
+ DEBUG ((EFI_D_ERROR, "Platform PEIM Loaded\n"));\r
+\r
+ MemDetect ();\r
+\r
+ PeiFvInitialization ();\r
+\r
+ MemMapInitialization ();\r
+\r
+ MiscInitialization ();\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ Platform PEI module include file.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _PLATFORM_PEI_H_INCLUDED_\r
+#define _PLATFORM_PEI_H_INCLUDED_\r
+\r
+VOID\r
+AddIoMemoryBaseSizeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
+ );\r
+\r
+VOID\r
+AddIoMemoryRangeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ EFI_PHYSICAL_ADDRESS MemoryLimit\r
+ );\r
+\r
+VOID\r
+AddMemoryBaseSizeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ UINT64 MemorySize\r
+ );\r
+\r
+VOID\r
+AddMemoryRangeHob (\r
+ EFI_PHYSICAL_ADDRESS MemoryBase,\r
+ EFI_PHYSICAL_ADDRESS MemoryLimit\r
+ );\r
+\r
+EFI_STATUS\r
+MemDetect (\r
+ VOID\r
+ );\r
+\r
+EFI_STATUS\r
+PeiFvInitialization (\r
+ VOID\r
+ );\r
+\r
+#endif // _PLATFORM_PEI_H_INCLUDED_\r
--- /dev/null
+#/** @file\r
+# Platform PEI driver\r
+#\r
+# This module provides platform specific function to detect boot mode.\r
+# Copyright (c) 2006 - 2009, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PlatformPei\r
+ FILE_GUID = 222c386d-5abc-4fb4-b124-fbb82488acf4\r
+ MODULE_TYPE = PEIM\r
+ VERSION_STRING = 1.0\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+ ENTRY_POINT = InitializePlatform\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+ Cmos.c\r
+ Fv.c\r
+ MemDetect.c\r
+ Platform.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ MdeModulePkg/MdeModulePkg.dec\r
+ OvmfPkg/OvmfPkg.dec\r
+\r
+[Guids]\r
+ gEfiMemoryTypeInformationGuid\r
+\r
+[LibraryClasses]\r
+ DebugLib\r
+ HobLib\r
+ IoLib\r
+ PeiResourcePublicationLib\r
+ PeiServicesTablePointerLib\r
+ PeimEntryPoint\r
+\r
+[FixedPcd.common]\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoveryBase\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoverySize\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdVariableStoreSize\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize\r
+\r
+[Pcd.common]\r
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase\r
+\r
+[Depex]\r
+ TRUE\r
+\r
--- /dev/null
+\r
+=== OVMF OVERVIEW ===\r
+\r
+The Open Virtual Machine Firmware (OVMF) project aims\r
+to support firmware for Virtual Machines using the edk2\r
+code base. More information can be found at:\r
+\r
+ https://edk2.tianocore.org/OVMF.html\r
+\r
+=== STATUS ===\r
+\r
+Current status: Alpha\r
+\r
+Current capabilities:\r
+* IA32 and X64 architectures\r
+* QEMU (0.9.1 or later)\r
+ - Video, keyboard, IDE, CD-ROM, serial\r
+ - Runs UEFI shell\r
+* UEFI Linux has booted (but is not stable)\r
+\r
+=== FUTURE PLANS ===\r
+\r
+* Stabilize UEFI Linux boot\r
+* Test/Stabilize UEFI Self-Certification Tests (SCT) results\r
+\r
--- /dev/null
+#/** @file\r
+# Reset Vector binary\r
+#\r
+# Copyright (c) 2006 - 2009, Intel Corporation.\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = ResetVector\r
+ FILE_GUID = 1BA0062E-C779-4582-8566-336AE8F78F09\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.1\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64\r
+#\r
+\r
+[Binaries.Ia32]\r
+ RAW|ResetVector.ia32.raw|*\r
+\r
+[Binaries.X64]\r
+ RAW|ResetVector.x64.raw|*\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; CommonMacros.inc\r
+;\r
+; Abstract:\r
+;\r
+; Common macros used in the ResetVector VTF module.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+%define ADDR16_OF(x) (0x10000 - fourGigabytes + x)\r
+%define ADDR_OF(x) (0x100000000 - fourGigabytes + x)\r
+\r
+%macro callEdx 1\r
+ mov edx, ADDR_OF(%%returnLabel)\r
+ jmp %1\r
+%%returnLabel:\r
+%endmacro\r
+\r
+%macro OneTimeCall 1\r
+ jmp %1\r
+%1 %+ OneTimerCallReturn:\r
+%endmacro\r
+\r
+%macro OneTimeCallRet 1\r
+ jmp %1 %+ OneTimerCallReturn\r
+%endmacro\r
+\r
+StartOfResetVectorCode:\r
+\r
+%define ADDR_OF_START_OF_RESET_CODE ADDR_OF(StartOfResetVectorCode)\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; 16RealTo32Flat.asm\r
+;\r
+; Abstract:\r
+;\r
+; Transition from 16 bit real mode into 32 bit flat protected mode\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+%define SEC_DEFAULT_CR0 0x40000023\r
+%define SEC_DEFAULT_CR4 0x640\r
+\r
+BITS 16\r
+\r
+to32BitFlat:\r
+\r
+ writeToSerialPort '1'\r
+ writeToSerialPort '6'\r
+ writeToSerialPort ' '\r
+\r
+ cli\r
+\r
+ mov bx, 0xf000\r
+ mov ds, bx\r
+\r
+ mov bx, ADDR16_OF(gdtr)\r
+\r
+o32 lgdt [bx]\r
+\r
+ mov eax, SEC_DEFAULT_CR0\r
+ mov cr0, eax\r
+\r
+; mov eax, cr0\r
+; or al, 1\r
+; mov cr0, eax\r
+\r
+ jmp LINEAR_CODE_SEL:dword ADDR_OF(jumpTo32BitAndLandHere)\r
+BITS 32\r
+jumpTo32BitAndLandHere:\r
+\r
+ mov eax, SEC_DEFAULT_CR4\r
+ mov cr4, eax\r
+\r
+ writeToSerialPort '3'\r
+ writeToSerialPort '2'\r
+ writeToSerialPort ' '\r
+\r
+ mov ax, LINEAR_SEL\r
+ mov ds, ax\r
+ mov es, ax\r
+ mov fs, ax\r
+ mov gs, ax\r
+ mov ss, ax\r
+\r
+ jmp TransitionFrom16RealTo32FlatComplete\r
+\r
+ALIGN 2\r
+\r
+gdtr:\r
+ dw GDT_END - GDT_BASE - 1 ; GDT limit\r
+ dd ADDR_OF(GDT_BASE)\r
+\r
+ALIGN 16\r
+\r
+GDT_BASE:\r
+; null descriptor\r
+NULL_SEL equ $-GDT_BASE\r
+ dw 0 ; limit 15:0\r
+ dw 0 ; base 15:0\r
+ db 0 ; base 23:16\r
+ db 0 ; type\r
+ db 0 ; limit 19:16, flags\r
+ db 0 ; base 31:24\r
+\r
+; linear data segment descriptor\r
+LINEAR_SEL equ $-GDT_BASE\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 092h ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
+\r
+; linear code segment descriptor\r
+LINEAR_CODE_SEL equ $-GDT_BASE\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 09Ah ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
+\r
+; system data segment descriptor\r
+SYS_DATA_SEL equ $-GDT_BASE\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 092h ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
+\r
+; system code segment descriptor\r
+SYS_CODE_SEL equ $-GDT_BASE\r
+ dw 0FFFFh ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 09Ah ; present, ring 0, data, expand-up, writable\r
+ db 0CFh ; page-granular, 32-bit\r
+ db 0\r
+\r
+; spare segment descriptor\r
+LINEAR_CODE64_SEL equ $-GDT_BASE\r
+ DW -1 ; LimitLow\r
+ DW 0 ; BaseLow\r
+ DB 0 ; BaseMid\r
+ DB 9bh\r
+ DB 0afh ; LimitHigh (CS.L=1, CS.D=0)\r
+ DB 0 ; BaseHigh\r
+\r
+; spare segment descriptor\r
+SPARE4_SEL equ $-GDT_BASE\r
+ dw 0 ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 0 ; present, ring 0, data, expand-up, writable\r
+ db 0 ; page-granular, 32-bit\r
+ db 0\r
+\r
+; spare segment descriptor\r
+SPARE5_SEL equ $-GDT_BASE\r
+ dw 0 ; limit 0xFFFFF\r
+ dw 0 ; base 0\r
+ db 0\r
+ db 0 ; present, ring 0, data, expand-up, writable\r
+ db 0 ; page-granular, 32-bit\r
+ db 0\r
+\r
+GDT_END:\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Reset-16Bit-old-tools.asm\r
+;\r
+; Abstract:\r
+;\r
+; First code exectuted by processor after resetting.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 16\r
+\r
+earlyInit_Real16:\r
+\r
+ jmp real16InitSerialPort\r
+real16SerialPortInitReturn:\r
+\r
+ jmp to32BitFlat\r
+\r
+ALIGN 16\r
+\r
+;\r
+; Junk data. Old GenFv tool will modify data here.\r
+;\r
+ DQ 0, 0\r
+\r
+;\r
+; Reset Vector\r
+;\r
+; This is where the processor will begin execution\r
+;\r
+ jmp short earlyInit_Real16\r
+\r
+;\r
+; Junk data. Old GenFv tool will modify data here.\r
+;\r
+ALIGN 16\r
+\r
+fourGigabytes:\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; Reset-16Bit-vft0.asm\r
+;\r
+; Abstract:\r
+;\r
+; First code exectuted by processor after resetting.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 16\r
+\r
+earlyInit_Real16:\r
+\r
+ jmp real16InitSerialPort\r
+real16SerialPortInitReturn:\r
+\r
+ jmp to32BitFlat\r
+\r
+ALIGN 16\r
+\r
+ DD 0, 0, 0\r
+\r
+;\r
+; The VTF signature\r
+;\r
+; VTF-0 means that the VTF (Volume Top File) code does not require\r
+; any fixups.\r
+;\r
+vtfSignature:\r
+ DB 'V', 'T', 'F', 0\r
+\r
+;\r
+; Reset Vector\r
+;\r
+; This is where the processor will begin execution\r
+;\r
+ jmp short earlyInit_Real16\r
+\r
+ALIGN 16\r
+\r
+fourGigabytes:\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; 32FlatTo64Flat.asm\r
+;\r
+; Abstract:\r
+;\r
+; Transition from 32 bit flat protected mode into 64 bit flat protected mode\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 32\r
+\r
+Transition32FlatTo64Flat:\r
+\r
+ mov eax, ((ADDR_OF_START_OF_RESET_CODE & ~0xfff) - 0x1000)\r
+ mov cr3, eax\r
+\r
+ mov eax, cr4\r
+ bts eax, 5 ; enable PAE\r
+ mov cr4, eax \r
+\r
+ mov ecx, 0xc0000080\r
+ rdmsr\r
+ bts eax, 8 ; set LME\r
+ wrmsr\r
+\r
+ mov eax, cr0\r
+ bts eax, 31 ; set PG\r
+ mov cr0, eax ; enable paging\r
+\r
+ jmp LINEAR_CODE64_SEL:ADDR_OF(jumpTo64BitAndLandHere)\r
+BITS 64\r
+jumpTo64BitAndLandHere:\r
+\r
+ writeToSerialPort '6'\r
+ writeToSerialPort '4'\r
+ writeToSerialPort ' '\r
+\r
+ OneTimeCallRet Transition32FlatTo64Flat\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; SearchForBfvBase.asm\r
+;\r
+; Abstract:\r
+;\r
+; Search for the Boot FV Base Address\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+;#define EFI_FIRMWARE_FILE_SYSTEM2_GUID \\r
+; { 0x8c8ce578, 0x8a3d, 0x4f1c, { 0x99, 0x35, 0x89, 0x61, 0x85, 0xc3, 0x2d, 0xd3 } }\r
+%define FFS_GUID_DWORD0 0x8c8ce578\r
+%define FFS_GUID_DWORD1 0x4f1c8a3d\r
+%define FFS_GUID_DWORD2 0x61893599\r
+%define FFS_GUID_DWORD3 0xd32dc385\r
+\r
+BITS 32\r
+\r
+;\r
+; Input:\r
+; None\r
+;\r
+; Output:\r
+; EBP - BFV Base Address\r
+;\r
+; Modified:\r
+; EAX, EBX\r
+;\r
+Flat32SearchForBfvBase:\r
+\r
+ xor eax, eax\r
+searchingForBfvHeaderLoop:\r
+ sub eax, 0x1000\r
+ cmp eax, 0xff800000\r
+ jb searchedForBfvHeaderButNotFound\r
+\r
+ ;\r
+ ; Check FFS GUID\r
+ ;\r
+ cmp dword [eax + 0x10], FFS_GUID_DWORD0\r
+ jne searchingForBfvHeaderLoop\r
+ cmp dword [eax + 0x14], FFS_GUID_DWORD1\r
+ jne searchingForBfvHeaderLoop\r
+ cmp dword [eax + 0x18], FFS_GUID_DWORD2\r
+ jne searchingForBfvHeaderLoop\r
+ cmp dword [eax + 0x1c], FFS_GUID_DWORD3\r
+ jne searchingForBfvHeaderLoop\r
+\r
+ ;\r
+ ; Check FV Length\r
+ ;\r
+ cmp dword [eax + 0x24], 0\r
+ jne searchingForBfvHeaderLoop\r
+ mov ebx, eax\r
+ add ebx, dword [eax + 0x20]\r
+ jnz searchingForBfvHeaderLoop\r
+\r
+ jmp searchedForBfvHeaderAndItWasFound\r
+\r
+searchedForBfvHeaderButNotFound:\r
+ writeToSerialPort '!'\r
+ xor eax, eax\r
+\r
+searchedForBfvHeaderAndItWasFound:\r
+ mov ebp, eax\r
+\r
+ writeToSerialPort 'B'\r
+ writeToSerialPort 'F'\r
+ writeToSerialPort 'V'\r
+ writeToSerialPort ' '\r
+\r
+ or ebp, ebp\r
+ jz $\r
+\r
+ OneTimeCallRet Flat32SearchForBfvBase\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; SearchForSecAndPeiEntry.asm\r
+;\r
+; Abstract:\r
+;\r
+; Search for the SEC Core and PEI Core entry points\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 32\r
+\r
+%define EFI_FV_FILETYPE_SECURITY_CORE 0x03\r
+%define EFI_FV_FILETYPE_PEI_CORE 0x04\r
+\r
+;\r
+; Input:\r
+; EBP - BFV Base Address\r
+;\r
+; Output:\r
+; ESI - SEC Core Entry Point Address (or 0 if not found)\r
+; EDI - PEI Core Entry Point Address (or 0 if not found)\r
+;\r
+; Modified:\r
+; EAX, EBX, ECX\r
+;\r
+Flat32SearchForSecAndPeiEntries:\r
+\r
+ ;\r
+ ; Initialize EBP and ESI to 0\r
+ ;\r
+ xor ebx, ebx\r
+ mov esi, ebx\r
+ mov edi, ebx\r
+\r
+ ;\r
+ ; Pass over the BFV header\r
+ ;\r
+ mov eax, ebp\r
+ mov bx, [ebp + 0x30]\r
+ add eax, ebx\r
+ jc doneSeachingForSecAndPeiEntries\r
+\r
+ jmp searchingForFfsFileHeaderLoop\r
+\r
+moveForwardWhileSearchingForFfsFileHeaderLoop:\r
+ ;\r
+ ; Make forward progress in the search\r
+ ;\r
+ inc eax\r
+ jc doneSeachingForSecAndPeiEntries\r
+\r
+searchingForFfsFileHeaderLoop:\r
+ test eax, eax\r
+ jz doneSeachingForSecAndPeiEntries\r
+\r
+ ;\r
+ ; Ensure 8 byte alignment\r
+ ;\r
+ add eax, 7\r
+ jc doneSeachingForSecAndPeiEntries\r
+ and al, 0xf8\r
+\r
+ ;\r
+ ; Look to see if there is an FFS file at eax\r
+ ;\r
+ mov bl, [eax + 0x17]\r
+ test bl, 0x20\r
+ jz moveForwardWhileSearchingForFfsFileHeaderLoop\r
+ mov ecx, [eax + 0x14]\r
+ and ecx, 0x00ffffff\r
+ or ecx, ecx\r
+ jz moveForwardWhileSearchingForFfsFileHeaderLoop\r
+; jmp $\r
+ add ecx, eax\r
+ jz jumpSinceWeFoundTheLastFfsFile\r
+ jc moveForwardWhileSearchingForFfsFileHeaderLoop\r
+jumpSinceWeFoundTheLastFfsFile:\r
+\r
+ ;\r
+ ; There seems to be a valid file at eax\r
+ ;\r
+ mov bl, [eax + 0x12] ; BL - File Type\r
+ cmp bl, EFI_FV_FILETYPE_PEI_CORE\r
+ je fileTypeIsPeiCore\r
+ cmp bl, EFI_FV_FILETYPE_SECURITY_CORE\r
+ jne readyToTryFfsFileAtEcx\r
+\r
+fileTypeIsSecCore:\r
+ callEdx GetEntryPointOfFfsFileReturnEdx\r
+ test eax, eax\r
+ jz readyToTryFfsFileAtEcx\r
+\r
+ mov esi, eax\r
+ jmp readyToTryFfsFileAtEcx\r
+\r
+fileTypeIsPeiCore:\r
+ callEdx GetEntryPointOfFfsFileReturnEdx\r
+ test eax, eax\r
+ jz readyToTryFfsFileAtEcx\r
+\r
+ mov edi, eax\r
+\r
+readyToTryFfsFileAtEcx:\r
+ mov eax, ecx\r
+ jmp searchingForFfsFileHeaderLoop\r
+\r
+doneSeachingForSecAndPeiEntries:\r
+\r
+ test esi, esi\r
+ jnz secCoreEntryPointWasFound\r
+ writeToSerialPort '!'\r
+secCoreEntryPointWasFound:\r
+ writeToSerialPort 'S'\r
+ writeToSerialPort 'E'\r
+ writeToSerialPort 'C'\r
+ writeToSerialPort ' '\r
+\r
+ test edi, edi\r
+ jnz peiCoreEntryPointWasFound\r
+ writeToSerialPort '!'\r
+peiCoreEntryPointWasFound:\r
+ writeToSerialPort 'P'\r
+ writeToSerialPort 'E'\r
+ writeToSerialPort 'I'\r
+ writeToSerialPort ' '\r
+\r
+ OneTimeCallRet Flat32SearchForSecAndPeiEntries\r
+\r
+\r
+%define EFI_SECTION_PE32 0x10\r
+\r
+;\r
+; Input:\r
+; EAX - Start of FFS file\r
+;\r
+; Output:\r
+; EAX - Entry point of PE32 (or 0 if not found)\r
+;\r
+; Modified:\r
+; EBX\r
+;\r
+GetEntryPointOfFfsFileReturnEdx:\r
+ test eax, eax\r
+ jz getEntryPointOfFfsFileErrorReturn\r
+\r
+ cmp byte [eax + 0x1b], EFI_SECTION_PE32\r
+ jne getEntryPointOfFfsFileErrorReturn\r
+\r
+ add eax, 0x1c ; EAX = Start of PE32 image\r
+\r
+ mov ebx, eax\r
+ cmp word [eax], 'MZ'\r
+ jne thereIsNotAnMzSignature\r
+ movzx ebx, word [eax + 0x3c]\r
+ add ebx, eax\r
+thereIsNotAnMzSignature:\r
+\r
+ ; if (Hdr.Te->Signature == EFI_TE_IMAGE_HEADER_SIGNATURE)\r
+ cmp word [ebx], 'VZ'\r
+ jne thereIsNoVzSignature\r
+ ; *EntryPoint = (VOID *)((UINTN)Pe32Data +\r
+ ; (UINTN)(Hdr.Te->AddressOfEntryPoint & 0x0ffffffff) +\r
+ ; sizeof(EFI_TE_IMAGE_HEADER) - Hdr.Te->StrippedSize);\r
+ add eax, [ebx + 0x8]\r
+ add eax, 0x28\r
+ movzx ebx, word [ebx + 0x6]\r
+ sub eax, ebx\r
+ jmp getEntryPointOfFfsFileReturn\r
+\r
+thereIsNoVzSignature:\r
+\r
+ ; if (Hdr.Pe32->Signature == EFI_IMAGE_NT_SIGNATURE)\r
+ cmp dword [ebx], `PE\x00\x00`\r
+ jne getEntryPointOfFfsFileErrorReturn\r
+\r
+ ; *EntryPoint = (VOID *)((UINTN)Pe32Data +\r
+ ; (UINTN)(Hdr.Pe32->OptionalHeader.AddressOfEntryPoint & 0x0ffffffff));\r
+ add eax, [ebx + 0x4 + 0x14 + 0x10]\r
+ jmp getEntryPointOfFfsFileReturn\r
+\r
+getEntryPointOfFfsFileErrorReturn:\r
+ mov eax, 0\r
+\r
+getEntryPointOfFfsFileReturn:\r
+ jmp edx\r
+\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; JumpToSec.asm\r
+;\r
+; Abstract:\r
+;\r
+; Jump from the reset vector binary to SEC\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 32\r
+\r
+TransitionFrom16RealTo32FlatComplete:\r
+\r
+ OneTimeCall Flat32SearchForBfvBase\r
+\r
+ OneTimeCall Flat32SearchForSecAndPeiEntries\r
+\r
+ ;\r
+ ; ESI - SEC Core entry point\r
+ ; EDI - PEI Core entry point\r
+ ; EBP - Start of BFV\r
+ ;\r
+ ; Jump to SEC Core entry point\r
+ ;\r
+\r
+%ifdef ARCH_IA32\r
+\r
+ jmp esi\r
+\r
+%else\r
+\r
+ OneTimeCall Transition32FlatTo64Flat\r
+BITS 64\r
+\r
+ mov rax, 0x00000000ffffffff\r
+ and rsi, rax\r
+ and rdi, rax\r
+ and rbp, rax\r
+ ;\r
+ ; RSI - SEC Core entry point\r
+ ; RDI - PEI Core entry point\r
+ ; RBP - Start of BFV\r
+ ;\r
+ ; Jump to SEC Core entry point\r
+ ;\r
+\r
+ jmp rsi\r
+\r
+%endif\r
+\r
+\r
--- /dev/null
+## @file
+# Makefile to create FFS Raw sections for VTF images.
+#
+# Copyright (c) 2008, Intel Corporation
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+TARGETS = Bin/ResetVector.ia32.raw Bin/ResetVector.x64.raw
+ASM = nasm
+
+COMMON_DEPS = \
+ Ia16/16RealTo32Flat.asm \
+ Ia32/32FlatTo64Flat.asm \
+ JumpToSec.asm \
+ Ia16/ResetVectorVtf0.asm \
+ Ia32/SearchForBfvBase.asm \
+ Ia32/SearchForSecAndPeiEntries.asm \
+ SerialDebug.asm \
+ Makefile \
+ Tools/FixupForRawSection.py
+
+.PHONY: all
+all: $(TARGETS)
+
+Bin/ResetVector.ia32.raw: $(COMMON_DEPS) ResetVectorCode.asm
+ nasm -D ARCH_IA32 -o $@ ResetVectorCode.asm
+ python Tools/FixupForRawSection.py $@
+
+Bin/ResetVector.x64.raw: $(COMMON_DEPS) ResetVectorCode.asm
+ nasm -D ARCH_X64 -o $@ ResetVectorCode.asm
+ python Tools/FixupForRawSection.py $@
+
+clean:
+ -rm $(TARGETS)
+
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; ResetVectorCode.asm\r
+;\r
+; Abstract:\r
+;\r
+; Create code for VTF raw section.\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+%ifdef ARCH_IA32\r
+ %ifdef ARCH_X64\r
+ %error "Only one of ARCH_IA32 or ARCH_X64 can be defined."\r
+ %endif\r
+%elifdef ARCH_X64\r
+%else\r
+ %error "Either ARCH_IA32 or ARCH_X64 must be defined."\r
+%endif\r
+\r
+%include "CommonMacros.inc"\r
+%include "SerialDebug.asm"\r
+%include "Ia32/SearchForBfvBase.asm"\r
+%include "Ia32/SearchForSecAndPeiEntries.asm"\r
+%include "JumpToSec.asm"\r
+%include "Ia16/16RealTo32Flat.asm"\r
+\r
+%ifdef ARCH_X64\r
+%include "Ia32/32FlatTo64Flat.asm"\r
+%endif\r
+\r
+%include "Ia16/ResetVectorVtf0.asm"\r
+\r
--- /dev/null
+;------------------------------------------------------------------------------\r
+;\r
+; Copyright (c) 2008, Intel Corporation\r
+; All rights reserved. This program and the accompanying materials\r
+; are licensed and made available under the terms and conditions of the BSD License\r
+; which accompanies this distribution. The full text of the license may be found at\r
+; http://opensource.org/licenses/bsd-license.php\r
+;\r
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;\r
+; Module Name:\r
+;\r
+; SerialDebug.asm\r
+;\r
+; Abstract:\r
+;\r
+; Serial port support macros\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+BITS 16\r
+\r
+;//---------------------------------------------\r
+;// UART Register Offsets\r
+;//---------------------------------------------\r
+%define BAUD_LOW_OFFSET 0x00\r
+%define BAUD_HIGH_OFFSET 0x01\r
+%define IER_OFFSET 0x01\r
+%define LCR_SHADOW_OFFSET 0x01\r
+%define FCR_SHADOW_OFFSET 0x02\r
+%define IR_CONTROL_OFFSET 0x02\r
+%define FCR_OFFSET 0x02\r
+%define EIR_OFFSET 0x02\r
+%define BSR_OFFSET 0x03\r
+%define LCR_OFFSET 0x03\r
+%define MCR_OFFSET 0x04\r
+%define LSR_OFFSET 0x05\r
+%define MSR_OFFSET 0x06\r
+\r
+;//---------------------------------------------\r
+;// UART Register Bit Defines\r
+;//---------------------------------------------\r
+%define LSR_TXRDY 0x20\r
+%define LSR_RXDA 0x01\r
+%define DLAB 0x01\r
+\r
+; UINT16 gComBase = 0x3f8;\r
+; UINTN gBps = 115200;\r
+; UINT8 gData = 8;\r
+; UINT8 gStop = 1;\r
+; UINT8 gParity = 0;\r
+; UINT8 gBreakSet = 0;\r
+\r
+%define DEFAULT_COM_BASE 0x3f8\r
+%define DEFAULT_BPS 115200\r
+%define DEFAULT_DATA 8\r
+%define DEFAULT_STOP 1\r
+%define DEFAULT_PARITY 0\r
+%define DEFAULT_BREAK_SET 0\r
+\r
+%define SERIAL_DEFAULT_LCR ( \\r
+ (DEFAULT_BREAK_SET << 6) | \\r
+ (DEFAULT_PARITY << 3) | \\r
+ (DEFAULT_STOP << 2) | \\r
+ (DEFAULT_DATA - 5) \\r
+ )\r
+\r
+%define SERIAL_PORT_IO_BASE_ADDRESS DEFAULT_COM_BASE\r
+\r
+%macro inFromSerialPort 1\r
+ mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r
+ in al, dx\r
+%endmacro\r
+\r
+%macro waitForSerialTxReady 0\r
+\r
+%%waitingForTx:\r
+ inFromSerialPort LSR_OFFSET\r
+ test al, LSR_TXRDY\r
+ jz %%waitingForTx\r
+\r
+%endmacro\r
+\r
+%macro outToSerialPort 2\r
+ mov dx, (SERIAL_PORT_IO_BASE_ADDRESS + %1)\r
+ mov al, %2\r
+ out dx, al\r
+%endmacro\r
+\r
+%macro writeToSerialPort 1\r
+ waitForSerialTxReady\r
+ outToSerialPort 0, %1\r
+%endmacro\r
+\r
+real16InitSerialPort:\r
+ ;\r
+ ; Set communications format\r
+ ;\r
+ outToSerialPort LCR_OFFSET, ((DLAB << 7) | SERIAL_DEFAULT_LCR)\r
+\r
+ ;\r
+ ; Configure baud rate\r
+ ;\r
+ outToSerialPort BAUD_HIGH_OFFSET, ((115200 / DEFAULT_BPS) >> 8)\r
+ outToSerialPort BAUD_LOW_OFFSET, ((115200 / DEFAULT_BPS) & 0xff)\r
+\r
+ ;\r
+ ; Switch back to bank 0\r
+ ;\r
+ outToSerialPort LCR_OFFSET, SERIAL_DEFAULT_LCR\r
+\r
+ jmp real16SerialPortInitReturn\r
+\r
--- /dev/null
+## @file
+# Apply fixup to VTF binary image for FFS Raw section
+#
+# Copyright (c) 2008, Intel Corporation
+#
+# All rights reserved. This program and the accompanying materials
+# are licensed and made available under the terms and conditions of the BSD License
+# which accompanies this distribution. The full text of the license may be found at
+# http://opensource.org/licenses/bsd-license.php
+#
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+import sys
+
+filename = sys.argv[1]
+
+if filename.lower().find('ia32') >= 0:
+ d = open(sys.argv[1], 'rb').read()
+ c = ((len(d) + 4 + 7) & ~7) - 4
+ if c > len(d):
+ c -= len(d)
+ f = open(sys.argv[1], 'wb')
+ f.write('\x90' * c)
+ f.write(d)
+ f.close()
+else:
+ from struct import pack
+
+ PAGE_PRESENT = 0x01
+ PAGE_READ_WRITE = 0x02
+ PAGE_USER_SUPERVISOR = 0x04
+ PAGE_WRITE_THROUGH = 0x08
+ PAGE_CACHE_DISABLE = 0x010
+ PAGE_ACCESSED = 0x020
+ PAGE_DIRTY = 0x040
+ PAGE_PAT = 0x080
+ PAGE_GLOBAL = 0x0100
+ PAGE_2M_MBO = 0x080
+ PAGE_2M_PAT = 0x01000
+
+ def NopAlign4k(s):
+ c = ((len(s) + 0xfff) & ~0xfff) - len(s)
+ return ('\x90' * c) + s
+
+ def PageDirectoryEntries4GbOf2MbPages(baseAddress):
+
+ s = ''
+ for i in range(0x800):
+ i = (
+ baseAddress + long(i << 21) +
+ PAGE_2M_MBO +
+ PAGE_CACHE_DISABLE +
+ PAGE_ACCESSED +
+ PAGE_DIRTY +
+ PAGE_READ_WRITE +
+ PAGE_PRESENT
+ )
+ s += pack('Q', i)
+ return s
+
+ def PageDirectoryPointerTable4GbOf2MbPages(pdeBase):
+ s = ''
+ for i in range(0x200):
+ i = (
+ pdeBase +
+ (min(i, 3) << 12) +
+ PAGE_CACHE_DISABLE +
+ PAGE_ACCESSED +
+ PAGE_READ_WRITE +
+ PAGE_PRESENT
+ )
+ s += pack('Q', i)
+ return s
+
+ def PageMapLevel4Table4GbOf2MbPages(pdptBase):
+ s = ''
+ for i in range(0x200):
+ i = (
+ pdptBase +
+ (min(i, 0) << 12) +
+ PAGE_CACHE_DISABLE +
+ PAGE_ACCESSED +
+ PAGE_READ_WRITE +
+ PAGE_PRESENT
+ )
+ s += pack('Q', i)
+ return s
+
+ def First4GbPageEntries(topAddress):
+ PDE = PageDirectoryEntries4GbOf2MbPages(0L)
+ pml4tBase = topAddress - 0x1000
+ pdptBase = pml4tBase - 0x1000
+ pdeBase = pdptBase - len(PDE)
+ PDPT = PageDirectoryPointerTable4GbOf2MbPages(pdeBase)
+ PML4T = PageMapLevel4Table4GbOf2MbPages(pdptBase)
+ return PDE + PDPT + PML4T
+
+ def AlignAndAddPageTables():
+ d = open(sys.argv[1], 'rb').read()
+ code = NopAlign4k(d)
+ topAddress = 0x100000000 - len(code)
+ d = ('\x90' * 4) + First4GbPageEntries(topAddress) + code
+ f = open(sys.argv[1], 'wb')
+ f.write(d)
+ f.close()
+
+ AlignAndAddPageTables()
+
--- /dev/null
+#
+# ConvertAsm.py: Automatically generated from SecEntry.asm
+#
+# TITLE SecEntry.asm
+
+#------------------------------------------------------------------------------
+#*
+#* Copyright 2006 - 2009, Intel Corporation
+#* All rights reserved. This program and the accompanying materials
+#* are licensed and made available under the terms and conditions of the BSD License
+#* which accompanies this distribution. The full text of the license may be found at
+#* http://opensource.org/licenses/bsd-license.php
+#*
+#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#* CpuAsm.asm
+#*
+#* Abstract:
+#*
+#------------------------------------------------------------------------------
+
+
+#include "SecMain.h"
+
+#EXTERN ASM_PFX(SecCoreStartupWithStack)
+
+#
+# SecCore Entry Point
+#
+# Processor is in flat protected mode
+#
+# @param ESI Pointer to SEC Core Entry Point (this function)
+# @param EDI Pointer to PEI Core Entry Point
+# @param EBP Pointer to the start of the Boot Firmware Volume
+#
+# @return None
+#
+#
+.intel_syntax
+ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+
+ #
+ # Load temporary stack top at very low memory. The C code
+ # can reload to a better address.
+ #
+ mov eax, INITIAL_TOP_OF_STACK
+ mov esp, eax
+ nop
+
+ #
+ # Call into C code
+ #
+ push eax
+ push edi
+ push esi
+ push ebp
+ call ASM_PFX(SecCoreStartupWithStack)
+
+
+#END
+
--- /dev/null
+ TITLE SecEntry.asm\r
+;------------------------------------------------------------------------------\r
+;*\r
+;* Copyright 2006 - 2009, Intel Corporation\r
+;* All rights reserved. This program and the accompanying materials\r
+;* are licensed and made available under the terms and conditions of the BSD License\r
+;* which accompanies this distribution. The full text of the license may be found at\r
+;* http://opensource.org/licenses/bsd-license.php\r
+;*\r
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;*\r
+;* CpuAsm.asm\r
+;*\r
+;* Abstract:\r
+;*\r
+;------------------------------------------------------------------------------\r
+\r
+#include "SecMain.h"\r
+\r
+ .686\r
+ .model flat,C\r
+ .code\r
+\r
+EXTERN SecCoreStartupWithStack:PROC\r
+\r
+;\r
+; SecCore Entry Point\r
+;\r
+; Processor is in flat protected mode\r
+;\r
+; @param ESI Pointer to SEC Core Entry Point (this function)\r
+; @param EDI Pointer to PEI Core Entry Point\r
+; @param EBP Pointer to the start of the Boot Firmware Volume\r
+;\r
+; @return None\r
+;\r
+;\r
+_ModuleEntryPoint PROC PUBLIC\r
+\r
+ ;\r
+ ; Load temporary stack top at very low memory. The C code\r
+ ; can reload to a better address.\r
+ ;\r
+ mov eax, INITIAL_TOP_OF_STACK\r
+ mov esp, eax\r
+ nop\r
+\r
+ ;\r
+ ; Call into C code\r
+ ;\r
+ push eax\r
+ push edi\r
+ push esi\r
+ push ebp\r
+ call SecCoreStartupWithStack\r
+\r
+_ModuleEntryPoint ENDP\r
+\r
+END\r
--- /dev/null
+#------------------------------------------------------------------------------\r
+#\r
+# Copyright (c) 2008, Intel Corporation\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+# Module Name:\r
+#\r
+# Stack.asm\r
+#\r
+# Abstract:\r
+#\r
+# Switch the stack from temporary memory to permenent memory.\r
+#\r
+#------------------------------------------------------------------------------\r
+\r
+#------------------------------------------------------------------------------\r
+# VOID\r
+# EFIAPI\r
+# SecSwitchStack (\r
+# UINT32 TemporaryMemoryBase,\r
+# UINT32 PermenentMemoryBase\r
+# );\r
+#------------------------------------------------------------------------------ \r
+\r
+#include <ProcessorBind.h>\r
+\r
+ASM_GLOBAL ASM_PFX(SecSwitchStack)\r
+ASM_PFX(SecSwitchStack):\r
+#\r
+# Save three register: eax, ebx, ecx\r
+# \r
+ push %eax\r
+ push %ebx\r
+ push %ecx\r
+ push %edx\r
+ \r
+#\r
+# !!CAUTION!! this function address's is pushed into stack after\r
+# migration of whole temporary memory, so need save it to permenent\r
+# memory at first!\r
+# \r
+ \r
+ movl 20(%esp), %ebx # Save the first parameter\r
+ movl 24(%esp), %ecx # Save the second parameter\r
+ \r
+#\r
+# Save this function's return address into permenent memory at first.\r
+# Then, Fixup the esp point to permenent memory\r
+#\r
+\r
+ movl %esp, %eax\r
+ subl %ebx, %eax\r
+ addl %ecx, %eax\r
+ movl (%esp), %edx # copy pushed register's value to permenent memory\r
+ movl %edx, (%eax)\r
+ movl 4(%esp), %edx\r
+ movl %edx, 4(%eax)\r
+ movl 8(%esp), %edx\r
+ movl %edx, 8(%eax)\r
+ movl 12(%esp), %edx\r
+ movl %edx, 12(%eax)\r
+ movl 16(%esp), %edx\r
+ movl %edx, 16(%eax)\r
+ movl %eax, %esp # From now, esp is pointed to permenent memory\r
+\r
+#\r
+# Fixup the ebp point to permenent memory\r
+#\r
+ movl %ebp, %eax\r
+ subl %ebx, %eax\r
+ addl %ecx, %eax\r
+ movl %eax, %ebp # From now, ebp is pointed to permenent memory\r
+ \r
+#\r
+# Fixup callee's ebp point for PeiDispatch\r
+# \r
+ movl (%ebp), %eax\r
+ subl %ebx, %eax\r
+ addl %ecx, %eax\r
+ movl %eax, (%ebp) # From now, Temporary's PPI caller's stack is in permenent memory\r
+ \r
+ pop %edx\r
+ pop %ecx\r
+ pop %ebx\r
+ pop %eax\r
+ ret\r
+\r
--- /dev/null
+/** @file\r
+ Switch Stack functions.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the new stack\r
+ specified by NewStack and passing in the parameters specified by Context1 and\r
+ Context2. Context1 and Context2 are optional and may be NULL. The function\r
+ EntryPoint must never return.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param NewBsp A pointer to the new BSP for the EntryPoint on IPF. It's\r
+ Reserved on other architectures.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PeiSwitchStacks (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *Context3, OPTIONAL\r
+ IN VOID *OldTopOfStack,\r
+ IN VOID *NewStack\r
+ )\r
+{\r
+ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;\r
+ \r
+ ASSERT (EntryPoint != NULL);\r
+ ASSERT (NewStack != NULL);\r
+\r
+ //\r
+ // Stack should be aligned with CPU_STACK_ALIGNMENT\r
+ //\r
+ ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);\r
+\r
+ JumpBuffer.Eip = (UINTN)EntryPoint;\r
+ JumpBuffer.Esp = (UINTN)NewStack - sizeof (VOID*);\r
+ JumpBuffer.Esp -= sizeof (Context1) + sizeof (Context2) + sizeof(Context3);\r
+ ((VOID**)JumpBuffer.Esp)[1] = Context1;\r
+ ((VOID**)JumpBuffer.Esp)[2] = Context2;\r
+ ((VOID**)JumpBuffer.Esp)[3] = Context3;\r
+\r
+ LongJump (&JumpBuffer, (UINTN)-1);\r
+\r
+ //\r
+ // InternalSwitchStack () will never return\r
+ //\r
+ ASSERT (FALSE); \r
+}\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the new stack\r
+ specified by NewStack and passing in the parameters specified by Context1 and\r
+ Context2. Context1 and Context2 are optional and may be NULL. The function\r
+ EntryPoint must never return.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param NewBsp A pointer to the new BSP for the EntryPoint on IPF. It's\r
+ Reserved on other architectures.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecSwitchStack (\r
+ IN UINTN TemporaryMemoryBase,\r
+ IN UINTN PermanentMemoryBase,\r
+ IN UINTN CopySize\r
+ )\r
+{\r
+ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;\r
+ UINTN SetJumpFlag;\r
+\r
+ ASSERT ((VOID*)TemporaryMemoryBase != NULL);\r
+ ASSERT ((VOID*)PermanentMemoryBase != NULL);\r
+\r
+ SetJumpFlag = SetJump (&JumpBuffer);\r
+ //\r
+ // The initial call to SetJump() must always return 0.\r
+ // Subsequent calls to LongJump() may cause a non-zero value to be returned by SetJump().\r
+ //\r
+ if (SetJumpFlag == 0) {\r
+ DEBUG ((EFI_D_ERROR, "SecSwitchStack+%d: Esp: 0x%xL\n", __LINE__, JumpBuffer.Esp));\r
+ JumpBuffer.Esp =\r
+ (INTN)JumpBuffer.Esp -\r
+ (INTN)TemporaryMemoryBase +\r
+ (INTN)PermanentMemoryBase;\r
+ MemoryFence ();\r
+ CopyMem((VOID*)PermanentMemoryBase, (VOID*)TemporaryMemoryBase, CopySize);\r
+ LongJump (&JumpBuffer, (UINTN)-1);\r
+ }\r
+\r
+}\r
+\r
--- /dev/null
+/** @file
+ Main SEC phase code. Transitions to PEI.
+
+ Copyright (c) 2008 - 2009, Intel Corporation
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Ppi/TemporaryRamSupport.h>
+#include <Library/PcdLib.h>
+
+#include "SecMain.h"
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+STATIC TEMPORARY_RAM_SUPPORT_PPI mTempRamSupportPpi = {
+ (TEMPORARY_RAM_MIGRATION) TemporaryRamMigration
+};
+
+STATIC EFI_PEI_PPI_DESCRIPTOR mPrivateDispatchTable[] = {
+ {
+ (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+ &gEfiTemporaryRamSupportPpiGuid,
+ &mTempRamSupportPpi
+ },
+};
+
+
+VOID
+InitializeIdtPtr (
+ IN VOID* IdtPtr
+ )
+{
+ IA32_DESCRIPTOR IdtDescriptor;
+
+ IdtDescriptor.Base = (UINTN)IdtPtr;
+ IdtDescriptor.Limit = (UINT16) 0;
+ AsmWriteIdtr (&IdtDescriptor);
+}
+
+VOID
+EFIAPI
+SecCoreStartupWithStack (
+ IN VOID *BootFirmwareVolumePtr,
+ IN VOID *SecCoreEntryPoint,
+ IN VOID *PeiCoreEntryPoint,
+ IN VOID *TopOfCurrentStack
+ )
+{
+ EFI_SEC_PEI_HAND_OFF *SecCoreData;
+ UINT8 *BottomOfTempRam;
+ UINT8 *TopOfTempRam;
+ UINTN SizeOfTempRam;
+ VOID *IdtPtr;
+
+ DEBUG ((EFI_D_ERROR,
+ "SecCoreStartupWithStack(0x%x, 0x%x, 0x%x, 0x%x)\n",
+ (UINT32)(UINTN)BootFirmwareVolumePtr,
+ (UINT32)(UINTN)SecCoreEntryPoint,
+ (UINT32)(UINTN)PeiCoreEntryPoint,
+ (UINT32)(UINTN)TopOfCurrentStack));
+
+
+ BottomOfTempRam = (UINT8*)(UINTN) INITIAL_TOP_OF_STACK;
+ SizeOfTempRam = (UINTN) SIZE_64KB;
+ TopOfTempRam = BottomOfTempRam + SizeOfTempRam;
+
+ //
+ // |-------------|
+ // | SecCoreData | 4k
+ // |-------------|
+ // | Heap | 28k
+ // |-------------|
+ // | Stack | 32k
+ // |-------------| <---- INITIAL_TOP_OF_STACK
+ //
+
+ //
+ // Bind this information into the SEC hand-off state
+ //
+ SecCoreData = (EFI_SEC_PEI_HAND_OFF*)((UINTN) TopOfTempRam - SIZE_4KB);
+ SecCoreData->DataSize = sizeof(EFI_SEC_PEI_HAND_OFF);
+
+ SecCoreData->BootFirmwareVolumeBase = (VOID*)(UINTN) PcdGet32 (PcdOvmfFlashFvRecoveryBase);
+ SecCoreData->BootFirmwareVolumeSize = PcdGet32 (PcdOvmfFlashFvRecoverySize);
+
+ SecCoreData->TemporaryRamBase = (VOID*) BottomOfTempRam;
+ SecCoreData->TemporaryRamSize = SizeOfTempRam;
+
+ SecCoreData->PeiTemporaryRamSize = 28 * SIZE_1KB;
+ SecCoreData->PeiTemporaryRamBase = (VOID*)((UINTN)SecCoreData - SecCoreData->PeiTemporaryRamSize);
+
+ SecCoreData->StackBase = SecCoreData->TemporaryRamBase;
+ SecCoreData->StackSize = (UINTN)SecCoreData->PeiTemporaryRamBase - (UINTN)SecCoreData->TemporaryRamBase;
+
+ //
+ // Initialize the IDT Pointer, since IA32 & X64 architectures
+ // use it to store the PEI Services pointer.
+ //
+ IdtPtr = (VOID*)((UINT8*)SecCoreData + sizeof (*SecCoreData) + sizeof (UINTN));
+ IdtPtr = ALIGN_POINTER(IdtPtr, 16);
+ InitializeIdtPtr (IdtPtr);
+
+ //
+ // Transfer control to the PEI Core
+ //
+ PeiSwitchStacks (
+ (SWITCH_STACK_ENTRY_POINT) (UINTN) PeiCoreEntryPoint,
+ SecCoreData,
+ (VOID *) (UINTN) ((EFI_PEI_PPI_DESCRIPTOR *) &mPrivateDispatchTable),
+ NULL,
+ TopOfCurrentStack,
+ (VOID *)((UINTN)SecCoreData->StackBase + SecCoreData->StackSize)
+ );
+
+ //
+ // If we get here, then the PEI Core returned. This is an error
+ //
+ ASSERT (FALSE);
+ CpuDeadLoop ();
+}
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ )
+{
+ DEBUG ((EFI_D_ERROR, "TemporaryRamMigration(0x%x, 0x%x, 0x%x)\n", (UINTN)TemporaryMemoryBase, (UINTN)PermanentMemoryBase, CopySize));
+
+ //
+ // Migrate the whole temporary memory to permenent memory.
+ //
+ CopyMem((VOID*)(UINTN)PermanentMemoryBase, (VOID*)(UINTN)TemporaryMemoryBase, CopySize);
+
+ //
+ // SecSwitchStack function must be invoked after the memory migration
+ // immediatly, also we need fixup the stack change caused by new call into
+ // permenent memory.
+ //
+ SecSwitchStack (
+ (UINTN) TemporaryMemoryBase,
+ (UINTN) PermanentMemoryBase,
+ CopySize
+ );
+
+ return EFI_SUCCESS;
+}
+
--- /dev/null
+/** @file
+ Header file for SEC code
+
+ Copyright (c) 2008 - 2009, Intel Corporation
+
+ All rights reserved. This program and the accompanying materials
+ are licensed and made available under the terms and conditions of the BSD License
+ which accompanies this distribution. The full text of the license may be found at
+ http://opensource.org/licenses/bsd-license.php
+
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#ifndef _PLATFORM_SECMAIN_H_
+#define _PLATFORM_SECMAIN_H_
+
+VOID
+EFIAPI
+PeiSwitchStacks (
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,
+ IN VOID *Context1, OPTIONAL
+ IN VOID *Context2, OPTIONAL
+ IN VOID *Context3, OPTIONAL
+ IN VOID *OldTopOfStack,
+ IN VOID *NewStack
+ );
+
+VOID
+EFIAPI
+SecSwitchStack (
+ IN UINTN TemporaryMemoryBase,
+ IN UINTN PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+EFI_STATUS
+EFIAPI
+TemporaryRamMigration (
+ IN CONST EFI_PEI_SERVICES **PeiServices,
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,
+ IN UINTN CopySize
+ );
+
+#define INITIAL_TOP_OF_STACK BASE_128KB
+
+#endif // _PLATFORM_SECMAIN_H_
+
--- /dev/null
+#/** @file\r
+# SEC Driver\r
+#\r
+# Copyright (c) 2008, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = SecMain\r
+ FILE_GUID = df1ccef6-f301-4a63-9661-fc6030dcc880\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ EDK_RELEASE_VERSION = 0x00020000\r
+ EFI_SPECIFICATION_VERSION = 0x00020000\r
+ ENTRY_POINT = SecMain\r
+\r
+#\r
+# The following information is for reference only and not required by the build tools.\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+ SecMain.c\r
+\r
+[Sources.IA32]\r
+ Ia32/SecEntry.asm\r
+ Ia32/SecEntry.S\r
+ Ia32/SwitchStack.c\r
+\r
+[Sources.X64]\r
+ X64/SecEntry.asm\r
+ X64/SecEntry.S\r
+ X64/SwitchStack.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ OvmfPkg/OvmfPkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+\r
+[Ppis]\r
+ gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED\r
+\r
+[FixedPcd.common]\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoveryBase\r
+ gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashFvRecoverySize\r
+\r
--- /dev/null
+# TITLE SecEntry.asm
+
+#------------------------------------------------------------------------------
+#*
+#* Copyright 2006 - 2009, Intel Corporation
+#* All rights reserved. This program and the accompanying materials
+#* are licensed and made available under the terms and conditions of the BSD License
+#* which accompanies this distribution. The full text of the license may be found at
+#* http://opensource.org/licenses/bsd-license.php
+#*
+#* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#*
+#* CpuAsm.asm
+#*
+#* Abstract:
+#*
+#------------------------------------------------------------------------------
+
+
+#include "SecMain.h"
+
+#EXTERN ASM_PFX(SecCoreStartupWithStack)
+
+#
+# SecCore Entry Point
+#
+# Processor is in flat protected mode
+#
+# @param ESI Pointer to SEC Core Entry Point (this function)
+# @param EDI Pointer to PEI Core Entry Point
+# @param EBP Pointer to the start of the Boot Firmware Volume
+#
+# @return None
+#
+#
+.intel_syntax
+ASM_GLOBAL ASM_PFX(_ModuleEntryPoint)
+ASM_PFX(_ModuleEntryPoint):
+
+ #
+ # Load temporary stack top at very low memory. The C code
+ # can reload to a better address.
+ #
+ mov %rsp, INITIAL_TOP_OF_STACK
+ nop
+
+ #
+ # Setup parameters and call SecCoreStartupWithStack
+ # rcx: BootFirmwareVolumePtr
+ # rdx: SecCoreEntryPoint
+ # r8: PeiCoreEntryPoint
+ # r9: TopOfCurrentStack
+ #
+ mov %rcx, %rbp
+ mov %rdx, %rsi
+ mov %r8, %rdi
+ mov %r9, %rsp
+ call ASM_PFX(SecCoreStartupWithStack)
+
--- /dev/null
+ TITLE SecEntry.asm\r
+;------------------------------------------------------------------------------\r
+;*\r
+;* Copyright 2006 - 2009, Intel Corporation\r
+;* All rights reserved. This program and the accompanying materials\r
+;* are licensed and made available under the terms and conditions of the BSD License\r
+;* which accompanies this distribution. The full text of the license may be found at\r
+;* http://opensource.org/licenses/bsd-license.php\r
+;*\r
+;* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+;* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+;*\r
+;* CpuAsm.asm\r
+;*\r
+;* Abstract:\r
+;*\r
+;------------------------------------------------------------------------------\r
+\r
+#include "SecMain.h"\r
+\r
+.code\r
+\r
+EXTERN SecCoreStartupWithStack:PROC\r
+\r
+;\r
+; SecCore Entry Point\r
+;\r
+; Processor is in flat protected mode\r
+;\r
+; @param ESI Pointer to SEC Core Entry Point (this function)\r
+; @param EDI Pointer to PEI Core Entry Point\r
+; @param EBP Pointer to the start of the Boot Firmware Volume\r
+;\r
+; @return None\r
+;\r
+;\r
+_ModuleEntryPoint PROC PUBLIC\r
+\r
+ ;\r
+ ; Load temporary stack top at very low memory. The C code\r
+ ; can reload to a better address.\r
+ ;\r
+ mov rsp, INITIAL_TOP_OF_STACK\r
+ nop\r
+\r
+ ;\r
+ ; Setup parameters and call SecCoreStartupWithStack\r
+ ; rcx: BootFirmwareVolumePtr\r
+ ; rdx: SecCoreEntryPoint\r
+ ; r8: PeiCoreEntryPoint\r
+ ; r9: TopOfCurrentStack\r
+ ;\r
+ mov rcx, rbp\r
+ mov rdx, rsi\r
+ mov r8, rdi\r
+ mov r9, rsp\r
+ call SecCoreStartupWithStack\r
+\r
+_ModuleEntryPoint ENDP\r
+\r
+END\r
--- /dev/null
+/** @file\r
+ Switch Stack functions.\r
+\r
+ Copyright (c) 2006 - 2007, Intel Corporation<BR>\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+//\r
+// Include common header file for this module.\r
+//\r
+\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PeiServicesLib.h>\r
+\r
+//\r
+// Type define for PEI Core Entry Point function\r
+//\r
+typedef\r
+VOID\r
+(EFIAPI *PEI_CORE_ENTRY_POINT)(\r
+ IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData,\r
+ IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList,\r
+ IN VOID *Data\r
+ )\r
+;\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the new stack\r
+ specified by NewStack and passing in the parameters specified by Context1 and\r
+ Context2. Context1 and Context2 are optional and may be NULL. The function\r
+ EntryPoint must never return.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param NewBsp A pointer to the new BSP for the EntryPoint on IPF. It's\r
+ Reserved on other architectures.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+PeiSwitchStacks (\r
+ IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
+ IN VOID *Context1, OPTIONAL\r
+ IN VOID *Context2, OPTIONAL\r
+ IN VOID *Context3, OPTIONAL\r
+ IN VOID *OldTopOfStack,\r
+ IN VOID *NewStack\r
+ )\r
+{\r
+ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;\r
+ UINTN SizeOfStackUsed;\r
+ UINTN SetJumpFlag;\r
+ \r
+ ASSERT (EntryPoint != NULL);\r
+ ASSERT (NewStack != NULL);\r
+\r
+ SetJumpFlag = SetJump (&JumpBuffer);\r
+ //\r
+ // The initial call to SetJump() must always return 0.\r
+ // Subsequent calls to LongJump() may cause a non-zero value to be returned by SetJump().\r
+ //\r
+ if (SetJumpFlag == 0) {\r
+ //\r
+ // Stack should be aligned with CPU_STACK_ALIGNMENT\r
+ //\r
+ ASSERT (((UINTN)NewStack & (CPU_STACK_ALIGNMENT - 1)) == 0);\r
+ \r
+ //JumpBuffer.Rip = (UINTN)EntryPoint;\r
+ SizeOfStackUsed = (UINTN)OldTopOfStack - JumpBuffer.Rsp;\r
+ JumpBuffer.Rsp = (UINTN)NewStack - SizeOfStackUsed;\r
+ MemoryFence ();\r
+ CopyMem (\r
+ (VOID*) ((UINTN)NewStack - SizeOfStackUsed),\r
+ (VOID*) ((UINTN)OldTopOfStack - SizeOfStackUsed),\r
+ SizeOfStackUsed\r
+ );\r
+ LongJump (&JumpBuffer, (UINTN)-1);\r
+ } else {\r
+ (*(PEI_CORE_ENTRY_POINT)(EntryPoint)) (\r
+ (EFI_SEC_PEI_HAND_OFF *) Context1,\r
+ (EFI_PEI_PPI_DESCRIPTOR *) Context2,\r
+ Context3\r
+ );\r
+ }\r
+\r
+ //\r
+ // InternalSwitchStack () will never return\r
+ //\r
+ ASSERT (FALSE); \r
+}\r
+\r
+/**\r
+ Transfers control to a function starting with a new stack.\r
+\r
+ Transfers control to the function specified by EntryPoint using the new stack\r
+ specified by NewStack and passing in the parameters specified by Context1 and\r
+ Context2. Context1 and Context2 are optional and may be NULL. The function\r
+ EntryPoint must never return.\r
+\r
+ If EntryPoint is NULL, then ASSERT().\r
+ If NewStack is NULL, then ASSERT().\r
+\r
+ @param EntryPoint A pointer to function to call with the new stack.\r
+ @param Context1 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param Context2 A pointer to the context to pass into the EntryPoint\r
+ function.\r
+ @param NewStack A pointer to the new stack to use for the EntryPoint\r
+ function.\r
+ @param NewBsp A pointer to the new BSP for the EntryPoint on IPF. It's\r
+ Reserved on other architectures.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+SecSwitchStack (\r
+ IN UINTN TemporaryMemoryBase,\r
+ IN UINTN PermanentMemoryBase,\r
+ IN UINTN CopySize\r
+ )\r
+{\r
+ BASE_LIBRARY_JUMP_BUFFER JumpBuffer;\r
+ UINTN SetJumpFlag;\r
+\r
+ ASSERT ((VOID*)TemporaryMemoryBase != NULL);\r
+ ASSERT ((VOID*)PermanentMemoryBase != NULL);\r
+\r
+ SetJumpFlag = SetJump (&JumpBuffer);\r
+ //\r
+ // The initial call to SetJump() must always return 0.\r
+ // Subsequent calls to LongJump() may cause a non-zero value to be returned by SetJump().\r
+ //\r
+ if (SetJumpFlag == 0) {\r
+ DEBUG ((EFI_D_ERROR, "SecSwitchStack+%d: Rsp: 0x%xL\n", __LINE__, JumpBuffer.Rsp));\r
+ JumpBuffer.Rsp =\r
+ (INTN)JumpBuffer.Rsp -\r
+ (INTN)TemporaryMemoryBase +\r
+ (INTN)PermanentMemoryBase;\r
+ MemoryFence ();\r
+ CopyMem((VOID*)PermanentMemoryBase, (VOID*)TemporaryMemoryBase, CopySize);\r
+ LongJump (&JumpBuffer, (UINTN)-1);\r
+ }\r
+\r
+}\r
+\r
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