ArmPkg: CpuDxe: fix AArch64 interrupt read masks

The AArch64 DAIF bits are different for reading (mrs) versus writing
(msr). The bitmask definitions assumed they were the same causing
incorrect results when trying to determine the current interrupt
state through ArmGetInterruptState.

The logic for interpreting the DAIF read data using the csel instruction
was also incorrect and is fixed.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Eugene Cohen <eugene@hp.com>
Reviewed-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>

diff --git a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
index 8fd4194ab2bcb5d56741910f2a4d648312582326..341bbce76cbd064e52ce9f565c38d762074a91ee 100644 (file)
--- a/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
+++ b/ArmPkg/Library/ArmLib/AArch64/ArmLibSupportV8.S
@@ -35,12 +35,14 @@ GCC_ASM_EXPORT (ReadCLIDR)
 \r
 .set MPIDR_U_BIT,    (30)\r
 .set MPIDR_U_MASK,   (1 << MPIDR_U_BIT)\r
-.set DAIF_FIQ_BIT,   (1 << 0)\r
-.set DAIF_IRQ_BIT,   (1 << 1)\r
-.set DAIF_ABORT_BIT, (1 << 2)\r
-.set DAIF_DEBUG_BIT, (1 << 3)\r
-.set DAIF_INT_BITS,  (DAIF_FIQ_BIT | DAIF_IRQ_BIT)\r
-.set DAIF_ALL,       (DAIF_DEBUG_BIT | DAIF_ABORT_BIT | DAIF_INT_BITS)\r
+\r
+// DAIF bit definitions for writing through msr daifclr/sr daifset\r
+.set DAIF_WR_FIQ_BIT,   (1 << 0)\r
+.set DAIF_WR_IRQ_BIT,   (1 << 1)\r
+.set DAIF_WR_ABORT_BIT, (1 << 2)\r
+.set DAIF_WR_DEBUG_BIT, (1 << 3)\r
+.set DAIF_WR_INT_BITS,  (DAIF_WR_FIQ_BIT | DAIF_WR_IRQ_BIT)\r
+.set DAIF_WR_ALL,       (DAIF_WR_DEBUG_BIT | DAIF_WR_ABORT_BIT | DAIF_WR_INT_BITS)\r
 \r
 \r
 ASM_PFX(ArmIsMpCore):\r
@@ -52,55 +54,55 @@ ASM_PFX(ArmIsMpCore):
 \r
 \r
 ASM_PFX(ArmEnableAsynchronousAbort):\r
-  msr   daifclr, #DAIF_ABORT_BIT\r
+  msr   daifclr, #DAIF_WR_ABORT_BIT\r
   isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmDisableAsynchronousAbort):\r
-  msr   daifset, #DAIF_ABORT_BIT\r
+  msr   daifset, #DAIF_WR_ABORT_BIT\r
   isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmEnableIrq):\r
-  msr   daifclr, #DAIF_IRQ_BIT\r
+  msr   daifclr, #DAIF_WR_IRQ_BIT\r
   isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmDisableIrq):\r
-  msr   daifset, #DAIF_IRQ_BIT\r
+  msr   daifset, #DAIF_WR_IRQ_BIT\r
   isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmEnableFiq):\r
-  msr   daifclr, #DAIF_FIQ_BIT\r
+  msr   daifclr, #DAIF_WR_FIQ_BIT\r
   isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmDisableFiq):\r
-  msr   daifset, #DAIF_FIQ_BIT\r
+  msr   daifset, #DAIF_WR_FIQ_BIT\r
   isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmEnableInterrupts):\r
-  msr   daifclr, #DAIF_INT_BITS\r
+  msr   daifclr, #DAIF_WR_INT_BITS\r
   isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmDisableInterrupts):\r
-  msr   daifset, #DAIF_INT_BITS\r
+  msr   daifset, #DAIF_WR_INT_BITS\r
   isb\r
   ret\r
 \r
 \r
 ASM_PFX(ArmDisableAllExceptions):\r
-  msr   daifset, #DAIF_ALL\r
+  msr   daifset, #DAIF_WR_ALL\r
   isb\r
   ret\r
 \r

diff --git a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
index 50faef4ed0b9750aac29956e36bb532da7f2be28..a6fd5e34454f4018f59f18733cf8ac3d1de8c4fb 100644 (file)
--- a/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
+++ b/ArmPkg/Library/ArmLib/Common/AArch64/ArmLibSupport.S
@@ -42,8 +42,8 @@ GCC_ASM_EXPORT (ArmWriteCpuActlr)
 \r
 #------------------------------------------------------------------------------\r
 \r
-.set DAIF_FIQ_BIT,   (1 << 0)\r
-.set DAIF_IRQ_BIT,   (1 << 1)\r
+.set DAIF_RD_FIQ_BIT,   (1 << 6)\r
+.set DAIF_RD_IRQ_BIT,   (1 << 7)\r
 \r
 ASM_PFX(ArmReadMidr):\r
   mrs     x0, midr_el1        // Read from Main ID Register (MIDR)\r
@@ -55,18 +55,14 @@ ASM_PFX(ArmCacheInfo):
 \r
 ASM_PFX(ArmGetInterruptState):\r
   mrs     x0, daif\r
-  tst     w0, #DAIF_IRQ_BIT   // Check if IRQ is enabled. Enabled if 0.\r
-  mov     w0, #0\r
-  mov     w1, #1\r
-  csel    w0, w1, w0, ne\r
+  tst     w0, #DAIF_RD_IRQ_BIT  // Check if IRQ is enabled. Enabled if 0 (Z=1)\r
+  cset    w0, eq                // if Z=1 return 1, else 0\r
   ret\r
 \r
 ASM_PFX(ArmGetFiqState):\r
   mrs     x0, daif\r
-  tst     w0, #DAIF_FIQ_BIT   // Check if FIQ is enabled. Enabled if 0.\r
-  mov     w0, #0\r
-  mov     w1, #1\r
-  csel    w0, w1, w0, ne\r
+  tst     w0, #DAIF_RD_FIQ_BIT  // Check if FIQ is enabled. Enabled if 0 (Z=1)\r
+  cset    w0, eq                // if Z=1 return 1, else 0\r
   ret\r
 \r
 ASM_PFX(ArmWriteCpacr):\r