**/\r
\r
#include "CpuMpPei.h"\r
-\r
-GLOBAL_REMOVE_IF_UNREFERENCED EFI_PEI_NOTIFY_DESCRIPTOR mNotifyList = {\r
- (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
- &gEfiEndOfPeiSignalPpiGuid,\r
- CpuMpEndOfPeiCallback\r
-};\r
-\r
-/**\r
- Sort the APIC ID of all processors.\r
-\r
- This function sorts the APIC ID of all processors so that processor number is\r
- assigned in the ascending order of APIC ID which eases MP debugging.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
-**/\r
-STATIC\r
-VOID\r
-SortApicId (\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData\r
- )\r
-{\r
- UINTN Index1;\r
- UINTN Index2;\r
- UINTN Index3;\r
- UINT32 ApicId;\r
- PEI_CPU_DATA CpuData;\r
- UINT32 ApCount;\r
-\r
- ApCount = PeiCpuMpData->CpuCount - 1;\r
-\r
- if (ApCount != 0) {\r
- for (Index1 = 0; Index1 < ApCount; Index1++) {\r
- Index3 = Index1;\r
- //\r
- // Sort key is the hardware default APIC ID\r
- //\r
- ApicId = PeiCpuMpData->CpuData[Index1].ApicId;\r
- for (Index2 = Index1 + 1; Index2 <= ApCount; Index2++) {\r
- if (ApicId > PeiCpuMpData->CpuData[Index2].ApicId) {\r
- Index3 = Index2;\r
- ApicId = PeiCpuMpData->CpuData[Index2].ApicId;\r
- }\r
- }\r
- if (Index3 != Index1) {\r
- CopyMem (&CpuData, &PeiCpuMpData->CpuData[Index3], sizeof (PEI_CPU_DATA));\r
- CopyMem (\r
- &PeiCpuMpData->CpuData[Index3],\r
- &PeiCpuMpData->CpuData[Index1],\r
- sizeof (PEI_CPU_DATA)\r
- );\r
- CopyMem (&PeiCpuMpData->CpuData[Index1], &CpuData, sizeof (PEI_CPU_DATA));\r
- }\r
- }\r
-\r
- //\r
- // Get the processor number for the BSP\r
- //\r
- ApicId = GetInitialApicId ();\r
- for (Index1 = 0; Index1 < PeiCpuMpData->CpuCount; Index1++) {\r
- if (PeiCpuMpData->CpuData[Index1].ApicId == ApicId) {\r
- PeiCpuMpData->BspNumber = (UINT32) Index1;\r
- break;\r
- }\r
- }\r
- }\r
-}\r
-\r
-/**\r
- Enable x2APIC mode on APs.\r
-\r
- @param Buffer Pointer to private data buffer.\r
-**/\r
-STATIC\r
-VOID\r
-EFIAPI\r
-ApFuncEnableX2Apic (\r
- IN OUT VOID *Buffer\r
- )\r
-{\r
- SetApicMode (LOCAL_APIC_MODE_X2APIC);\r
-}\r
-\r
-/**\r
- Get AP loop mode.\r
-\r
- @param MonitorFilterSize Returns the largest monitor-line size in bytes.\r
-\r
- @return The AP loop mode.\r
-**/\r
-STATIC\r
-UINT8\r
-GetApLoopMode (\r
- OUT UINT16 *MonitorFilterSize\r
- )\r
-{\r
- UINT8 ApLoopMode;\r
- UINT32 RegEbx;\r
- UINT32 RegEcx;\r
- UINT32 RegEdx;\r
-\r
- ASSERT (MonitorFilterSize != NULL);\r
-\r
- ApLoopMode = PcdGet8 (PcdCpuApLoopMode);\r
- ASSERT (ApLoopMode >= ApInHltLoop && ApLoopMode <= ApInRunLoop);\r
- if (ApLoopMode == ApInMwaitLoop) {\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, &RegEcx, NULL);\r
- if ((RegEcx & BIT3) == 0) {\r
- //\r
- // If processor does not support MONITOR/MWAIT feature\r
- // by CPUID.[EAX=01H]:ECX.BIT3, force AP in Hlt-loop mode\r
- //\r
- ApLoopMode = ApInHltLoop;\r
- }\r
- }\r
-\r
- if (ApLoopMode == ApInHltLoop) {\r
- *MonitorFilterSize = 0;\r
- } else if (ApLoopMode == ApInRunLoop) {\r
- *MonitorFilterSize = sizeof (UINT32);\r
- } else if (ApLoopMode == ApInMwaitLoop) {\r
- //\r
- // CPUID.[EAX=05H]:EBX.BIT0-15: Largest monitor-line size in bytes\r
- // CPUID.[EAX=05H].EDX: C-states supported using MWAIT\r
- //\r
- AsmCpuid (CPUID_MONITOR_MWAIT, NULL, &RegEbx, NULL, &RegEdx);\r
- *MonitorFilterSize = RegEbx & 0xFFFF;\r
- }\r
-\r
- return ApLoopMode;\r
-}\r
-\r
-/**\r
- Get CPU MP Data pointer from the Guided HOB.\r
-\r
- @return Pointer to Pointer to PEI CPU MP Data\r
-**/\r
-PEI_CPU_MP_DATA *\r
-GetMpHobData (\r
- VOID\r
- )\r
-{\r
- EFI_HOB_GUID_TYPE *GuidHob;\r
- VOID *DataInHob;\r
- PEI_CPU_MP_DATA *CpuMpData;\r
-\r
- CpuMpData = NULL;\r
- GuidHob = GetFirstGuidHob (&gEfiCallerIdGuid);\r
- if (GuidHob != NULL) {\r
- DataInHob = GET_GUID_HOB_DATA (GuidHob);\r
- CpuMpData = (PEI_CPU_MP_DATA *)(*(UINTN *)DataInHob);\r
- }\r
- ASSERT (CpuMpData != NULL);\r
- return CpuMpData;\r
-}\r
-\r
-/**\r
- Save the volatile registers required to be restored following INIT IPI.\r
- \r
- @param VolatileRegisters Returns buffer saved the volatile resisters\r
-**/\r
-STATIC\r
-VOID\r
-SaveVolatileRegisters (\r
- OUT CPU_VOLATILE_REGISTERS *VolatileRegisters\r
- )\r
-{\r
- UINT32 RegEdx;\r
-\r
- VolatileRegisters->Cr0 = AsmReadCr0 ();\r
- VolatileRegisters->Cr3 = AsmReadCr3 ();\r
- VolatileRegisters->Cr4 = AsmReadCr4 ();\r
-\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);\r
- if ((RegEdx & BIT2) != 0) {\r
- //\r
- // If processor supports Debugging Extensions feature\r
- // by CPUID.[EAX=01H]:EDX.BIT2\r
- //\r
- VolatileRegisters->Dr0 = AsmReadDr0 ();\r
- VolatileRegisters->Dr1 = AsmReadDr1 ();\r
- VolatileRegisters->Dr2 = AsmReadDr2 ();\r
- VolatileRegisters->Dr3 = AsmReadDr3 ();\r
- VolatileRegisters->Dr6 = AsmReadDr6 ();\r
- VolatileRegisters->Dr7 = AsmReadDr7 ();\r
- }\r
-}\r
-\r
-/**\r
- Restore the volatile registers following INIT IPI.\r
- \r
- @param VolatileRegisters Pointer to volatile resisters\r
- @param IsRestoreDr TRUE: Restore DRx if supported\r
- FALSE: Do not restore DRx\r
-**/\r
-STATIC\r
-VOID\r
-RestoreVolatileRegisters (\r
- IN CPU_VOLATILE_REGISTERS *VolatileRegisters,\r
- IN BOOLEAN IsRestoreDr\r
- )\r
-{\r
- UINT32 RegEdx;\r
-\r
- AsmWriteCr0 (VolatileRegisters->Cr0);\r
- AsmWriteCr3 (VolatileRegisters->Cr3);\r
- AsmWriteCr4 (VolatileRegisters->Cr4);\r
-\r
- if (IsRestoreDr) {\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);\r
- if ((RegEdx & BIT2) != 0) {\r
- //\r
- // If processor supports Debugging Extensions feature\r
- // by CPUID.[EAX=01H]:EDX.BIT2\r
- //\r
- AsmWriteDr0 (VolatileRegisters->Dr0);\r
- AsmWriteDr1 (VolatileRegisters->Dr1);\r
- AsmWriteDr2 (VolatileRegisters->Dr2);\r
- AsmWriteDr3 (VolatileRegisters->Dr3);\r
- AsmWriteDr6 (VolatileRegisters->Dr6);\r
- AsmWriteDr7 (VolatileRegisters->Dr7);\r
- }\r
- }\r
-}\r
-\r
-/**\r
- Find the current Processor number by APIC ID.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
- @param ProcessorNumber Return the pocessor number found\r
-\r
- @retval EFI_SUCCESS ProcessorNumber is found and returned.\r
- @retval EFI_NOT_FOUND ProcessorNumber is not found.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-GetProcessorNumber (\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData,\r
- OUT UINTN *ProcessorNumber\r
- )\r
-{\r
- UINTN TotalProcessorNumber;\r
- UINTN Index;\r
-\r
- TotalProcessorNumber = PeiCpuMpData->CpuCount;\r
- for (Index = 0; Index < TotalProcessorNumber; Index ++) {\r
- if (PeiCpuMpData->CpuData[Index].ApicId == GetInitialApicId ()) {\r
- *ProcessorNumber = Index;\r
- return EFI_SUCCESS;\r
- }\r
- }\r
- return EFI_NOT_FOUND;\r
-}\r
-\r
-/**\r
- This function will be called from AP reset code if BSP uses WakeUpAP.\r
-\r
- @param ExchangeInfo Pointer to the MP exchange info buffer\r
- @param NumApsExecuting Number of current executing AP\r
-**/\r
-STATIC\r
-VOID\r
-EFIAPI\r
-ApCFunction (\r
- IN MP_CPU_EXCHANGE_INFO *ExchangeInfo,\r
- IN UINTN NumApsExecuting\r
- )\r
-{\r
- PEI_CPU_MP_DATA *PeiCpuMpData;\r
- UINTN ProcessorNumber;\r
- EFI_AP_PROCEDURE Procedure;\r
- UINTN BistData;\r
- volatile UINT32 *ApStartupSignalBuffer;\r
-\r
- PeiCpuMpData = ExchangeInfo->PeiCpuMpData;\r
- while (TRUE) {\r
- if (PeiCpuMpData->InitFlag) {\r
- ProcessorNumber = NumApsExecuting;\r
- //\r
- // Sync BSP's Control registers to APs\r
- //\r
- RestoreVolatileRegisters (&PeiCpuMpData->CpuData[0].VolatileRegisters, FALSE);\r
- //\r
- // This is first time AP wakeup, get BIST information from AP stack\r
- //\r
- BistData = *(UINTN *) (PeiCpuMpData->Buffer + ProcessorNumber * PeiCpuMpData->CpuApStackSize - sizeof (UINTN));\r
- PeiCpuMpData->CpuData[ProcessorNumber].Health.Uint32 = (UINT32) BistData;\r
- PeiCpuMpData->CpuData[ProcessorNumber].ApicId = GetInitialApicId ();\r
- if (PeiCpuMpData->CpuData[ProcessorNumber].ApicId >= 0xFF) {\r
- //\r
- // Set x2APIC mode if there are any logical processor reporting\r
- // an APIC ID of 255 or greater.\r
- //\r
- AcquireSpinLock(&PeiCpuMpData->MpLock);\r
- PeiCpuMpData->X2ApicEnable = TRUE;\r
- ReleaseSpinLock(&PeiCpuMpData->MpLock);\r
- }\r
- //\r
- // Sync BSP's Mtrr table to all wakeup APs and load microcode on APs.\r
- //\r
- MtrrSetAllMtrrs (&PeiCpuMpData->MtrrTable);\r
- MicrocodeDetect (PeiCpuMpData);\r
- PeiCpuMpData->CpuData[ProcessorNumber].State = CpuStateIdle;\r
- } else {\r
- //\r
- // Execute AP function if AP is not disabled\r
- //\r
- GetProcessorNumber (PeiCpuMpData, &ProcessorNumber);\r
- if (PeiCpuMpData->ApLoopMode == ApInHltLoop) {\r
- //\r
- // Restore AP's volatile registers saved\r
- //\r
- RestoreVolatileRegisters (&PeiCpuMpData->CpuData[ProcessorNumber].VolatileRegisters, TRUE);\r
- }\r
-\r
- if ((PeiCpuMpData->CpuData[ProcessorNumber].State != CpuStateDisabled) &&\r
- (PeiCpuMpData->ApFunction != 0)) {\r
- PeiCpuMpData->CpuData[ProcessorNumber].State = CpuStateBusy;\r
- Procedure = (EFI_AP_PROCEDURE)(UINTN)PeiCpuMpData->ApFunction;\r
- //\r
- // Invoke AP function here\r
- //\r
- Procedure ((VOID *)(UINTN)PeiCpuMpData->ApFunctionArgument);\r
- //\r
- // Re-get the processor number due to BSP/AP maybe exchange in AP function\r
- //\r
- GetProcessorNumber (PeiCpuMpData, &ProcessorNumber);\r
- PeiCpuMpData->CpuData[ProcessorNumber].State = CpuStateIdle;\r
- }\r
- }\r
-\r
- //\r
- // AP finished executing C code\r
- //\r
- InterlockedIncrement ((UINT32 *)&PeiCpuMpData->FinishedCount);\r
-\r
- //\r
- // Place AP is specified loop mode\r
- //\r
- if (PeiCpuMpData->ApLoopMode == ApInHltLoop) {\r
- //\r
- // Save AP volatile registers\r
- //\r
- SaveVolatileRegisters (&PeiCpuMpData->CpuData[ProcessorNumber].VolatileRegisters);\r
- //\r
- // Place AP in Hlt-loop\r
- //\r
- while (TRUE) {\r
- DisableInterrupts ();\r
- CpuSleep ();\r
- CpuPause ();\r
- }\r
- }\r
- ApStartupSignalBuffer = PeiCpuMpData->CpuData[ProcessorNumber].StartupApSignal;\r
- while (TRUE) {\r
- DisableInterrupts ();\r
- if (PeiCpuMpData->ApLoopMode == ApInMwaitLoop) {\r
- //\r
- // Place AP in Mwait-loop\r
- //\r
- AsmMonitor ((UINTN)ApStartupSignalBuffer, 0, 0);\r
- if (*ApStartupSignalBuffer != WAKEUP_AP_SIGNAL) {\r
- //\r
- // If AP start-up signal is not set, place AP into\r
- // the maximum C-state\r
- //\r
- AsmMwait (PeiCpuMpData->ApTargetCState << 4, 0);\r
- }\r
- } else if (PeiCpuMpData->ApLoopMode == ApInRunLoop) {\r
- //\r
- // Place AP in Run-loop\r
- //\r
- CpuPause ();\r
- } else {\r
- ASSERT (FALSE);\r
- }\r
-\r
- //\r
- // If AP start-up signal is written, AP is waken up\r
- // otherwise place AP in loop again\r
- //\r
- if (*ApStartupSignalBuffer == WAKEUP_AP_SIGNAL) {\r
- //\r
- // Clear AP start-up signal when AP waken up\r
- //\r
- InterlockedCompareExchange32 (\r
- (UINT32 *)ApStartupSignalBuffer,\r
- WAKEUP_AP_SIGNAL,\r
- 0\r
- );\r
- break;\r
- }\r
- }\r
- }\r
-}\r
-\r
-/**\r
- Write AP start-up signal to wakeup AP.\r
-\r
- @param ApStartupSignalBuffer Pointer to AP wakeup signal\r
-**/\r
-VOID\r
-WriteStartupSignal (\r
- IN volatile UINT32 *ApStartupSignalBuffer\r
- )\r
-{\r
- *ApStartupSignalBuffer = WAKEUP_AP_SIGNAL;\r
- //\r
- // If AP is waken up, StartupApSignal should be cleared.\r
- // Otherwise, write StartupApSignal again till AP waken up.\r
- //\r
- while (InterlockedCompareExchange32 (\r
- (UINT32 *)ApStartupSignalBuffer,\r
- WAKEUP_AP_SIGNAL,\r
- WAKEUP_AP_SIGNAL\r
- ) != 0) {\r
- CpuPause ();\r
- }\r
-}\r
-\r
-/**\r
- This function will be called by BSP to wakeup AP.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
- @param Broadcast TRUE: Send broadcast IPI to all APs\r
- FALSE: Send IPI to AP by ApicId\r
- @param ProcessorNumber The handle number of specified processor\r
- @param Procedure The function to be invoked by AP\r
- @param ProcedureArgument The argument to be passed into AP function\r
-**/\r
-STATIC\r
-VOID\r
-WakeUpAP (\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData,\r
- IN BOOLEAN Broadcast,\r
- IN UINTN ProcessorNumber,\r
- IN EFI_AP_PROCEDURE Procedure, OPTIONAL\r
- IN VOID *ProcedureArgument OPTIONAL\r
- )\r
-{\r
- volatile MP_CPU_EXCHANGE_INFO *ExchangeInfo;\r
- UINTN Index;\r
-\r
- PeiCpuMpData->ApFunction = (UINTN) Procedure;\r
- PeiCpuMpData->ApFunctionArgument = (UINTN) ProcedureArgument;\r
- PeiCpuMpData->FinishedCount = 0;\r
-\r
- ExchangeInfo = PeiCpuMpData->MpCpuExchangeInfo;\r
- ExchangeInfo->Lock = 0;\r
- ExchangeInfo->StackStart = PeiCpuMpData->Buffer;\r
- ExchangeInfo->StackSize = PeiCpuMpData->CpuApStackSize;\r
- ExchangeInfo->BufferStart = PeiCpuMpData->WakeupBuffer;\r
- ExchangeInfo->ModeOffset = PeiCpuMpData->AddressMap.ModeEntryOffset;\r
- ExchangeInfo->Cr3 = AsmReadCr3 ();\r
- ExchangeInfo->CodeSegment = AsmReadCs ();\r
- ExchangeInfo->DataSegment = AsmReadDs ();\r
- ExchangeInfo->CFunction = (UINTN) ApCFunction;\r
- ExchangeInfo->NumApsExecuting = 0;\r
- ExchangeInfo->PeiCpuMpData = PeiCpuMpData;\r
-\r
- //\r
- // Get the BSP's data of GDT and IDT\r
- //\r
- AsmReadGdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->GdtrProfile);\r
- AsmReadIdtr ((IA32_DESCRIPTOR *) &ExchangeInfo->IdtrProfile);\r
-\r
- if (PeiCpuMpData->ApLoopMode == ApInMwaitLoop) {\r
- //\r
- // Get AP target C-state each time when waking up AP,\r
- // for it maybe updated by platform again\r
- //\r
- PeiCpuMpData->ApTargetCState = PcdGet8 (PcdCpuApTargetCstate);\r
- }\r
-\r
- //\r
- // Wakeup APs per AP loop state\r
- //\r
- if (PeiCpuMpData->ApLoopMode == ApInHltLoop || PeiCpuMpData->InitFlag) {\r
- if (Broadcast) {\r
- SendInitSipiSipiAllExcludingSelf ((UINT32) ExchangeInfo->BufferStart);\r
- } else {\r
- SendInitSipiSipi (\r
- PeiCpuMpData->CpuData[ProcessorNumber].ApicId,\r
- (UINT32) ExchangeInfo->BufferStart\r
- );\r
- }\r
- } else if ((PeiCpuMpData->ApLoopMode == ApInMwaitLoop) ||\r
- (PeiCpuMpData->ApLoopMode == ApInRunLoop)) {\r
- if (Broadcast) {\r
- for (Index = 0; Index < PeiCpuMpData->CpuCount; Index++) {\r
- if (Index != PeiCpuMpData->BspNumber) {\r
- WriteStartupSignal (PeiCpuMpData->CpuData[Index].StartupApSignal);\r
- }\r
- }\r
- } else {\r
- WriteStartupSignal (PeiCpuMpData->CpuData[ProcessorNumber].StartupApSignal);\r
- }\r
- } else {\r
- ASSERT (FALSE);\r
- }\r
- return ;\r
-}\r
-\r
-/**\r
- Get available system memory below 1MB by specified size.\r
-\r
- @param WakeupBufferSize Wakeup buffer size required\r
-\r
- @retval other Return wakeup buffer address below 1MB.\r
- @retval -1 Cannot find free memory below 1MB.\r
-**/\r
-STATIC\r
-UINTN\r
-GetWakeupBuffer (\r
- IN UINTN WakeupBufferSize\r
- )\r
-{\r
- EFI_PEI_HOB_POINTERS Hob;\r
- UINTN WakeupBufferStart;\r
- UINTN WakeupBufferEnd;\r
-\r
- //\r
- // Get the HOB list for processing\r
- //\r
- Hob.Raw = GetHobList ();\r
-\r
- //\r
- // Collect memory ranges\r
- //\r
- while (!END_OF_HOB_LIST (Hob)) {\r
- if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {\r
- if ((Hob.ResourceDescriptor->PhysicalStart < BASE_1MB) &&\r
- (Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) &&\r
- ((Hob.ResourceDescriptor->ResourceAttribute &\r
- (EFI_RESOURCE_ATTRIBUTE_READ_PROTECTED |\r
- EFI_RESOURCE_ATTRIBUTE_WRITE_PROTECTED |\r
- EFI_RESOURCE_ATTRIBUTE_EXECUTION_PROTECTED\r
- )) == 0)\r
- ) {\r
- //\r
- // Need memory under 1MB to be collected here\r
- //\r
- WakeupBufferEnd = (UINTN) (Hob.ResourceDescriptor->PhysicalStart + Hob.ResourceDescriptor->ResourceLength);\r
- if (WakeupBufferEnd > BASE_1MB) {\r
- //\r
- // Wakeup buffer should be under 1MB\r
- //\r
- WakeupBufferEnd = BASE_1MB;\r
- }\r
- //\r
- // Wakeup buffer should be aligned on 4KB\r
- //\r
- WakeupBufferStart = (WakeupBufferEnd - WakeupBufferSize) & ~(SIZE_4KB - 1);\r
- if (WakeupBufferStart < Hob.ResourceDescriptor->PhysicalStart) {\r
- continue;\r
- }\r
- //\r
- // Create a memory allocation HOB.\r
- //\r
- BuildMemoryAllocationHob (\r
- WakeupBufferStart,\r
- WakeupBufferSize,\r
- EfiBootServicesData\r
- );\r
- return WakeupBufferStart;\r
- }\r
- }\r
- //\r
- // Find the next HOB\r
- //\r
- Hob.Raw = GET_NEXT_HOB (Hob);\r
- }\r
-\r
- return (UINTN) -1;\r
-}\r
-\r
-/**\r
- Get available system memory below 1MB by specified size.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
-**/\r
-STATIC\r
-VOID\r
-BackupAndPrepareWakeupBuffer(\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData\r
- )\r
-{\r
- CopyMem (\r
- (VOID *) PeiCpuMpData->BackupBuffer,\r
- (VOID *) PeiCpuMpData->WakeupBuffer,\r
- PeiCpuMpData->BackupBufferSize\r
- );\r
- CopyMem (\r
- (VOID *) PeiCpuMpData->WakeupBuffer,\r
- (VOID *) PeiCpuMpData->AddressMap.RendezvousFunnelAddress,\r
- PeiCpuMpData->AddressMap.RendezvousFunnelSize\r
- );\r
-}\r
-\r
-/**\r
- Restore wakeup buffer data.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
-**/\r
-STATIC\r
-VOID\r
-RestoreWakeupBuffer(\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData\r
- )\r
-{\r
- CopyMem ((VOID *) PeiCpuMpData->WakeupBuffer, (VOID *) PeiCpuMpData->BackupBuffer, PeiCpuMpData->BackupBufferSize);\r
-}\r
-\r
-/**\r
- This function will get CPU count in the system.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
-\r
- @return AP processor count\r
-**/\r
-UINT32\r
-CountProcessorNumber (\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData\r
- )\r
-{\r
- //\r
- // Load Microcode on BSP\r
- //\r
- MicrocodeDetect (PeiCpuMpData);\r
- //\r
- // Store BSP's MTRR setting\r
- //\r
- MtrrGetAllMtrrs (&PeiCpuMpData->MtrrTable);\r
-\r
- //\r
- // Only perform AP detection if PcdCpuMaxLogicalProcessorNumber is greater than 1\r
- //\r
- if (PcdGet32 (PcdCpuMaxLogicalProcessorNumber) > 1) {\r
- //\r
- // Send 1st broadcast IPI to APs to wakeup APs\r
- //\r
- PeiCpuMpData->InitFlag = TRUE;\r
- PeiCpuMpData->X2ApicEnable = FALSE;\r
- WakeUpAP (PeiCpuMpData, TRUE, 0, NULL, NULL);\r
- //\r
- // Wait for AP task to complete and then exit.\r
- //\r
- MicroSecondDelay (PcdGet32 (PcdCpuApInitTimeOutInMicroSeconds));\r
- PeiCpuMpData->InitFlag = FALSE;\r
- PeiCpuMpData->CpuCount += (UINT32)PeiCpuMpData->MpCpuExchangeInfo->NumApsExecuting;\r
- ASSERT (PeiCpuMpData->CpuCount <= PcdGet32 (PcdCpuMaxLogicalProcessorNumber));\r
- //\r
- // Wait for all APs finished the initialization\r
- //\r
- while (PeiCpuMpData->FinishedCount < (PeiCpuMpData->CpuCount - 1)) {\r
- CpuPause ();\r
- }\r
-\r
- if (PeiCpuMpData->X2ApicEnable) {\r
- DEBUG ((EFI_D_INFO, "Force x2APIC mode!\n"));\r
- //\r
- // Wakeup all APs to enable x2APIC mode\r
- //\r
- WakeUpAP (PeiCpuMpData, TRUE, 0, ApFuncEnableX2Apic, NULL);\r
- //\r
- // Wait for all known APs finished\r
- //\r
- while (PeiCpuMpData->FinishedCount < (PeiCpuMpData->CpuCount - 1)) {\r
- CpuPause ();\r
- }\r
- //\r
- // Enable x2APIC on BSP\r
- //\r
- SetApicMode (LOCAL_APIC_MODE_X2APIC);\r
- }\r
- DEBUG ((EFI_D_INFO, "APIC MODE is %d\n", GetApicMode ()));\r
- //\r
- // Sort BSP/Aps by CPU APIC ID in ascending order\r
- //\r
- SortApicId (PeiCpuMpData);\r
- }\r
-\r
- DEBUG ((EFI_D_INFO, "CpuMpPei: Find %d processors in system.\n", PeiCpuMpData->CpuCount));\r
- return PeiCpuMpData->CpuCount;\r
-}\r
-\r
-/**\r
- Prepare for AP wakeup buffer and copy AP reset code into it.\r
-\r
- Get wakeup buffer below 1MB. Allocate memory for CPU MP Data and APs Stack.\r
-\r
- @return Pointer to PEI CPU MP Data\r
-**/\r
-PEI_CPU_MP_DATA *\r
-PrepareAPStartupVector (\r
- VOID\r
- )\r
-{\r
- EFI_STATUS Status;\r
- UINT32 MaxCpuCount;\r
- PEI_CPU_MP_DATA *PeiCpuMpData;\r
- EFI_PHYSICAL_ADDRESS Buffer;\r
- UINTN BufferSize;\r
- UINTN WakeupBuffer;\r
- UINTN WakeupBufferSize;\r
- MP_ASSEMBLY_ADDRESS_MAP AddressMap;\r
- UINT8 ApLoopMode;\r
- UINT16 MonitorFilterSize;\r
- UINT8 *MonitorBuffer;\r
- UINTN Index;\r
-\r
- AsmGetAddressMap (&AddressMap);\r
- WakeupBufferSize = AddressMap.RendezvousFunnelSize + sizeof (MP_CPU_EXCHANGE_INFO);\r
- WakeupBuffer = GetWakeupBuffer ((WakeupBufferSize + SIZE_4KB - 1) & ~(SIZE_4KB - 1));\r
- ASSERT (WakeupBuffer != (UINTN) -1);\r
- DEBUG ((EFI_D_INFO, "CpuMpPei: WakeupBuffer = 0x%x\n", WakeupBuffer));\r
-\r
- //\r
- // Allocate Pages for APs stack, CPU MP Data, backup buffer for wakeup buffer,\r
- // and monitor buffer if required.\r
- //\r
- MaxCpuCount = PcdGet32(PcdCpuMaxLogicalProcessorNumber);\r
- BufferSize = PcdGet32 (PcdCpuApStackSize) * MaxCpuCount + sizeof (PEI_CPU_MP_DATA)\r
- + WakeupBufferSize + sizeof (PEI_CPU_DATA) * MaxCpuCount;\r
- ApLoopMode = GetApLoopMode (&MonitorFilterSize);\r
- BufferSize += MonitorFilterSize * MaxCpuCount;\r
- Status = PeiServicesAllocatePages (\r
- EfiBootServicesData,\r
- EFI_SIZE_TO_PAGES (BufferSize),\r
- &Buffer\r
- );\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- PeiCpuMpData = (PEI_CPU_MP_DATA *) (UINTN) (Buffer + PcdGet32 (PcdCpuApStackSize) * MaxCpuCount);\r
- PeiCpuMpData->Buffer = (UINTN) Buffer;\r
- PeiCpuMpData->CpuApStackSize = PcdGet32 (PcdCpuApStackSize);\r
- PeiCpuMpData->WakeupBuffer = WakeupBuffer;\r
- PeiCpuMpData->BackupBuffer = (UINTN)PeiCpuMpData + sizeof (PEI_CPU_MP_DATA);\r
- PeiCpuMpData->BackupBufferSize = WakeupBufferSize;\r
- PeiCpuMpData->MpCpuExchangeInfo = (MP_CPU_EXCHANGE_INFO *) (UINTN) (WakeupBuffer + AddressMap.RendezvousFunnelSize);\r
-\r
- PeiCpuMpData->CpuCount = 1;\r
- PeiCpuMpData->BspNumber = 0;\r
- PeiCpuMpData->CpuData = (PEI_CPU_DATA *) (PeiCpuMpData->BackupBuffer +\r
- PeiCpuMpData->BackupBufferSize);\r
- PeiCpuMpData->CpuData[0].ApicId = GetInitialApicId ();\r
- PeiCpuMpData->CpuData[0].Health.Uint32 = 0;\r
- PeiCpuMpData->EndOfPeiFlag = FALSE;\r
- InitializeSpinLock(&PeiCpuMpData->MpLock);\r
- SaveVolatileRegisters (&PeiCpuMpData->CpuData[0].VolatileRegisters);\r
- CopyMem (&PeiCpuMpData->AddressMap, &AddressMap, sizeof (MP_ASSEMBLY_ADDRESS_MAP));\r
- //\r
- // Initialize AP loop mode\r
- //\r
- PeiCpuMpData->ApLoopMode = ApLoopMode;\r
- DEBUG ((EFI_D_INFO, "AP Loop Mode is %d\n", PeiCpuMpData->ApLoopMode));\r
- MonitorBuffer = (UINT8 *)(PeiCpuMpData->CpuData + MaxCpuCount);\r
- if (PeiCpuMpData->ApLoopMode != ApInHltLoop) {\r
- //\r
- // Set up APs wakeup signal buffer\r
- //\r
- for (Index = 0; Index < MaxCpuCount; Index++) {\r
- PeiCpuMpData->CpuData[Index].StartupApSignal = \r
- (UINT32 *)(MonitorBuffer + MonitorFilterSize * Index);\r
- }\r
- }\r
- //\r
- // Backup original data and copy AP reset code in it\r
- //\r
- BackupAndPrepareWakeupBuffer(PeiCpuMpData);\r
-\r
- return PeiCpuMpData;\r
-}\r
-\r
-/**\r
- Notify function on End Of Pei PPI.\r
-\r
- On S3 boot, this function will restore wakeup buffer data.\r
- On normal boot, this function will flag wakeup buffer to be un-used type.\r
-\r
- @param PeiServices The pointer to the PEI Services Table.\r
- @param NotifyDescriptor Address of the notification descriptor data structure.\r
- @param Ppi Address of the PPI that was installed.\r
-\r
- @retval EFI_SUCCESS When everything is OK.\r
-\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMpEndOfPeiCallback (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
- IN VOID *Ppi\r
- )\r
-{\r
- EFI_STATUS Status;\r
- EFI_BOOT_MODE BootMode;\r
- PEI_CPU_MP_DATA *PeiCpuMpData;\r
- EFI_PEI_HOB_POINTERS Hob;\r
- EFI_HOB_MEMORY_ALLOCATION *MemoryHob;\r
-\r
- DEBUG ((EFI_D_INFO, "CpuMpPei: CpuMpEndOfPeiCallback () invoked\n"));\r
-\r
- Status = PeiServicesGetBootMode (&BootMode);\r
- ASSERT_EFI_ERROR (Status);\r
-\r
- PeiCpuMpData = GetMpHobData ();\r
- ASSERT (PeiCpuMpData != NULL);\r
-\r
- if (BootMode != BOOT_ON_S3_RESUME) {\r
- //\r
- // Get the HOB list for processing\r
- //\r
- Hob.Raw = GetHobList ();\r
- //\r
- // Collect memory ranges\r
- //\r
- while (!END_OF_HOB_LIST (Hob)) {\r
- if (Hob.Header->HobType == EFI_HOB_TYPE_MEMORY_ALLOCATION) {\r
- MemoryHob = Hob.MemoryAllocation;\r
- if(MemoryHob->AllocDescriptor.MemoryBaseAddress == PeiCpuMpData->WakeupBuffer) {\r
- //\r
- // Flag this HOB type to un-used\r
- //\r
- GET_HOB_TYPE (Hob) = EFI_HOB_TYPE_UNUSED;\r
- break;\r
- }\r
- }\r
- Hob.Raw = GET_NEXT_HOB (Hob);\r
- }\r
- } else {\r
- RestoreWakeupBuffer (PeiCpuMpData);\r
- PeiCpuMpData->EndOfPeiFlag = TRUE;\r
- }\r
- return EFI_SUCCESS;\r
-}\r
-\r
/**\r
The Entry point of the MP CPU PEIM.\r
\r
#include <Ppi/SecPlatformInformation.h>\r
#include <Ppi/SecPlatformInformation2.h>\r
#include <Ppi/EndOfPeiPhase.h>\r
-#include <Ppi/VectorHandoffInfo.h>\r
-\r
-#include <Register/Cpuid.h>\r
-#include <Register/LocalApic.h>\r
-#include <Register/Msr.h>\r
\r
#include <Library/BaseLib.h>\r
-#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/LocalApicLib.h>\r
-#include <Library/MtrrLib.h>\r
-#include <Library/PcdLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/ReportStatusCodeLib.h>\r
-#include <Library/SynchronizationLib.h>\r
-#include <Library/TimerLib.h>\r
-#include <Library/UefiCpuLib.h>\r
-#include <Library/CpuLib.h>\r
#include <Library/CpuExceptionHandlerLib.h>\r
#include <Library/MpInitLib.h>\r
\r
-#include "Microcode.h"\r
-\r
-//\r
-// AP state\r
-//\r
-typedef enum {\r
- CpuStateIdle,\r
- CpuStateBusy,\r
- CpuStateDisabled\r
-} CPU_STATE;\r
-\r
-#define WAKEUP_AP_SIGNAL SIGNATURE_32 ('S', 'T', 'A', 'P')\r
-\r
-typedef enum {\r
- ApInHltLoop = 1,\r
- ApInMwaitLoop = 2,\r
- ApInRunLoop = 3\r
-} AP_LOOP_MODE;\r
-\r
-//\r
-// AP reset code information\r
-//\r
-typedef struct {\r
- UINT8 *RendezvousFunnelAddress;\r
- UINTN ModeEntryOffset;\r
- UINTN RendezvousFunnelSize;\r
-} MP_ASSEMBLY_ADDRESS_MAP;\r
-\r
-//\r
-// CPU exchange information for switch BSP\r
-//\r
-typedef struct {\r
- UINT8 State; // offset 0\r
- UINTN StackPointer; // offset 4 / 8\r
- IA32_DESCRIPTOR Gdtr; // offset 8 / 16\r
- IA32_DESCRIPTOR Idtr; // offset 14 / 26\r
-} CPU_EXCHANGE_ROLE_INFO;\r
-\r
-typedef struct _PEI_CPU_MP_DATA PEI_CPU_MP_DATA;\r
-\r
-#pragma pack(1)\r
-\r
-//\r
-// MP CPU exchange information for AP reset code\r
-// This structure is required to be packed because fixed field offsets\r
-// into this structure are used in assembly code in this module\r
-//\r
-typedef struct {\r
- UINTN Lock;\r
- UINTN StackStart;\r
- UINTN StackSize;\r
- UINTN CFunction;\r
- IA32_DESCRIPTOR GdtrProfile;\r
- IA32_DESCRIPTOR IdtrProfile;\r
- UINTN BufferStart;\r
- UINTN ModeOffset;\r
- UINTN NumApsExecuting;\r
- UINTN CodeSegment;\r
- UINTN DataSegment;\r
- UINTN Cr3;\r
- PEI_CPU_MP_DATA *PeiCpuMpData;\r
-} MP_CPU_EXCHANGE_INFO;\r
-\r
-#pragma pack()\r
-\r
-typedef struct {\r
- UINTN Cr0;\r
- UINTN Cr3;\r
- UINTN Cr4;\r
- UINTN Dr0;\r
- UINTN Dr1;\r
- UINTN Dr2;\r
- UINTN Dr3;\r
- UINTN Dr6;\r
- UINTN Dr7;\r
-} CPU_VOLATILE_REGISTERS;\r
-\r
-typedef struct {\r
- volatile UINT32 *StartupApSignal;\r
- UINT32 ApicId;\r
- EFI_HEALTH_FLAGS Health;\r
- CPU_STATE State;\r
- BOOLEAN CpuHealthy;\r
- CPU_VOLATILE_REGISTERS VolatileRegisters;\r
-} PEI_CPU_DATA;\r
-\r
-//\r
-// PEI CPU MP Data save in memory\r
-//\r
-struct _PEI_CPU_MP_DATA {\r
- SPIN_LOCK MpLock;\r
- UINT32 CpuCount;\r
- UINT32 BspNumber;\r
- UINTN Buffer;\r
- UINTN CpuApStackSize;\r
- MP_ASSEMBLY_ADDRESS_MAP AddressMap;\r
- UINTN WakeupBuffer;\r
- UINTN BackupBuffer;\r
- UINTN BackupBufferSize;\r
- UINTN ApFunction;\r
- UINTN ApFunctionArgument;\r
- volatile UINT32 FinishedCount;\r
- BOOLEAN EndOfPeiFlag;\r
- BOOLEAN InitFlag;\r
- BOOLEAN X2ApicEnable;\r
- CPU_EXCHANGE_ROLE_INFO BSPInfo;\r
- CPU_EXCHANGE_ROLE_INFO APInfo;\r
- MTRR_SETTINGS MtrrTable;\r
- UINT8 ApLoopMode;\r
- UINT8 ApTargetCState;\r
- PEI_CPU_DATA *CpuData;\r
- volatile MP_CPU_EXCHANGE_INFO *MpCpuExchangeInfo;\r
-};\r
extern EFI_PEI_PPI_DESCRIPTOR mPeiCpuMpPpiDesc;\r
\r
\r
-/**\r
- Assembly code to get starting address and size of the rendezvous entry for APs.\r
- Information for fixing a jump instruction in the code is also returned.\r
-\r
- @param AddressMap Output buffer for address map information.\r
-**/\r
-VOID\r
-EFIAPI\r
-AsmGetAddressMap (\r
- OUT MP_ASSEMBLY_ADDRESS_MAP *AddressMap\r
- );\r
-\r
-/**\r
- Assembly code to load GDT table and update segment accordingly.\r
-\r
- @param Gdtr Pointer to GDT descriptor\r
-**/\r
-VOID\r
-EFIAPI\r
-AsmInitializeGdt (\r
- IN IA32_DESCRIPTOR *Gdtr\r
- );\r
-\r
-/**\r
- Get available system memory below 1MB by specified size.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
-**/\r
-STATIC\r
-VOID\r
-BackupAndPrepareWakeupBuffer(\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData\r
- );\r
-\r
-/**\r
- Restore wakeup buffer data.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
-**/\r
-STATIC\r
-VOID\r
-RestoreWakeupBuffer(\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData\r
- );\r
-\r
-/**\r
- Notify function on End Of Pei PPI.\r
-\r
- On S3 boot, this function will restore wakeup buffer data.\r
- On normal boot, this function will flag wakeup buffer to be un-used type.\r
-\r
- @param PeiServices The pointer to the PEI Services Table.\r
- @param NotifyDescriptor Address of the notification descriptor data structure.\r
- @param Ppi Address of the PPI that was installed.\r
-\r
- @retval EFI_SUCCESS When everything is OK.\r
-\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-EFIAPI\r
-CpuMpEndOfPeiCallback (\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,\r
- IN VOID *Ppi\r
- );\r
-\r
-/**\r
- This function will be called by BSP to wakeup AP.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
- @param Broadcast TRUE: Send broadcast IPI to all APs\r
- FALSE: Send IPI to AP by ApicId\r
- @param ProcessorNumber The handle number of specified processor\r
- @param Procedure The function to be invoked by AP\r
- @param ProcedureArgument The argument to be passed into AP function\r
-**/\r
-STATIC\r
-VOID\r
-WakeUpAP (\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData,\r
- IN BOOLEAN Broadcast,\r
- IN UINTN ProcessorNumber,\r
- IN EFI_AP_PROCEDURE Procedure, OPTIONAL\r
- IN VOID *ProcedureArgument OPTIONAL\r
- );\r
-\r
-/**\r
- Get CPU MP Data pointer from the Guided HOB.\r
-\r
- @return Pointer to Pointer to PEI CPU MP Data\r
-**/\r
-PEI_CPU_MP_DATA *\r
-GetMpHobData (\r
- VOID\r
- );\r
-\r
-/**\r
- Find the current Processor number by APIC ID.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
- @param ProcessorNumber Return the pocessor number found\r
-\r
- @retval EFI_SUCCESS ProcessorNumber is found and returned.\r
- @retval EFI_NOT_FOUND ProcessorNumber is not found.\r
-**/\r
-STATIC\r
-EFI_STATUS\r
-GetProcessorNumber (\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData,\r
- OUT UINTN *ProcessorNumber\r
- );\r
-\r
/**\r
Collects BIST data from PPI.\r
\r
OUT EFI_SEC_PLATFORM_INFORMATION_RECORD2 *PlatformInformationRecord2\r
);\r
\r
-/**\r
- Detect whether specified processor can find matching microcode patch and load it.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
-**/\r
-VOID\r
-MicrocodeDetect (\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData\r
- );\r
-\r
#endif\r
CpuMpPei.h\r
CpuMpPei.c\r
CpuBist.c\r
- Microcode.h\r
- Microcode.c\r
PeiMpServices.h\r
PeiMpServices.c\r
\r
-[Sources.IA32]\r
- Ia32/MpEqu.inc\r
- Ia32/MpFuncs.asm\r
- Ia32/MpFuncs.nasm\r
-\r
-[Sources.X64]\r
- X64/MpEqu.inc\r
- X64/MpFuncs.asm\r
- X64/MpFuncs.nasm\r
-\r
[Packages]\r
MdePkg/MdePkg.dec\r
MdeModulePkg/MdeModulePkg.dec\r
\r
[LibraryClasses]\r
BaseLib\r
- BaseMemoryLib\r
DebugLib\r
HobLib\r
LocalApicLib\r
- MtrrLib\r
- PcdLib\r
PeimEntryPoint\r
PeiServicesLib\r
ReportStatusCodeLib\r
- SynchronizationLib\r
- TimerLib\r
- UefiCpuLib\r
- CpuLib\r
CpuExceptionHandlerLib\r
MpInitLib\r
\r
[Ppis]\r
gEfiPeiMpServicesPpiGuid ## PRODUCES\r
- gEfiEndOfPeiSignalPpiGuid ## NOTIFY\r
gEfiSecPlatformInformationPpiGuid ## SOMETIMES_CONSUMES\r
## SOMETIMES_CONSUMES\r
## SOMETIMES_PRODUCES\r
gEfiSecPlatformInformation2PpiGuid\r
gEfiVectorHandoffInfoPpiGuid ## SOMETIMES_CONSUMES\r
\r
-[Pcd]\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber ## CONSUMES\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds ## CONSUMES\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuApStackSize ## CONSUMES\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress ## CONSUMES\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize ## CONSUMES\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode ## CONSUMES\r
- gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate ## SOMETIMES_CONSUMES\r
-\r
[Depex]\r
gEfiPeiMemoryDiscoveredPpiGuid\r
\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; MpEqu.inc\r
-;\r
-; Abstract:\r
-;\r
-; This is the equates file for Multiple Processor support\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-VacantFlag equ 00h\r
-NotVacantFlag equ 0ffh\r
-\r
-CPU_SWITCH_STATE_IDLE equ 0\r
-CPU_SWITCH_STATE_STORED equ 1\r
-CPU_SWITCH_STATE_LOADED equ 2\r
-\r
-LockLocation equ (RendezvousFunnelProcEnd - RendezvousFunnelProcStart)\r
-StackStartAddressLocation equ LockLocation + 04h\r
-StackSizeLocation equ LockLocation + 08h\r
-ApProcedureLocation equ LockLocation + 0Ch\r
-GdtrLocation equ LockLocation + 10h\r
-IdtrLocation equ LockLocation + 16h\r
-BufferStartLocation equ LockLocation + 1Ch\r
-ModeOffsetLocation equ LockLocation + 20h\r
-NumApsExecutingLoction equ LockLocation + 24h\r
-CodeSegmentLocation equ LockLocation + 28h\r
-DataSegmentLocation equ LockLocation + 2Ch\r
-\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; MpFuncs32.asm\r
-;\r
-; Abstract:\r
-;\r
-; This is the assembly code for MP support\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-.686p\r
-.model flat\r
-\r
-include MpEqu.inc\r
-InitializeFloatingPointUnits PROTO C\r
-\r
-.code\r
-\r
-;-------------------------------------------------------------------------------------\r
-;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
-;procedure serializes all the AP processors through an Init sequence. It must be\r
-;noted that APs arrive here very raw...ie: real mode, no stack.\r
-;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
-;IS IN MACHINE CODE.\r
-;-------------------------------------------------------------------------------------\r
-RendezvousFunnelProc PROC PUBLIC\r
-RendezvousFunnelProcStart::\r
-; At this point CS = 0x(vv00) and ip= 0x0.\r
-; Save BIST information to ebp firstly\r
- db 66h, 08bh, 0e8h ; mov ebp, eax ; save BIST information\r
-\r
- db 8ch,0c8h ; mov ax, cs\r
- db 8eh,0d8h ; mov ds, ax\r
- db 8eh,0c0h ; mov es, ax\r
- db 8eh,0d0h ; mov ss, ax\r
- db 33h,0c0h ; xor ax, ax\r
- db 8eh,0e0h ; mov fs, ax\r
- db 8eh,0e8h ; mov gs, ax\r
-\r
- db 0BEh ; opcode of mov si, mem16\r
- dw BufferStartLocation ; mov si, BufferStartLocation\r
- db 66h, 8Bh, 1Ch ; mov ebx, dword ptr [si]\r
-\r
- db 0BEh ; opcode of mov si, mem16\r
- dw ModeOffsetLocation ; mov si, ModeOffsetLocation\r
- db 66h, 8Bh, 04h ; mov eax, [si]\r
- db 0BEh ; opcode of mov si, mem16\r
- dw CodeSegmentLocation ; mov si, CodeSegmentLocation\r
- db 66h, 8Bh, 14h ; mov edx, [si]\r
- db 89h, 0C7h ; mov di, ax\r
- db 83h, 0EFh, 02h ; sub di, 02h\r
- db 89h, 15h ; mov [di], dx\r
- db 83h, 0EFh, 04h ; sub di, 04h\r
- db 66h, 01h, 0D8h ; add eax, ebx\r
- db 66h, 89h, 05h ; mov [di], eax\r
-\r
- db 0BEh ; opcode of mov si, mem16\r
- dw DataSegmentLocation ; mov si, DataSegmentLocation\r
- db 66h, 8Bh, 14h ; mov edx, [si]\r
-\r
- db 0BEh ; opcode of mov si, mem16\r
- dw GdtrLocation ; mov si, GdtrLocation\r
- db 66h ; db 66h\r
- db 2Eh, 0Fh, 01h, 14h ; lgdt fword ptr cs:[si]\r
-\r
- db 0BEh\r
- dw IdtrLocation ; mov si, IdtrLocation\r
- db 66h ; db 66h\r
- db 2Eh,0Fh, 01h, 1Ch ; lidt fword ptr cs:[si]\r
-\r
- db 33h, 0C0h ; xor ax, ax\r
- db 8Eh, 0D8h ; mov ds, ax\r
-\r
- db 0Fh, 20h, 0C0h ; mov eax, cr0 ;Get control register 0\r
- db 66h, 83h, 0C8h, 03h ; or eax, 000000003h ;Set PE bit (bit #0) & MP\r
- db 0Fh, 22h, 0C0h ; mov cr0, eax\r
-\r
- db 66h, 67h, 0EAh ; far jump\r
- dd 0h ; 32-bit offset\r
- dw 0h ; 16-bit selector\r
-\r
-Flat32Start:: ; protected mode entry point\r
- mov ds, dx\r
- mov es, dx\r
- mov fs, dx\r
- mov gs, dx\r
- mov ss, dx\r
-\r
- mov esi, ebx\r
- mov edi, esi\r
- add edi, LockLocation\r
- mov eax, NotVacantFlag\r
-\r
-TestLock:\r
- xchg dword ptr [edi], eax\r
- cmp eax, NotVacantFlag\r
- jz TestLock\r
-\r
- mov edi, esi\r
- add edi, NumApsExecutingLoction\r
- inc dword ptr [edi]\r
- mov ebx, dword ptr [edi]\r
-\r
-ProgramStack:\r
- mov edi, esi\r
- add edi, StackSizeLocation\r
- mov eax, dword ptr [edi]\r
- mov edi, esi\r
- add edi, StackStartAddressLocation\r
- add eax, dword ptr [edi]\r
- mov esp, eax\r
- mov dword ptr [edi], eax\r
-\r
-Releaselock:\r
- mov eax, VacantFlag\r
- mov edi, esi\r
- add edi, LockLocation\r
- xchg dword ptr [edi], eax\r
-\r
-CProcedureInvoke:\r
- push ebp ; push BIST data at top of AP stack\r
- xor ebp, ebp ; clear ebp for call stack trace\r
- push ebp\r
- mov ebp, esp\r
-\r
- mov eax, InitializeFloatingPointUnits\r
- call eax ; Call assembly function to initialize FPU per UEFI spec\r
-\r
- push ebx ; Push NumApsExecuting\r
- mov eax, esi\r
- add eax, LockLocation\r
- push eax ; push address of exchange info data buffer\r
-\r
- mov edi, esi\r
- add edi, ApProcedureLocation\r
- mov eax, dword ptr [edi]\r
-\r
- call eax ; invoke C function\r
-\r
- jmp $ ; never reach here\r
-\r
-RendezvousFunnelProc ENDP\r
-RendezvousFunnelProcEnd::\r
-\r
-;-------------------------------------------------------------------------------------\r
-; AsmGetAddressMap (&AddressMap);\r
-;-------------------------------------------------------------------------------------\r
-AsmGetAddressMap PROC near C PUBLIC\r
- pushad\r
- mov ebp,esp\r
-\r
- mov ebx, dword ptr [ebp+24h]\r
- mov dword ptr [ebx], RendezvousFunnelProcStart\r
- mov dword ptr [ebx + 4h], Flat32Start - RendezvousFunnelProcStart\r
- mov dword ptr [ebx + 8h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
-\r
- popad\r
- ret\r
-AsmGetAddressMap ENDP\r
-\r
-PAUSE32 MACRO\r
- DB 0F3h\r
- DB 090h\r
- ENDM\r
-\r
-;-------------------------------------------------------------------------------------\r
-;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
-;about to become an AP. It switches it'stack with the current AP.\r
-;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);\r
-;-------------------------------------------------------------------------------------\r
-AsmExchangeRole PROC near C PUBLIC\r
- ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
- ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
- pushad\r
- mov ebp,esp\r
-\r
- ; esi contains MyInfo pointer\r
- mov esi, dword ptr [ebp+24h]\r
-\r
- ; edi contains OthersInfo pointer\r
- mov edi, dword ptr [ebp+28h]\r
-\r
- ;Store EFLAGS, GDTR and IDTR register to stack\r
- pushfd\r
- mov eax, cr4\r
- push eax ; push cr4 firstly\r
- mov eax, cr0\r
- push eax\r
-\r
- sgdt fword ptr [esi+8]\r
- sidt fword ptr [esi+14]\r
-\r
- ; Store the its StackPointer\r
- mov dword ptr [esi+4],esp\r
-\r
- ; update its switch state to STORED\r
- mov byte ptr [esi], CPU_SWITCH_STATE_STORED\r
-\r
-WaitForOtherStored:\r
- ; wait until the other CPU finish storing its state\r
- cmp byte ptr [edi], CPU_SWITCH_STATE_STORED\r
- jz OtherStored\r
- PAUSE32\r
- jmp WaitForOtherStored\r
-\r
-OtherStored:\r
- ; Since another CPU already stored its state, load them\r
- ; load GDTR value\r
- lgdt fword ptr [edi+8]\r
-\r
- ; load IDTR value\r
- lidt fword ptr [edi+14]\r
-\r
- ; load its future StackPointer\r
- mov esp, dword ptr [edi+4]\r
-\r
- ; update the other CPU's switch state to LOADED\r
- mov byte ptr [edi], CPU_SWITCH_STATE_LOADED\r
-\r
-WaitForOtherLoaded:\r
- ; wait until the other CPU finish loading new state,\r
- ; otherwise the data in stack may corrupt\r
- cmp byte ptr [esi], CPU_SWITCH_STATE_LOADED\r
- jz OtherLoaded\r
- PAUSE32\r
- jmp WaitForOtherLoaded\r
-\r
-OtherLoaded:\r
- ; since the other CPU already get the data it want, leave this procedure\r
- pop eax\r
- mov cr0, eax\r
- pop eax\r
- mov cr4, eax\r
- popfd\r
-\r
- popad\r
- ret\r
-AsmExchangeRole ENDP\r
-\r
-END\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; MpFuncs.nasm\r
-;\r
-; Abstract:\r
-;\r
-; This is the assembly code for MP support\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-%include "MpEqu.inc"\r
-extern ASM_PFX(InitializeFloatingPointUnits)\r
-\r
-SECTION .text\r
-\r
-;-------------------------------------------------------------------------------------\r
-;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
-;procedure serializes all the AP processors through an Init sequence. It must be\r
-;noted that APs arrive here very raw...ie: real mode, no stack.\r
-;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
-;IS IN MACHINE CODE.\r
-;-------------------------------------------------------------------------------------\r
-global ASM_PFX(RendezvousFunnelProc)\r
-ASM_PFX(RendezvousFunnelProc):\r
-RendezvousFunnelProcStart:\r
-; At this point CS = 0x(vv00) and ip= 0x0.\r
-BITS 16\r
- mov ebp, eax ; save BIST information\r
-\r
- mov ax, cs\r
- mov ds, ax\r
- mov es, ax\r
- mov ss, ax\r
- xor ax, ax\r
- mov fs, ax\r
- mov gs, ax\r
-\r
- mov si, BufferStartLocation\r
- mov ebx, [si]\r
-\r
- mov si, ModeOffsetLocation\r
- mov eax, [si]\r
- mov si, CodeSegmentLocation\r
- mov edx, [si]\r
- mov di, ax\r
- sub di, 02h\r
- mov [di], dx\r
- sub di, 04h\r
- add eax, ebx\r
- mov [di],eax\r
-\r
- mov si, DataSegmentLocation\r
- mov edx, [si]\r
-\r
- mov si, GdtrLocation\r
-o32 lgdt [cs:si]\r
-\r
- mov si, IdtrLocation\r
-o32 lidt [cs:si]\r
-\r
- xor ax, ax\r
- mov ds, ax\r
-\r
- mov eax, cr0 ;Get control register 0\r
- or eax, 000000003h ;Set PE bit (bit #0) & MP\r
- mov cr0, eax\r
-\r
- jmp 0:strict dword 0 ; far jump to protected mode\r
-BITS 32\r
-Flat32Start: ; protected mode entry point\r
- mov ds, dx\r
- mov es, dx\r
- mov fs, dx\r
- mov gs, dx\r
- mov ss, dx\r
-\r
- mov esi, ebx\r
- mov edi, esi\r
- add edi, LockLocation\r
- mov eax, NotVacantFlag\r
-\r
-TestLock:\r
- xchg [edi], eax\r
- cmp eax, NotVacantFlag\r
- jz TestLock\r
-\r
- mov edi, esi\r
- add edi, NumApsExecutingLoction\r
- inc dword [edi]\r
- mov ebx, [edi]\r
-\r
-ProgramStack:\r
- mov edi, esi\r
- add edi, StackSizeLocation\r
- mov eax, [edi]\r
- mov edi, esi\r
- add edi, StackStartAddressLocation\r
- add eax, [edi]\r
- mov esp, eax\r
- mov [edi], eax\r
-\r
-Releaselock:\r
- mov eax, VacantFlag\r
- mov edi, esi\r
- add edi, LockLocation\r
- xchg [edi], eax\r
-\r
-CProcedureInvoke:\r
- push ebp ; push BIST data at top of AP stack\r
- xor ebp, ebp ; clear ebp for call stack trace\r
- push ebp\r
- mov ebp, esp\r
-\r
- mov eax, ASM_PFX(InitializeFloatingPointUnits)\r
- call eax ; Call assembly function to initialize FPU per UEFI spec\r
-\r
- push ebx ; Push NumApsExecuting\r
- mov eax, esi\r
- add eax, LockLocation\r
- push eax ; push address of exchange info data buffer\r
-\r
- mov edi, esi\r
- add edi, ApProcedureLocation\r
- mov eax, [edi]\r
-\r
- call eax ; invoke C function\r
-\r
- jmp $ ; never reach here\r
-RendezvousFunnelProcEnd:\r
-\r
-;-------------------------------------------------------------------------------------\r
-; AsmGetAddressMap (&AddressMap);\r
-;-------------------------------------------------------------------------------------\r
-global ASM_PFX(AsmGetAddressMap)\r
-ASM_PFX(AsmGetAddressMap):\r
- pushad\r
- mov ebp,esp\r
-\r
- mov ebx, [ebp + 24h]\r
- mov dword [ebx], RendezvousFunnelProcStart\r
- mov dword [ebx + 4h], Flat32Start - RendezvousFunnelProcStart\r
- mov dword [ebx + 8h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
-\r
- popad\r
- ret\r
-\r
-;-------------------------------------------------------------------------------------\r
-;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
-;about to become an AP. It switches it'stack with the current AP.\r
-;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);\r
-;-------------------------------------------------------------------------------------\r
-global ASM_PFX(AsmExchangeRole)\r
-ASM_PFX(AsmExchangeRole):\r
- ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
- ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
- pushad\r
- mov ebp,esp\r
-\r
- ; esi contains MyInfo pointer\r
- mov esi, [ebp + 24h]\r
-\r
- ; edi contains OthersInfo pointer\r
- mov edi, [ebp + 28h]\r
-\r
- ;Store EFLAGS, GDTR and IDTR register to stack\r
- pushfd\r
- mov eax, cr4\r
- push eax ; push cr4 firstly\r
- mov eax, cr0\r
- push eax\r
-\r
- sgdt [esi + 8]\r
- sidt [esi + 14]\r
-\r
- ; Store the its StackPointer\r
- mov [esi + 4],esp\r
-\r
- ; update its switch state to STORED\r
- mov byte [esi], CPU_SWITCH_STATE_STORED\r
-\r
-WaitForOtherStored:\r
- ; wait until the other CPU finish storing its state\r
- cmp byte [edi], CPU_SWITCH_STATE_STORED\r
- jz OtherStored\r
- pause\r
- jmp WaitForOtherStored\r
-\r
-OtherStored:\r
- ; Since another CPU already stored its state, load them\r
- ; load GDTR value\r
- lgdt [edi + 8]\r
-\r
- ; load IDTR value\r
- lidt [edi + 14]\r
-\r
- ; load its future StackPointer\r
- mov esp, [edi + 4]\r
-\r
- ; update the other CPU's switch state to LOADED\r
- mov byte [edi], CPU_SWITCH_STATE_LOADED\r
-\r
-WaitForOtherLoaded:\r
- ; wait until the other CPU finish loading new state,\r
- ; otherwise the data in stack may corrupt\r
- cmp byte [esi], CPU_SWITCH_STATE_LOADED\r
- jz OtherLoaded\r
- pause\r
- jmp WaitForOtherLoaded\r
-\r
-OtherLoaded:\r
- ; since the other CPU already get the data it want, leave this procedure\r
- pop eax\r
- mov cr0, eax\r
- pop eax\r
- mov cr4, eax\r
- popfd\r
-\r
- popad\r
- ret\r
+++ /dev/null
-/** @file\r
- Implementation of loading microcode on processors.\r
-\r
- Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#include "CpuMpPei.h"\r
-\r
-/**\r
- Get microcode update signature of currently loaded microcode update.\r
-\r
- @return Microcode signature.\r
-\r
-**/\r
-UINT32\r
-GetCurrentMicrocodeSignature (\r
- VOID\r
- )\r
-{\r
- UINT64 Signature;\r
-\r
- AsmWriteMsr64 (EFI_MSR_IA32_BIOS_SIGN_ID, 0);\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, NULL);\r
- Signature = AsmReadMsr64 (EFI_MSR_IA32_BIOS_SIGN_ID);\r
- return (UINT32) RShiftU64 (Signature, 32);\r
-}\r
-\r
-/**\r
- Detect whether specified processor can find matching microcode patch and load it.\r
-\r
- @param PeiCpuMpData Pointer to PEI CPU MP Data\r
-**/\r
-VOID\r
-MicrocodeDetect (\r
- IN PEI_CPU_MP_DATA *PeiCpuMpData\r
- )\r
-{\r
- UINT64 MicrocodePatchAddress;\r
- UINT64 MicrocodePatchRegionSize;\r
- UINT32 ExtendedTableLength;\r
- UINT32 ExtendedTableCount;\r
- EFI_CPU_MICROCODE_EXTENDED_TABLE *ExtendedTable;\r
- EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER *ExtendedTableHeader;\r
- EFI_CPU_MICROCODE_HEADER *MicrocodeEntryPoint;\r
- UINTN MicrocodeEnd;\r
- UINTN Index;\r
- UINT8 PlatformId;\r
- UINT32 RegEax;\r
- UINT32 CurrentRevision;\r
- UINT32 LatestRevision;\r
- UINTN TotalSize;\r
- UINT32 CheckSum32;\r
- BOOLEAN CorrectMicrocode;\r
- MICROCODE_INFO MicrocodeInfo;\r
-\r
- ZeroMem (&MicrocodeInfo, sizeof (MICROCODE_INFO));\r
- MicrocodePatchAddress = PcdGet64 (PcdCpuMicrocodePatchAddress);\r
- MicrocodePatchRegionSize = PcdGet64 (PcdCpuMicrocodePatchRegionSize);\r
- if (MicrocodePatchRegionSize == 0) {\r
- //\r
- // There is no microcode patches\r
- //\r
- return;\r
- }\r
-\r
- CurrentRevision = GetCurrentMicrocodeSignature ();\r
- if (CurrentRevision != 0) {\r
- //\r
- // Skip loading microcode if it has been loaded successfully\r
- //\r
- return;\r
- }\r
-\r
- ExtendedTableLength = 0;\r
- //\r
- // Here data of CPUID leafs have not been collected into context buffer, so\r
- // GetProcessorCpuid() cannot be used here to retrieve CPUID data.\r
- //\r
- AsmCpuid (CPUID_VERSION_INFO, &RegEax, NULL, NULL, NULL);\r
-\r
- //\r
- // The index of platform information resides in bits 50:52 of MSR IA32_PLATFORM_ID\r
- //\r
- PlatformId = (UINT8) AsmMsrBitFieldRead64 (EFI_MSR_IA32_PLATFORM_ID, 50, 52);\r
-\r
- LatestRevision = 0;\r
- MicrocodeEnd = (UINTN) (MicrocodePatchAddress + MicrocodePatchRegionSize);\r
- MicrocodeEntryPoint = (EFI_CPU_MICROCODE_HEADER *) (UINTN) MicrocodePatchAddress;\r
- do {\r
- //\r
- // Check if the microcode is for the Cpu and the version is newer\r
- // and the update can be processed on the platform\r
- //\r
- CorrectMicrocode = FALSE;\r
- if (MicrocodeEntryPoint->HeaderVersion == 0x1) {\r
- //\r
- // It is the microcode header. It is not the padding data between microcode patches\r
- // because the padding data should not include 0x00000001 and it should be the repeated\r
- // byte format (like 0xXYXYXYXY....).\r
- //\r
- if (MicrocodeEntryPoint->ProcessorId == RegEax &&\r
- MicrocodeEntryPoint->UpdateRevision > LatestRevision &&\r
- (MicrocodeEntryPoint->ProcessorFlags & (1 << PlatformId))\r
- ) {\r
- if (MicrocodeEntryPoint->DataSize == 0) {\r
- CheckSum32 = CalculateSum32 ((UINT32 *)MicrocodeEntryPoint, 2048);\r
- } else {\r
- CheckSum32 = CalculateSum32 ((UINT32 *)MicrocodeEntryPoint, MicrocodeEntryPoint->DataSize + sizeof(EFI_CPU_MICROCODE_HEADER));\r
- }\r
- if (CheckSum32 == 0) {\r
- CorrectMicrocode = TRUE;\r
- }\r
- } else if ((MicrocodeEntryPoint->DataSize != 0) &&\r
- (MicrocodeEntryPoint->UpdateRevision > LatestRevision)) {\r
- ExtendedTableLength = MicrocodeEntryPoint->TotalSize - (MicrocodeEntryPoint->DataSize + sizeof (EFI_CPU_MICROCODE_HEADER));\r
- if (ExtendedTableLength != 0) {\r
- //\r
- // Extended Table exist, check if the CPU in support list\r
- //\r
- ExtendedTableHeader = (EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER *)((UINT8 *)(MicrocodeEntryPoint) + MicrocodeEntryPoint->DataSize + sizeof (EFI_CPU_MICROCODE_HEADER));\r
- //\r
- // Calculate Extended Checksum\r
- //\r
- if ((ExtendedTableLength % 4) == 0) {\r
- CheckSum32 = CalculateSum32 ((UINT32 *)ExtendedTableHeader, ExtendedTableLength);\r
- if (CheckSum32 == 0) {\r
- //\r
- // Checksum correct\r
- //\r
- ExtendedTableCount = ExtendedTableHeader->ExtendedSignatureCount;\r
- ExtendedTable = (EFI_CPU_MICROCODE_EXTENDED_TABLE *)(ExtendedTableHeader + 1);\r
- for (Index = 0; Index < ExtendedTableCount; Index ++) {\r
- CheckSum32 = CalculateSum32 ((UINT32 *)ExtendedTable, sizeof(EFI_CPU_MICROCODE_EXTENDED_TABLE));\r
- if (CheckSum32 == 0) {\r
- //\r
- // Verify Header\r
- //\r
- if ((ExtendedTable->ProcessorSignature == RegEax) &&\r
- (ExtendedTable->ProcessorFlag & (1 << PlatformId)) ) {\r
- //\r
- // Find one\r
- //\r
- CorrectMicrocode = TRUE;\r
- break;\r
- }\r
- }\r
- ExtendedTable ++;\r
- }\r
- }\r
- }\r
- }\r
- }\r
- } else {\r
- //\r
- // It is the padding data between the microcode patches for microcode patches alignment.\r
- // Because the microcode patch is the multiple of 1-KByte, the padding data should not\r
- // exist if the microcode patch alignment value is not larger than 1-KByte. So, the microcode\r
- // alignment value should be larger than 1-KByte. We could skip SIZE_1KB padding data to\r
- // find the next possible microcode patch header.\r
- //\r
- MicrocodeEntryPoint = (EFI_CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + SIZE_1KB);\r
- continue;\r
- }\r
- //\r
- // Get the next patch.\r
- //\r
- if (MicrocodeEntryPoint->DataSize == 0) {\r
- TotalSize = 2048;\r
- } else {\r
- TotalSize = MicrocodeEntryPoint->TotalSize;\r
- }\r
-\r
- if (CorrectMicrocode) {\r
- LatestRevision = MicrocodeEntryPoint->UpdateRevision;\r
- MicrocodeInfo.MicrocodeData = (VOID *)((UINTN)MicrocodeEntryPoint + sizeof (EFI_CPU_MICROCODE_HEADER));\r
- MicrocodeInfo.MicrocodeSize = TotalSize;\r
- MicrocodeInfo.ProcessorId = RegEax;\r
- }\r
-\r
- MicrocodeEntryPoint = (EFI_CPU_MICROCODE_HEADER *) (((UINTN) MicrocodeEntryPoint) + TotalSize);\r
- } while (((UINTN) MicrocodeEntryPoint < MicrocodeEnd));\r
-\r
- if (LatestRevision > CurrentRevision) {\r
- //\r
- // BIOS only authenticate updates that contain a numerically larger revision\r
- // than the currently loaded revision, where Current Signature < New Update\r
- // Revision. A processor with no loaded update is considered to have a\r
- // revision equal to zero.\r
- //\r
- AsmWriteMsr64 (\r
- EFI_MSR_IA32_BIOS_UPDT_TRIG,\r
- (UINT64) (UINTN) MicrocodeInfo.MicrocodeData\r
- );\r
- //\r
- // Get and check new microcode signature\r
- //\r
- CurrentRevision = GetCurrentMicrocodeSignature ();\r
- if (CurrentRevision != LatestRevision) {\r
- AcquireSpinLock(&PeiCpuMpData->MpLock);\r
- DEBUG ((EFI_D_ERROR, "Updated microcode signature [0x%08x] does not match \\r
- loaded microcode signature [0x%08x]\n", CurrentRevision, LatestRevision));\r
- ReleaseSpinLock(&PeiCpuMpData->MpLock);\r
- }\r
- }\r
-}\r
+++ /dev/null
-/** @file\r
- Definitions for loading microcode on processors.\r
-\r
- Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
- This program and the accompanying materials\r
- are licensed and made available under the terms and conditions of the BSD License\r
- which accompanies this distribution. The full text of the license may be found at\r
- http://opensource.org/licenses/bsd-license.php\r
-\r
- THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
- WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-\r
-**/\r
-\r
-#ifndef _CPU_MICROCODE_H_\r
-#define _CPU_MICROCODE_H_\r
-\r
-#define EFI_MSR_IA32_PLATFORM_ID 0x17\r
-#define EFI_MSR_IA32_BIOS_UPDT_TRIG 0x79\r
-#define EFI_MSR_IA32_BIOS_SIGN_ID 0x8b\r
-\r
-#define MAX_MICROCODE_DESCRIPTOR_LENGTH 100\r
-\r
-typedef struct {\r
- VOID *MicrocodeData;\r
- UINTN MicrocodeSize;\r
- UINT32 ProcessorId;\r
-} MICROCODE_INFO;\r
-\r
-//\r
-// Definition for IA32 microcode format\r
-//\r
-typedef struct {\r
- UINT32 HeaderVersion;\r
- UINT32 UpdateRevision;\r
- UINT32 Date;\r
- UINT32 ProcessorId;\r
- UINT32 Checksum;\r
- UINT32 LoaderRevision;\r
- UINT32 ProcessorFlags;\r
- UINT32 DataSize;\r
- UINT32 TotalSize;\r
- UINT8 Reserved[12];\r
-} EFI_CPU_MICROCODE_HEADER;\r
-\r
-typedef struct {\r
- UINT32 ExtendedSignatureCount;\r
- UINT32 ExtendedTableChecksum;\r
- UINT8 Reserved[12];\r
-} EFI_CPU_MICROCODE_EXTENDED_TABLE_HEADER;\r
-\r
-typedef struct {\r
- UINT32 ProcessorSignature;\r
- UINT32 ProcessorFlag;\r
- UINT32 ProcessorChecksum;\r
-} EFI_CPU_MICROCODE_EXTENDED_TABLE;\r
-\r
-#endif\r
};\r
\r
\r
-/**\r
- Get CPU Package/Core/Thread location information.\r
-\r
- @param InitialApicId CPU APIC ID\r
- @param Location Pointer to CPU location information\r
-**/\r
-STATIC\r
-VOID\r
-ExtractProcessorLocation (\r
- IN UINT32 InitialApicId,\r
- OUT EFI_CPU_PHYSICAL_LOCATION *Location\r
- )\r
-{\r
- BOOLEAN TopologyLeafSupported;\r
- UINTN ThreadBits;\r
- UINTN CoreBits;\r
- UINT32 RegEax;\r
- UINT32 RegEbx;\r
- UINT32 RegEcx;\r
- UINT32 RegEdx;\r
- UINT32 MaxCpuIdIndex;\r
- UINT32 SubIndex;\r
- UINTN LevelType;\r
- UINT32 MaxLogicProcessorsPerPackage;\r
- UINT32 MaxCoresPerPackage;\r
-\r
- //\r
- // Check if the processor is capable of supporting more than one logical processor.\r
- //\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, NULL, NULL, &RegEdx);\r
- if ((RegEdx & BIT28) == 0) {\r
- Location->Thread = 0;\r
- Location->Core = 0;\r
- Location->Package = 0;\r
- return;\r
- }\r
-\r
- ThreadBits = 0;\r
- CoreBits = 0;\r
-\r
- //\r
- // Assume three-level mapping of APIC ID: Package:Core:SMT.\r
- //\r
-\r
- TopologyLeafSupported = FALSE;\r
- //\r
- // Get the max index of basic CPUID\r
- //\r
- AsmCpuid (CPUID_SIGNATURE, &MaxCpuIdIndex, NULL, NULL, NULL);\r
-\r
- //\r
- // If the extended topology enumeration leaf is available, it\r
- // is the preferred mechanism for enumerating topology.\r
- //\r
- if (MaxCpuIdIndex >= CPUID_EXTENDED_TOPOLOGY) {\r
- AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, 0, &RegEax, &RegEbx, &RegEcx, NULL);\r
- //\r
- // If CPUID.(EAX=0BH, ECX=0H):EBX returns zero and maximum input value for\r
- // basic CPUID information is greater than 0BH, then CPUID.0BH leaf is not\r
- // supported on that processor.\r
- //\r
- if (RegEbx != 0) {\r
- TopologyLeafSupported = TRUE;\r
-\r
- //\r
- // Sub-leaf index 0 (ECX= 0 as input) provides enumeration parameters to extract\r
- // the SMT sub-field of x2APIC ID.\r
- //\r
- LevelType = (RegEcx >> 8) & 0xff;\r
- ASSERT (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT);\r
- ThreadBits = RegEax & 0x1f;\r
-\r
- //\r
- // Software must not assume any "level type" encoding\r
- // value to be related to any sub-leaf index, except sub-leaf 0.\r
- //\r
- SubIndex = 1;\r
- do {\r
- AsmCpuidEx (CPUID_EXTENDED_TOPOLOGY, SubIndex, &RegEax, NULL, &RegEcx, NULL);\r
- LevelType = (RegEcx >> 8) & 0xff;\r
- if (LevelType == CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE) {\r
- CoreBits = (RegEax & 0x1f) - ThreadBits;\r
- break;\r
- }\r
- SubIndex++;\r
- } while (LevelType != CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID);\r
- }\r
- }\r
-\r
- if (!TopologyLeafSupported) {\r
- AsmCpuid (CPUID_VERSION_INFO, NULL, &RegEbx, NULL, NULL);\r
- MaxLogicProcessorsPerPackage = (RegEbx >> 16) & 0xff;\r
- if (MaxCpuIdIndex >= CPUID_CACHE_PARAMS) {\r
- AsmCpuidEx (CPUID_CACHE_PARAMS, 0, &RegEax, NULL, NULL, NULL);\r
- MaxCoresPerPackage = (RegEax >> 26) + 1;\r
- } else {\r
- //\r
- // Must be a single-core processor.\r
- //\r
- MaxCoresPerPackage = 1;\r
- }\r
-\r
- ThreadBits = (UINTN) (HighBitSet32 (MaxLogicProcessorsPerPackage / MaxCoresPerPackage - 1) + 1);\r
- CoreBits = (UINTN) (HighBitSet32 (MaxCoresPerPackage - 1) + 1);\r
- }\r
-\r
- Location->Thread = InitialApicId & ~((-1) << ThreadBits);\r
- Location->Core = (InitialApicId >> ThreadBits) & ~((-1) << CoreBits);\r
- Location->Package = (InitialApicId >> (ThreadBits + CoreBits));\r
-}\r
-\r
-/**\r
- Worker function for SwitchBSP().\r
-\r
- Worker function for SwitchBSP(), assigned to the AP which is intended to become BSP.\r
-\r
- @param Buffer Pointer to CPU MP Data\r
-**/\r
-STATIC\r
-VOID\r
-EFIAPI\r
-FutureBSPProc (\r
- IN VOID *Buffer\r
- )\r
-{\r
- PEI_CPU_MP_DATA *DataInHob;\r
-\r
- DataInHob = (PEI_CPU_MP_DATA *) Buffer;\r
- AsmExchangeRole (&DataInHob->APInfo, &DataInHob->BSPInfo);\r
-}\r
-\r
/**\r
This service retrieves the number of logical processor in the platform\r
and the number of those logical processors that are enabled on this boot.\r
\r
#include "CpuMpPei.h"\r
\r
-//\r
-// The MP data for switch BSP\r
-//\r
-#define CPU_SWITCH_STATE_IDLE 0\r
-#define CPU_SWITCH_STATE_STORED 1\r
-#define CPU_SWITCH_STATE_LOADED 2\r
-\r
-#define CPU_CHECK_AP_INTERVAL 0x100 // 100 microseconds\r
-\r
-/**\r
- This function is called by both the BSP and the AP which is to become the BSP to\r
- Exchange execution context including stack between them. After return from this\r
- function, the BSP becomes AP and the AP becomes the BSP.\r
-\r
- @param MyInfo Pointer to buffer holding the exchanging information for the executing processor.\r
- @param OthersInfo Pointer to buffer holding the exchanging information for the peer.\r
-**/\r
-VOID\r
-EFIAPI\r
-AsmExchangeRole (\r
- IN CPU_EXCHANGE_ROLE_INFO *MyInfo,\r
- IN CPU_EXCHANGE_ROLE_INFO *OthersInfo\r
- );\r
\r
/**\r
This service retrieves the number of logical processor in the platform\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; MpEqu.inc\r
-;\r
-; Abstract:\r
-;\r
-; This is the equates file for Multiple Processor support\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-VacantFlag equ 00h\r
-NotVacantFlag equ 0ffh\r
-\r
-CPU_SWITCH_STATE_IDLE equ 0\r
-CPU_SWITCH_STATE_STORED equ 1\r
-CPU_SWITCH_STATE_LOADED equ 2\r
-\r
-LockLocation equ (RendezvousFunnelProcEnd - RendezvousFunnelProcStart)\r
-StackStartAddressLocation equ LockLocation + 08h\r
-StackSizeLocation equ LockLocation + 10h\r
-ApProcedureLocation equ LockLocation + 18h\r
-GdtrLocation equ LockLocation + 20h\r
-IdtrLocation equ LockLocation + 2Ah\r
-BufferStartLocation equ LockLocation + 34h\r
-ModeOffsetLocation equ LockLocation + 3Ch\r
-NumApsExecutingLoction equ LockLocation + 44h\r
-CodeSegmentLocation equ LockLocation + 4Ch\r
-DataSegmentLocation equ LockLocation + 54h\r
-Cr3Location equ LockLocation + 5Ch\r
-\r
-;-------------------------------------------------------------------------------\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; MpFuncs32.asm\r
-;\r
-; Abstract:\r
-;\r
-; This is the assembly code for MP support\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-include MpEqu.inc\r
-extern InitializeFloatingPointUnits:PROC\r
-\r
-.code\r
-;-------------------------------------------------------------------------------------\r
-;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
-;procedure serializes all the AP processors through an Init sequence. It must be\r
-;noted that APs arrive here very raw...ie: real mode, no stack.\r
-;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
-;IS IN MACHINE CODE.\r
-;-------------------------------------------------------------------------------------\r
-RendezvousFunnelProc PROC PUBLIC\r
-RendezvousFunnelProcStart::\r
-; At this point CS = 0x(vv00) and ip= 0x0.\r
-; Save BIST information to ebp firstly\r
- db 66h, 08bh, 0e8h ; mov ebp, eax ; save BIST information\r
-\r
- db 8ch,0c8h ; mov ax, cs\r
- db 8eh,0d8h ; mov ds, ax\r
- db 8eh,0c0h ; mov es, ax\r
- db 8eh,0d0h ; mov ss, ax\r
- db 33h,0c0h ; xor ax, ax\r
- db 8eh,0e0h ; mov fs, ax\r
- db 8eh,0e8h ; mov gs, ax\r
-\r
- db 0BEh ; opcode of mov si, mem16\r
- dw BufferStartLocation ; mov si, BufferStartLocation\r
- db 66h, 8Bh, 1Ch ; mov ebx, dword ptr [si]\r
-\r
- db 0BFh ; opcode of mov di, mem16 \r
- dw ModeOffsetLocation ; mov di, ModeOffsetLocation\r
- db 66h, 8Bh, 05h ; mov eax, [di]\r
- db 0BFh ; opcode of mov di, mem16 \r
- dw CodeSegmentLocation ; mov di, CodeSegmentLocation\r
- db 66h, 8Bh, 15h ; mov edx, [di]\r
- db 89h, 0C7h ; mov di, ax\r
- db 83h, 0EFh, 02h ; sub di, 02h \r
- db 89h, 15h ; mov [di], dx ; Patch long mode CS\r
- db 83h, 0EFh, 04h ; sub di, 04h\r
- db 66h, 01h, 0D8h ; add eax, ebx\r
- db 66h, 89h, 05h ; mov [di], eax ; Patch address\r
-\r
- db 0BEh ; opcode of mov si, mem16\r
- dw GdtrLocation ; mov si, GdtrLocation\r
- db 66h ; db 66h\r
- db 2Eh, 0Fh, 01h, 14h ; lgdt fword ptr cs:[si]\r
-\r
- db 0BEh\r
- dw IdtrLocation ; mov si, IdtrLocation\r
- db 66h ; db 66h\r
- db 2Eh,0Fh, 01h, 1Ch ; lidt fword ptr cs:[si]\r
-\r
- db 0BFh ; opcode of mov di, mem16 \r
- dw DataSegmentLocation ; mov di, DataSegmentLocation\r
- db 66h, 8Bh, 3Dh ; mov edi, [di] ; Save long mode DS in edi\r
-\r
- db 0BEh\r
- dw Cr3Location ; mov si, Cr3Location\r
- db 66h, 8Bh, 0Ch ; mov ecx, dword ptr [si] ; ECX is keeping the value of CR3\r
-\r
- db 31h, 0C0h ; xor ax, ax\r
- db 8Eh, 0D8h ; mov ds, ax ; Clear data segment\r
-\r
- db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Get control register 0\r
- db 66h, 83h, 0C8h, 03h ; or eax, 000000003h ; Set PE bit (bit #0) & MP\r
- db 0Fh, 22h, 0C0h ; mov cr0, eax\r
-\r
- db 0Fh, 20h, 0E0h ; mov eax, cr4\r
- db 66h, 0Fh, 0BAh, 0E8h, 05h ; bts eax, 5\r
- db 0Fh, 22h, 0E0h ; mov cr4, eax\r
-\r
- db 0Fh, 22h, 0D9h ; mov cr3, ecx\r
-\r
- db 66h, 0B9h\r
- dd 0C0000080h ; mov ecx, 0c0000080h ; EFER MSR number.\r
- db 0Fh, 32h ; rdmsr ; Read EFER.\r
- db 66h, 0Fh, 0BAh, 0E8h, 08h; bts eax, 8 ; Set LME=1.\r
- db 0Fh, 30h ; wrmsr ; Write EFER.\r
-\r
- db 0Fh, 20h, 0C0h ; mov eax, cr0 ; Read CR0.\r
- db 66h, 0Fh, 0BAh, 0E8h, 1Fh; bts eax, 31 ; Set PG=1.\r
- db 0Fh, 22h, 0C0h ; mov cr0, eax ; Write CR0.\r
-\r
-LONG_JUMP:\r
- db 66h, 0EAh ; far jump\r
- dd 0h ; 32-bit offset\r
- dw 0h ; 16-bit selector\r
-\r
-LongModeStart::\r
- mov eax, edi\r
- mov ds, ax\r
- mov es, ax\r
- mov ss, ax\r
-\r
- mov esi, ebx\r
- mov edi, esi\r
- add edi, LockLocation\r
- mov rax, NotVacantFlag\r
-\r
-TestLock:\r
- xchg qword ptr [edi], rax\r
- cmp rax, NotVacantFlag\r
- jz TestLock\r
-\r
- mov edi, esi\r
- add edi, NumApsExecutingLoction\r
- inc dword ptr [edi]\r
- mov ebx, dword ptr [edi]\r
-\r
-ProgramStack:\r
- mov edi, esi\r
- add edi, StackSizeLocation\r
- mov rax, qword ptr [edi]\r
- mov edi, esi\r
- add edi, StackStartAddressLocation\r
- add rax, qword ptr [edi]\r
- mov rsp, rax\r
- mov qword ptr [edi], rax\r
-\r
-Releaselock:\r
- mov rax, VacantFlag\r
- mov edi, esi\r
- add edi, LockLocation\r
- xchg qword ptr [edi], rax\r
-\r
-CProcedureInvoke:\r
- push rbp ; push BIST data\r
- xor rbp, rbp ; clear ebp for call stack trace\r
- push rbp\r
- mov rbp, rsp\r
-\r
- mov rax, InitializeFloatingPointUnits\r
- sub rsp, 20h\r
- call rax ; Call assembly function to initialize FPU per UEFI spec\r
- add rsp, 20h\r
-\r
- mov edx, ebx ; edx is NumApsExecuting\r
- mov ecx, esi\r
- add ecx, LockLocation ; rcx is address of exchange info data buffer\r
-\r
- mov edi, esi\r
- add edi, ApProcedureLocation\r
- mov rax, qword ptr [edi]\r
-\r
- sub rsp, 20h\r
- call rax ; invoke C function\r
- add rsp, 20h\r
- jmp $\r
-\r
-RendezvousFunnelProc ENDP\r
-RendezvousFunnelProcEnd::\r
-\r
-;-------------------------------------------------------------------------------------\r
-; AsmGetAddressMap (&AddressMap);\r
-;-------------------------------------------------------------------------------------\r
-AsmGetAddressMap PROC\r
- mov rax, offset RendezvousFunnelProcStart\r
- mov qword ptr [rcx], rax\r
- mov qword ptr [rcx + 8h], LongModeStart - RendezvousFunnelProcStart\r
- mov qword ptr [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
- ret\r
-AsmGetAddressMap ENDP\r
-\r
-;-------------------------------------------------------------------------------------\r
-;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
-;about to become an AP. It switches it'stack with the current AP.\r
-;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);\r
-;-------------------------------------------------------------------------------------\r
-AsmExchangeRole PROC\r
- ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
- ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
-\r
- push rax\r
- push rbx\r
- push rcx\r
- push rdx\r
- push rsi\r
- push rdi\r
- push rbp\r
- push r8\r
- push r9\r
- push r10\r
- push r11\r
- push r12\r
- push r13\r
- push r14\r
- push r15\r
-\r
- mov rax, cr0\r
- push rax\r
-\r
- mov rax, cr4\r
- push rax\r
-\r
- ; rsi contains MyInfo pointer\r
- mov rsi, rcx\r
-\r
- ; rdi contains OthersInfo pointer\r
- mov rdi, rdx\r
-\r
- ;Store EFLAGS, GDTR and IDTR regiter to stack\r
- pushfq\r
- sgdt fword ptr [rsi + 16]\r
- sidt fword ptr [rsi + 26]\r
-\r
- ; Store the its StackPointer\r
- mov qword ptr [rsi + 8], rsp\r
-\r
- ; update its switch state to STORED\r
- mov byte ptr [rsi], CPU_SWITCH_STATE_STORED\r
-\r
-WaitForOtherStored:\r
- ; wait until the other CPU finish storing its state\r
- cmp byte ptr [rdi], CPU_SWITCH_STATE_STORED\r
- jz OtherStored\r
- pause\r
- jmp WaitForOtherStored\r
-\r
-OtherStored:\r
- ; Since another CPU already stored its state, load them\r
- ; load GDTR value\r
- lgdt fword ptr [rdi + 16]\r
-\r
- ; load IDTR value\r
- lidt fword ptr [rdi + 26]\r
-\r
- ; load its future StackPointer\r
- mov rsp, qword ptr [rdi + 8]\r
-\r
- ; update the other CPU's switch state to LOADED\r
- mov byte ptr [rdi], CPU_SWITCH_STATE_LOADED\r
-\r
-WaitForOtherLoaded:\r
- ; wait until the other CPU finish loading new state,\r
- ; otherwise the data in stack may corrupt\r
- cmp byte ptr [rsi], CPU_SWITCH_STATE_LOADED\r
- jz OtherLoaded\r
- pause\r
- jmp WaitForOtherLoaded\r
-\r
-OtherLoaded:\r
- ; since the other CPU already get the data it want, leave this procedure\r
- popfq\r
-\r
- pop rax\r
- mov cr4, rax\r
-\r
- pop rax\r
- mov cr0, rax\r
-\r
- pop r15\r
- pop r14\r
- pop r13\r
- pop r12\r
- pop r11\r
- pop r10\r
- pop r9\r
- pop r8\r
- pop rbp\r
- pop rdi\r
- pop rsi\r
- pop rdx\r
- pop rcx\r
- pop rbx\r
- pop rax\r
-\r
- ret\r
-AsmExchangeRole ENDP\r
-\r
-END\r
+++ /dev/null
-;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
-; This program and the accompanying materials\r
-; are licensed and made available under the terms and conditions of the BSD License\r
-; which accompanies this distribution. The full text of the license may be found at\r
-; http://opensource.org/licenses/bsd-license.php.\r
-;\r
-; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
-;\r
-; Module Name:\r
-;\r
-; MpFuncs.nasm\r
-;\r
-; Abstract:\r
-;\r
-; This is the assembly code for MP support\r
-;\r
-;-------------------------------------------------------------------------------\r
-\r
-%include "MpEqu.inc"\r
-extern ASM_PFX(InitializeFloatingPointUnits)\r
-\r
-DEFAULT REL\r
-\r
-SECTION .text\r
-\r
-;-------------------------------------------------------------------------------------\r
-;RendezvousFunnelProc procedure follows. All APs execute their procedure. This\r
-;procedure serializes all the AP processors through an Init sequence. It must be\r
-;noted that APs arrive here very raw...ie: real mode, no stack.\r
-;ALSO THIS PROCEDURE IS EXECUTED BY APs ONLY ON 16 BIT MODE. HENCE THIS PROC\r
-;IS IN MACHINE CODE.\r
-;-------------------------------------------------------------------------------------\r
-global ASM_PFX(RendezvousFunnelProc)\r
-ASM_PFX(RendezvousFunnelProc):\r
-RendezvousFunnelProcStart:\r
-; At this point CS = 0x(vv00) and ip= 0x0.\r
-; Save BIST information to ebp firstly\r
-\r
-BITS 16\r
- mov ebp, eax ; Save BIST information\r
-\r
- mov ax, cs\r
- mov ds, ax\r
- mov es, ax\r
- mov ss, ax\r
- xor ax, ax\r
- mov fs, ax\r
- mov gs, ax\r
-\r
- mov si, BufferStartLocation\r
- mov ebx, [si]\r
-\r
- mov di, ModeOffsetLocation\r
- mov eax, [di]\r
- mov di, CodeSegmentLocation\r
- mov edx, [di]\r
- mov di, ax\r
- sub di, 02h \r
- mov [di],dx ; Patch long mode CS\r
- sub di, 04h\r
- add eax, ebx\r
- mov [di],eax ; Patch address\r
-\r
- mov si, GdtrLocation\r
-o32 lgdt [cs:si]\r
-\r
- mov si, IdtrLocation\r
-o32 lidt [cs:si]\r
-\r
-\r
- mov di, DataSegmentLocation\r
- mov edi, [di] ; Save long mode DS in edi\r
-\r
- mov si, Cr3Location ; Save CR3 in ecx\r
- mov ecx, [si]\r
-\r
- xor ax, ax\r
- mov ds, ax ; Clear data segment\r
-\r
- mov eax, cr0 ; Get control register 0\r
- or eax, 000000003h ; Set PE bit (bit #0) & MP\r
- mov cr0, eax\r
-\r
- mov eax, cr4\r
- bts eax, 5\r
- mov cr4, eax\r
-\r
- mov cr3, ecx ; Load CR3\r
-\r
- mov ecx, 0c0000080h ; EFER MSR number\r
- rdmsr ; Read EFER\r
- bts eax, 8 ; Set LME=1\r
- wrmsr ; Write EFER\r
-\r
- mov eax, cr0 ; Read CR0\r
- bts eax, 31 ; Set PG=1\r
- mov cr0, eax ; Write CR0\r
-\r
- jmp 0:strict dword 0 ; far jump to long mode\r
-BITS 64\r
-LongModeStart:\r
- mov eax, edi\r
- mov ds, ax\r
- mov es, ax\r
- mov ss, ax\r
-\r
- mov esi, ebx\r
- mov edi, esi\r
- add edi, LockLocation\r
- mov rax, NotVacantFlag\r
-\r
-TestLock:\r
- xchg qword [edi], rax\r
- cmp rax, NotVacantFlag\r
- jz TestLock\r
-\r
- mov edi, esi\r
- add edi, NumApsExecutingLoction\r
- inc dword [edi]\r
- mov ebx, [edi]\r
-\r
-ProgramStack:\r
- mov edi, esi\r
- add edi, StackSizeLocation\r
- mov rax, qword [edi]\r
- mov edi, esi\r
- add edi, StackStartAddressLocation\r
- add rax, qword [edi]\r
- mov rsp, rax\r
- mov qword [edi], rax\r
-\r
-Releaselock:\r
- mov rax, VacantFlag\r
- mov edi, esi\r
- add edi, LockLocation\r
- xchg qword [edi], rax\r
-\r
-CProcedureInvoke:\r
- push rbp ; push BIST data at top of AP stack\r
- xor rbp, rbp ; clear ebp for call stack trace\r
- push rbp\r
- mov rbp, rsp\r
-\r
- mov rax, ASM_PFX(InitializeFloatingPointUnits)\r
- sub rsp, 20h\r
- call rax ; Call assembly function to initialize FPU per UEFI spec\r
- add rsp, 20h\r
-\r
- mov edx, ebx ; edx is NumApsExecuting\r
- mov ecx, esi\r
- add ecx, LockLocation ; rcx is address of exchange info data buffer\r
-\r
- mov edi, esi\r
- add edi, ApProcedureLocation\r
- mov rax, qword [edi]\r
-\r
- sub rsp, 20h\r
- call rax ; invoke C function\r
- add rsp, 20h\r
- jmp $\r
-\r
-RendezvousFunnelProcEnd:\r
-\r
-;-------------------------------------------------------------------------------------\r
-; AsmGetAddressMap (&AddressMap);\r
-;-------------------------------------------------------------------------------------\r
-global ASM_PFX(AsmGetAddressMap)\r
-ASM_PFX(AsmGetAddressMap):\r
- mov rax, ASM_PFX(RendezvousFunnelProc)\r
- mov qword [rcx], rax\r
- mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStart\r
- mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunnelProcStart\r
- ret\r
-\r
-;-------------------------------------------------------------------------------------\r
-;AsmExchangeRole procedure follows. This procedure executed by current BSP, that is\r
-;about to become an AP. It switches it'stack with the current AP.\r
-;AsmExchangeRole (IN CPU_EXCHANGE_INFO *MyInfo, IN CPU_EXCHANGE_INFO *OthersInfo);\r
-;-------------------------------------------------------------------------------------\r
-global ASM_PFX(AsmExchangeRole)\r
-ASM_PFX(AsmExchangeRole):\r
- ; DO NOT call other functions in this function, since 2 CPU may use 1 stack\r
- ; at the same time. If 1 CPU try to call a function, stack will be corrupted.\r
-\r
- push rax\r
- push rbx\r
- push rcx\r
- push rdx\r
- push rsi\r
- push rdi\r
- push rbp\r
- push r8\r
- push r9\r
- push r10\r
- push r11\r
- push r12\r
- push r13\r
- push r14\r
- push r15\r
-\r
- mov rax, cr0\r
- push rax\r
-\r
- mov rax, cr4\r
- push rax\r
-\r
- ; rsi contains MyInfo pointer\r
- mov rsi, rcx\r
-\r
- ; rdi contains OthersInfo pointer\r
- mov rdi, rdx\r
-\r
- ;Store EFLAGS, GDTR and IDTR regiter to stack\r
- pushfq\r
- sgdt [rsi + 16]\r
- sidt [rsi + 26]\r
-\r
- ; Store the its StackPointer\r
- mov [rsi + 8], rsp\r
-\r
- ; update its switch state to STORED\r
- mov byte [rsi], CPU_SWITCH_STATE_STORED\r
-\r
-WaitForOtherStored:\r
- ; wait until the other CPU finish storing its state\r
- cmp byte [rdi], CPU_SWITCH_STATE_STORED\r
- jz OtherStored\r
- pause\r
- jmp WaitForOtherStored\r
-\r
-OtherStored:\r
- ; Since another CPU already stored its state, load them\r
- ; load GDTR value\r
- lgdt [rdi + 16]\r
-\r
- ; load IDTR value\r
- lidt [rdi + 26]\r
-\r
- ; load its future StackPointer\r
- mov rsp, [rdi + 8]\r
-\r
- ; update the other CPU's switch state to LOADED\r
- mov byte [rdi], CPU_SWITCH_STATE_LOADED\r
-\r
-WaitForOtherLoaded:\r
- ; wait until the other CPU finish loading new state,\r
- ; otherwise the data in stack may corrupt\r
- cmp byte [rsi], CPU_SWITCH_STATE_LOADED\r
- jz OtherLoaded\r
- pause\r
- jmp WaitForOtherLoaded\r
-\r
-OtherLoaded:\r
- ; since the other CPU already get the data it want, leave this procedure\r
- popfq\r
-\r
- pop rax\r
- mov cr4, rax\r
-\r
- pop rax\r
- mov cr0, rax\r
-\r
- pop r15\r
- pop r14\r
- pop r13\r
- pop r12\r
- pop r11\r
- pop r10\r
- pop r9\r
- pop r8\r
- pop rbp\r
- pop rdi\r
- pop rsi\r
- pop rdx\r
- pop rcx\r
- pop rbx\r
- pop rax\r
-\r
- ret\r
projects / mirror_edk2.git / commitdiff