UefiCpuPkg/SmmCpuFeaturesLib: replace hard-coded machine code

Replace hard-coded machine code with equivalent assembly source code.
Changes tested by checking for machine code equivalence by disassembling
the original and changed code.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Chris Ruffin <chris.ruffin@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
index b1c84a494f7b4c64090899c3772d2101da2544a2..00c0f0672c0b1dc62d71ae00ca8a1cf970660ffc 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -51,6 +51,11 @@ global ASM_PFX(gStmSmbase)
 global ASM_PFX(gStmXdSupported)\r
 extern ASM_PFX(gStmSmiHandlerIdtr)\r
 \r
+ASM_PFX(gStmSmiCr3)      EQU StmSmiCr3Patch - 4\r
+ASM_PFX(gStmSmiStack)    EQU StmSmiStackPatch - 4\r
+ASM_PFX(gStmSmbase)      EQU StmSmbasePatch - 4\r
+ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1\r
+\r
     SECTION .text\r
 \r
 BITS 16\r
@@ -66,8 +71,8 @@ _StmSmiEntryPoint:
 o32 lgdt    [cs:bx]                       ; lgdt fword ptr cs:[bx]\r
     mov     ax, PROTECT_MODE_CS\r
     mov     [cs:bx-0x2],ax\r
-    DB      0x66, 0xbf                   ; mov edi, SMBASE\r
-ASM_PFX(gStmSmbase): DD 0\r
+o32 mov     edi, strict dword 0\r
+StmSmbasePatch:\r
     lea     eax, [edi + (@32bit - _StmSmiEntryPoint) + 0x8000]\r
     mov     [cs:bx-0x6],eax\r
     mov     ebx, cr0\r
@@ -87,15 +92,15 @@ o16 mov     es, ax
 o16 mov     fs, ax\r
 o16 mov     gs, ax\r
 o16 mov     ss, ax\r
-    DB      0xbc                   ; mov esp, imm32\r
-ASM_PFX(gStmSmiStack): DD 0\r
+    mov     esp, strict dword 0\r
+StmSmiStackPatch:\r
     mov     eax, ASM_PFX(gStmSmiHandlerIdtr)\r
     lidt    [eax]\r
     jmp     ProtFlatMode\r
 \r
 ProtFlatMode:\r
-    DB      0xb8                        ; mov eax, imm32\r
-ASM_PFX(gStmSmiCr3): DD 0\r
+    mov eax, strict dword 0\r
+StmSmiCr3Patch:\r
     mov     cr3, eax\r
 ;\r
 ; Need to test for CR4 specific bit support\r
@@ -134,8 +139,8 @@ ASM_PFX(gStmSmiCr3): DD 0
 .6:\r
 \r
 ; enable NXE if supported\r
-    DB      0b0h                        ; mov al, imm8\r
-ASM_PFX(gStmXdSupported):     DB      1\r
+    mov     al, strict byte 1\r
+StmXdSupportedPatch:\r
     cmp     al, 0\r
     jz      @SkipXd\r
 ;\r
@@ -268,4 +273,3 @@ _StmSmiHandler:
 \r
 ASM_PFX(gcStmSmiHandlerSize)   : DW        $ - _StmSmiEntryPoint\r
 ASM_PFX(gcStmSmiHandlerOffset) : DW        _StmSmiHandler - _StmSmiEntryPoint\r
-\r

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
index 0ce8501ba94e78dbf81efeae829ada6340a1ed38..93dc3005b7b2fdaa1d5f9a228918d5ae47097bbb 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/Ia32/SmiException.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -87,7 +87,7 @@ ASM_PFX(OnException):
 \r
     mov  ebx, eax\r
     mov  eax, 4\r
-    DB  0x0f, 0x01, 0x0c1 ; VMCALL\r
+    vmcall\r
     jmp $\r
 \r
 global ASM_PFX(OnStmSetup)\r
@@ -173,4 +173,3 @@ ASM_PFX(OnStmTeardown):
 \r
 .72:\r
   rsm\r
-\r

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
index c801591fc7642044e0459ee27b51b9b2e80bc10c..bcac643e962cf47604d70a428d80f8e2fe7faf87 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiEntry.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -61,6 +61,11 @@ global ASM_PFX(gcStmSmiHandlerTemplate)
 global ASM_PFX(gcStmSmiHandlerSize)\r
 global ASM_PFX(gcStmSmiHandlerOffset)\r
 \r
+ASM_PFX(gStmSmbase)      EQU StmSmbasePatch - 4\r
+ASM_PFX(gStmSmiStack)    EQU StmSmiStackPatch - 4\r
+ASM_PFX(gStmSmiCr3)      EQU StmSmiCr3Patch - 4\r
+ASM_PFX(gStmXdSupported) EQU StmXdSupportedPatch - 1\r
+\r
     DEFAULT REL\r
     SECTION .text\r
 \r
@@ -76,8 +81,8 @@ _StmSmiEntryPoint:
 o32 lgdt    [cs:bx]                       ; lgdt fword ptr cs:[bx]\r
     mov     ax, PROTECT_MODE_CS\r
     mov     [cs:bx-0x2],ax\r
-    DB      0x66, 0xbf                   ; mov edi, SMBASE\r
-ASM_PFX(gStmSmbase): DD 0\r
+o32 mov     edi, strict dword 0\r
+StmSmbasePatch:\r
     lea     eax, [edi + (@ProtectedMode - _StmSmiEntryPoint) + 0x8000]\r
     mov     [cs:bx-0x6],eax\r
     mov     ebx, cr0\r
@@ -97,14 +102,14 @@ o16 mov     es, ax
 o16 mov     fs, ax\r
 o16 mov     gs, ax\r
 o16 mov     ss, ax\r
-    DB      0xbc                   ; mov esp, imm32\r
-ASM_PFX(gStmSmiStack): DD 0\r
+    mov     esp, strict dword 0\r
+StmSmiStackPatch:\r
     jmp     ProtFlatMode\r
 \r
 BITS 64\r
 ProtFlatMode:\r
-    DB      0xb8                        ; mov eax, offset gStmSmiCr3\r
-ASM_PFX(gStmSmiCr3): DD 0\r
+    mov     eax, strict dword 0\r
+StmSmiCr3Patch:\r
     mov     cr3, rax\r
     mov     eax, 0x668                   ; as cr4.PGE is not set here, refresh cr3\r
     mov     cr4, rax                    ; in PreModifyMtrrs() to flush TLB.\r
@@ -119,8 +124,8 @@ ASM_PFX(gStmSmiCr3): DD 0
     ltr     ax\r
 \r
 ; enable NXE if supported\r
-    DB      0xb0                        ; mov al, imm8\r
-ASM_PFX(gStmXdSupported):     DB      1\r
+    mov al, strict byte 1\r
+StmXdSupportedPatch:\r
     cmp     al, 0\r
     jz      @SkipXd\r
 ;\r
@@ -178,8 +183,7 @@ CommonHandler:
     ; Save FP registers\r
     ;\r
     sub     rsp, 0x200\r
-    DB      0x48                         ; FXSAVE64\r
-    fxsave  [rsp]\r
+    fxsave64 [rsp]\r
 \r
     add     rsp, -0x20\r
 \r
@@ -200,8 +204,7 @@ CommonHandler:
     ;\r
     ; Restore FP registers\r
     ;\r
-    DB      0x48                         ; FXRSTOR64\r
-    fxrstor [rsp]\r
+    fxrstor64 [rsp]\r
 \r
     add     rsp, 0x200\r
 \r

diff --git a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
index fe1bf3f16574dde8e02c7aea86c5e29614204e6d..ce9d7c2bb64e7ecc48755f57bd7d335335712944 100644 (file)
--- a/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
+++ b/UefiCpuPkg/Library/SmmCpuFeaturesLib/X64/SmiException.nasm
@@ -1,5 +1,5 @@
 ;------------------------------------------------------------------------------ ;\r
-; Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+; Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r
 ; This program and the accompanying materials\r
 ; are licensed and made available under the terms and conditions of the BSD License\r
 ; which accompanies this distribution.  The full text of the license may be found at\r
@@ -86,7 +86,7 @@ ASM_PFX(OnException):
     add  rsp, 0x28\r
     mov  ebx, eax\r
     mov  eax, 4\r
-    DB  0x0f, 0x01, 0x0c1 ; VMCALL\r
+    vmcall\r
     jmp $\r
 \r
 global ASM_PFX(OnStmSetup)\r
@@ -176,4 +176,3 @@ ASM_PFX(OnStmTeardown):
 \r
 .12:\r
   rsm\r
-\r