**/\r
\r
#include <IndustryStandard/Pci.h> // EFI_PCI_COMMAND_IO_SPACE\r
-#include <IndustryStandard/Q35MchIch9.h> // INTEL_Q35_MCH_DEVICE_ID\r
#include <Library/BaseLib.h> // DisableInterrupts()\r
#include <Library/BaseMemoryLib.h> // ZeroMem()\r
#include <Library/DebugLib.h> // ASSERT()\r
#include <Library/MemoryAllocationLib.h> // ReallocatePool()\r
-#include <Library/PcdLib.h> // PcdGet16()\r
#include <Library/PciHostBridgeLib.h> // PCI_ROOT_BRIDGE_APERTURE\r
#include <Library/PciHostBridgeUtilityLib.h> // PciHostBridgeUtilityInitRoot...\r
#include <Library/PciLib.h> // PciRead32()\r
ASSERT (RootBridges != NULL);\r
PciHostBridgeUtilityInitRootBridge (\r
Attributes, Attributes, 0,\r
- FALSE, PcdGet16 (PcdOvmfHostBridgePciDevId) != INTEL_Q35_MCH_DEVICE_ID,\r
+ FALSE, TRUE /* NoExtendedConfigSpace */,\r
(UINT8) PrimaryBus, (UINT8) SubBus,\r
&Io, &Mem, &MemAbove4G, &mNonExistAperture, &mNonExistAperture,\r
&RootBridges[*NumberOfRootBridges]\r