// IPF context buffer used by SetJump() and LongJump()\r
//\r
typedef struct {\r
- UINT64 InitialUNAT;\r
- UINT64 AfterSpillUNAT;\r
- UINT64 PFS;\r
- UINT64 BSP;\r
- UINT64 RNAT;\r
- UINT64 Predicates;\r
- UINT64 LoopCount;\r
+ UINT64 F2[2];\r
+ UINT64 F3[2];\r
+ UINT64 F4[2];\r
+ UINT64 F5[2];\r
+ UINT64 F16[2];\r
+ UINT64 F17[2];\r
+ UINT64 F18[2];\r
+ UINT64 F19[2];\r
+ UINT64 F20[2];\r
+ UINT64 F21[2];\r
+ UINT64 F22[2];\r
+ UINT64 F23[2];\r
+ UINT64 F24[2];\r
+ UINT64 F25[2];\r
+ UINT64 F26[2];\r
+ UINT64 F27[2];\r
+ UINT64 F28[2];\r
+ UINT64 F29[2];\r
+ UINT64 F30[2];\r
+ UINT64 F31[2];\r
UINT64 R4;\r
UINT64 R5;\r
UINT64 R6;\r
UINT64 R7;\r
UINT64 SP;\r
- UINT64 F2Low;\r
- UINT64 F2High;\r
- UINT64 F3Low;\r
- UINT64 F3High;\r
- UINT64 F4Low;\r
- UINT64 F4High;\r
- UINT64 F5Low;\r
- UINT64 F5High;\r
- UINT64 F16Low;\r
- UINT64 F16High;\r
- UINT64 F17Low;\r
- UINT64 F17High;\r
- UINT64 F18Low;\r
- UINT64 F18High;\r
- UINT64 F19Low;\r
- UINT64 F19High;\r
- UINT64 F20Low;\r
- UINT64 F20High;\r
- UINT64 F21Low;\r
- UINT64 F21High;\r
- UINT64 F22Low;\r
- UINT64 F22High;\r
- UINT64 F23Low;\r
- UINT64 F23High;\r
- UINT64 F24Low;\r
- UINT64 F24High;\r
- UINT64 F25Low;\r
- UINT64 F25High;\r
- UINT64 F26Low;\r
- UINT64 F26High;\r
- UINT64 F27Low;\r
- UINT64 F27High;\r
- UINT64 F28Low;\r
- UINT64 F28High;\r
- UINT64 F29Low;\r
- UINT64 F29High;\r
- UINT64 F30Low;\r
- UINT64 F30High;\r
- UINT64 F31Low;\r
- UINT64 F31High;\r
- UINT64 FPSR;\r
UINT64 BR0;\r
UINT64 BR1;\r
UINT64 BR2;\r
UINT64 BR3;\r
UINT64 BR4;\r
UINT64 BR5;\r
+ UINT64 InitialUNAT;\r
+ UINT64 AfterSpillUNAT;\r
+ UINT64 PFS;\r
+ UINT64 BSP;\r
+ UINT64 Predicates;\r
+ UINT64 LoopCount;\r
+ UINT64 FPSR;\r
} BASE_LIBRARY_JUMP_BUFFER;\r
\r
#elif defined (MDE_CPU_X64)\r
\r
//\r
// Byte packed structure for an IDTR, GDTR, LDTR descriptor\r
+/// @bug How to make this structure byte-packed in a compiler independent way?\r
//\r
typedef struct {\r
UINT16 Limit;\r
<LibraryClass Usage="ALWAYS_CONSUMED">BaseMemoryLib</LibraryClass>\r
<LibraryClass Usage="ALWAYS_CONSUMED">DebugLib</LibraryClass>\r
<LibraryClass Usage="ALWAYS_CONSUMED">TimerLib</LibraryClass>\r
+ <LibraryClass Usage="ALWAYS_CONSUMED">PcdLib</LibraryClass>\r
</LibraryClassDefinitions>\r
<SourceFiles>\r
<Filename>String.c</Filename>\r
<Filename>RRotU32.c</Filename>\r
<Filename>RRotU64.c</Filename>\r
<Filename>RShiftU64.c</Filename>\r
+ <Filename>SetJump.c</Filename>\r
+ <Filename>LongJump.c</Filename>\r
<Filename>SwapBytes16.c</Filename>\r
<Filename>SwapBytes32.c</Filename>\r
<Filename>SwapBytes64.c</Filename>\r
+ <Filename>SwitchStack.c</Filename>\r
<Arch ArchType="IA32">\r
<Filename>x86LowLevel.c</Filename>\r
<Filename>x86Thunk.c</Filename>\r
<Filename>Unaligned.c</Filename>\r
- <Filename>LongJump.c</Filename>\r
- <Filename>SwitchStack.c</Filename>\r
<Filename>Ia32/Non-existing.c</Filename>\r
<Filename>Ia32/InternalSwitchStack.c</Filename>\r
<Filename>Ia32/LShiftU64.asm</Filename>\r
<Filename>Ia32/Thunk16.asm</Filename>\r
</Arch>\r
<Arch ArchType="X64">\r
- <Filename>x86LowLevel.c</Filename>\r
- <Filename>x86Thunk.c</Filename>\r
+ <Filename>X86LowLevel.c</Filename>\r
+ <Filename>X86Thunk.c</Filename>\r
<Filename>Unaligned.c</Filename>\r
<Filename>Math64.c</Filename>\r
- <Filename>LongJump.c</Filename>\r
- <Filename>SwitchStack.c</Filename>\r
- <Filename>x64/Non-existing.c</Filename>\r
- <Filename>x64/SwitchStack.asm</Filename>\r
- <Filename>x64/SetJump.asm</Filename>\r
- <Filename>x64/LongJump.asm</Filename>\r
- <Filename>x64/CpuId.asm</Filename>\r
- <Filename>x64/ReadEflags.asm</Filename>\r
- <Filename>x64/ReadMsr32.asm</Filename>\r
- <Filename>x64/ReadMsr64.asm</Filename>\r
- <Filename>x64/WriteMsr32.asm</Filename>\r
- <Filename>x64/WriteMsr64.asm</Filename>\r
- <Filename>x64/ReadCr0.asm</Filename>\r
- <Filename>x64/ReadCr2.asm</Filename>\r
- <Filename>x64/ReadCr3.asm</Filename>\r
- <Filename>x64/ReadCr4.asm</Filename>\r
- <Filename>x64/WriteCr0.asm</Filename>\r
- <Filename>x64/WriteCr2.asm</Filename>\r
- <Filename>x64/WriteCr3.asm</Filename>\r
- <Filename>x64/WriteCr4.asm</Filename>\r
- <Filename>x64/ReadDr0.asm</Filename>\r
- <Filename>x64/ReadDr1.asm</Filename>\r
- <Filename>x64/ReadDr2.asm</Filename>\r
- <Filename>x64/ReadDr3.asm</Filename>\r
- <Filename>x64/ReadDr4.asm</Filename>\r
- <Filename>x64/ReadDr5.asm</Filename>\r
- <Filename>x64/ReadDr6.asm</Filename>\r
- <Filename>x64/ReadDr7.asm</Filename>\r
- <Filename>x64/WriteDr0.asm</Filename>\r
- <Filename>x64/WriteDr1.asm</Filename>\r
- <Filename>x64/WriteDr2.asm</Filename>\r
- <Filename>x64/WriteDr3.asm</Filename>\r
- <Filename>x64/WriteDr4.asm</Filename>\r
- <Filename>x64/WriteDr5.asm</Filename>\r
- <Filename>x64/WriteDr6.asm</Filename>\r
- <Filename>x64/WriteDr7.asm</Filename>\r
- <Filename>x64/ReadCs.asm</Filename>\r
- <Filename>x64/ReadDs.asm</Filename>\r
- <Filename>x64/ReadEs.asm</Filename>\r
- <Filename>x64/ReadFs.asm</Filename>\r
- <Filename>x64/ReadGs.asm</Filename>\r
- <Filename>x64/ReadSs.asm</Filename>\r
- <Filename>x64/ReadTr.asm</Filename>\r
- <Filename>x64/ReadGdtr.asm</Filename>\r
- <Filename>x64/WriteGdtr.asm</Filename>\r
- <Filename>x64/ReadIdtr.asm</Filename>\r
- <Filename>x64/WriteIdtr.asm</Filename>\r
- <Filename>x64/ReadLdtr.asm</Filename>\r
- <Filename>x64/WriteLdtr.asm</Filename>\r
- <Filename>x64/FxSave.asm</Filename>\r
- <Filename>x64/FxRestore.asm</Filename>\r
- <Filename>x64/ReadMm0.asm</Filename>\r
- <Filename>x64/ReadMm1.asm</Filename>\r
- <Filename>x64/ReadMm2.asm</Filename>\r
- <Filename>x64/ReadMm3.asm</Filename>\r
- <Filename>x64/ReadMm4.asm</Filename>\r
- <Filename>x64/ReadMm5.asm</Filename>\r
- <Filename>x64/ReadMm6.asm</Filename>\r
- <Filename>x64/ReadMm7.asm</Filename>\r
- <Filename>x64/WriteMm0.asm</Filename>\r
- <Filename>x64/WriteMm1.asm</Filename>\r
- <Filename>x64/WriteMm2.asm</Filename>\r
- <Filename>x64/WriteMm3.asm</Filename>\r
- <Filename>x64/WriteMm4.asm</Filename>\r
- <Filename>x64/WriteMm5.asm</Filename>\r
- <Filename>x64/WriteMm6.asm</Filename>\r
- <Filename>x64/WriteMm7.asm</Filename>\r
- <Filename>x64/ReadTsc.asm</Filename>\r
- <Filename>x64/ReadPmc.asm</Filename>\r
- <Filename>x64/Monitor.asm</Filename>\r
- <Filename>x64/Mwait.asm</Filename>\r
- <Filename>x64/DisablePaging64.asm</Filename>\r
- <Filename>x64/Wbinvd.asm</Filename>\r
- <Filename>x64/Invd.asm</Filename>\r
- <Filename>x64/FlushCacheLine.asm</Filename>\r
- <Filename>x64/InterlockedIncrement.asm</Filename>\r
- <Filename>x64/InterlockedDecrement.asm</Filename>\r
- <Filename>x64/InterlockedCompareExchange32.asm</Filename>\r
- <Filename>x64/InterlockedCompareExchange64.asm</Filename>\r
- <Filename>x64/EnableInterrupts.asm</Filename>\r
- <Filename>x64/DisableInterrupts.asm</Filename>\r
- <Filename>x64/EnableDisableInterrupts.asm</Filename>\r
- <Filename>x64/CpuSleep.asm</Filename>\r
- <Filename>x64/CpuPause.asm</Filename>\r
- <Filename>x64/CpuBreakpoint.asm</Filename>\r
- <Filename>x64/CpuFlushTlb.asm</Filename>\r
- <Filename>x64/Thunk16.asm</Filename>\r
+ <Filename>X64/Non-existing.c</Filename>\r
+ <Filename>X64/SwitchStack.asm</Filename>\r
+ <Filename>X64/SetJump.asm</Filename>\r
+ <Filename>X64/LongJump.asm</Filename>\r
+ <Filename>X64/CpuId.asm</Filename>\r
+ <Filename>X64/CpuIdEx.asm</Filename>\r
+ <Filename>X64/ReadEflags.asm</Filename>\r
+ <Filename>X64/ReadMsr32.asm</Filename>\r
+ <Filename>X64/ReadMsr64.asm</Filename>\r
+ <Filename>X64/WriteMsr32.asm</Filename>\r
+ <Filename>X64/WriteMsr64.asm</Filename>\r
+ <Filename>X64/ReadCr0.asm</Filename>\r
+ <Filename>X64/ReadCr2.asm</Filename>\r
+ <Filename>X64/ReadCr3.asm</Filename>\r
+ <Filename>X64/ReadCr4.asm</Filename>\r
+ <Filename>X64/WriteCr0.asm</Filename>\r
+ <Filename>X64/WriteCr2.asm</Filename>\r
+ <Filename>X64/WriteCr3.asm</Filename>\r
+ <Filename>X64/WriteCr4.asm</Filename>\r
+ <Filename>X64/ReadDr0.asm</Filename>\r
+ <Filename>X64/ReadDr1.asm</Filename>\r
+ <Filename>X64/ReadDr2.asm</Filename>\r
+ <Filename>X64/ReadDr3.asm</Filename>\r
+ <Filename>X64/ReadDr4.asm</Filename>\r
+ <Filename>X64/ReadDr5.asm</Filename>\r
+ <Filename>X64/ReadDr6.asm</Filename>\r
+ <Filename>X64/ReadDr7.asm</Filename>\r
+ <Filename>X64/WriteDr0.asm</Filename>\r
+ <Filename>X64/WriteDr1.asm</Filename>\r
+ <Filename>X64/WriteDr2.asm</Filename>\r
+ <Filename>X64/WriteDr3.asm</Filename>\r
+ <Filename>X64/WriteDr4.asm</Filename>\r
+ <Filename>X64/WriteDr5.asm</Filename>\r
+ <Filename>X64/WriteDr6.asm</Filename>\r
+ <Filename>X64/WriteDr7.asm</Filename>\r
+ <Filename>X64/ReadCs.asm</Filename>\r
+ <Filename>X64/ReadDs.asm</Filename>\r
+ <Filename>X64/ReadEs.asm</Filename>\r
+ <Filename>X64/ReadFs.asm</Filename>\r
+ <Filename>X64/ReadGs.asm</Filename>\r
+ <Filename>X64/ReadSs.asm</Filename>\r
+ <Filename>X64/ReadTr.asm</Filename>\r
+ <Filename>X64/ReadGdtr.asm</Filename>\r
+ <Filename>X64/WriteGdtr.asm</Filename>\r
+ <Filename>X64/ReadIdtr.asm</Filename>\r
+ <Filename>X64/WriteIdtr.asm</Filename>\r
+ <Filename>X64/ReadLdtr.asm</Filename>\r
+ <Filename>X64/WriteLdtr.asm</Filename>\r
+ <Filename>X64/FxSave.asm</Filename>\r
+ <Filename>X64/FxRestore.asm</Filename>\r
+ <Filename>X64/ReadMm0.asm</Filename>\r
+ <Filename>X64/ReadMm1.asm</Filename>\r
+ <Filename>X64/ReadMm2.asm</Filename>\r
+ <Filename>X64/ReadMm3.asm</Filename>\r
+ <Filename>X64/ReadMm4.asm</Filename>\r
+ <Filename>X64/ReadMm5.asm</Filename>\r
+ <Filename>X64/ReadMm6.asm</Filename>\r
+ <Filename>X64/ReadMm7.asm</Filename>\r
+ <Filename>X64/WriteMm0.asm</Filename>\r
+ <Filename>X64/WriteMm1.asm</Filename>\r
+ <Filename>X64/WriteMm2.asm</Filename>\r
+ <Filename>X64/WriteMm3.asm</Filename>\r
+ <Filename>X64/WriteMm4.asm</Filename>\r
+ <Filename>X64/WriteMm5.asm</Filename>\r
+ <Filename>X64/WriteMm6.asm</Filename>\r
+ <Filename>X64/WriteMm7.asm</Filename>\r
+ <Filename>X64/ReadTsc.asm</Filename>\r
+ <Filename>X64/ReadPmc.asm</Filename>\r
+ <Filename>X64/Monitor.asm</Filename>\r
+ <Filename>X64/Mwait.asm</Filename>\r
+ <Filename>X64/DisablePaging64.asm</Filename>\r
+ <Filename>X64/Wbinvd.asm</Filename>\r
+ <Filename>X64/Invd.asm</Filename>\r
+ <Filename>X64/FlushCacheLine.asm</Filename>\r
+ <Filename>X64/InterlockedIncrement.asm</Filename>\r
+ <Filename>X64/InterlockedDecrement.asm</Filename>\r
+ <Filename>X64/InterlockedCompareExchange32.asm</Filename>\r
+ <Filename>X64/InterlockedCompareExchange64.asm</Filename>\r
+ <Filename>X64/EnableInterrupts.asm</Filename>\r
+ <Filename>X64/DisableInterrupts.asm</Filename>\r
+ <Filename>X64/EnableDisableInterrupts.asm</Filename>\r
+ <Filename>X64/CpuSleep.asm</Filename>\r
+ <Filename>X64/CpuPause.asm</Filename>\r
+ <Filename>X64/CpuBreakpoint.asm</Filename>\r
+ <Filename>X64/CpuFlushTlb.asm</Filename>\r
+ <Filename>X64/Thunk16.asm</Filename>\r
</Arch>\r
<Arch ArchType="IPF">\r
<Filename>Math64.c</Filename>\r
- <Filename>LongJump.c</Filename>\r
- <Filename>SwitchStack.c</Filename>\r
<Filename>Ipf/PalCallStatic.s</Filename>\r
<Filename>Ipf/setjmp.s</Filename>\r
+ <Filename>Ipf/longjmp.s</Filename>\r
<Filename>Ipf/SwitchStack.s</Filename>\r
<Filename>Ipf/Unaligned.c</Filename>\r
<Filename>Ipf/CpuBreakpoint.c</Filename>\r
/** @file\r
- Switch Stack functions. \r
+ Switch Stack functions.\r
\r
Copyright (c) 2006, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
\r
**/\r
\r
-\r
+VOID\r
+EFIAPI\r
+InternalAssertJumpBuffer (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
+ );\r
\r
UINTN\r
EFIAPI\r
SetJump (\r
- IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
)\r
{\r
- ASSERT (JumpBuffer != NULL);\r
- ASSERT (FALSE);\r
+ InternalAssertJumpBuffer (JumpBuffer);\r
return 0;\r
}\r
\r
VOID\r
EFIAPI\r
-LongJump (\r
- IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
- IN UINTN Value\r
+InternalLongJump (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
+ IN UINTN Value\r
)\r
{\r
- ASSERT (JumpBuffer != NULL);\r
- ASSERT (Value != 0);\r
ASSERT (FALSE);\r
}\r
**/\r
VOID\r
EFIAPI\r
-SwitchStack (\r
+InternalSwitchStack (\r
IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
IN VOID *Context1, OPTIONAL\r
IN VOID *Context2, OPTIONAL\r
;------------------------------------------------------------------------------\r
\r
.386\r
- .model flat\r
+ .model flat,C\r
.code\r
\r
-__LongJump PROC\r
+IntenralLongJump PROC\r
pop eax\r
pop edx\r
pop eax\r
mov ebp, [edx + 12]\r
mov esp, [edx + 16]\r
jmp dword ptr [edx + 20]\r
-__LongJump ENDP\r
+IntenralLongJump ENDP\r
\r
END\r
;------------------------------------------------------------------------------\r
\r
.386\r
- .model flat\r
+ .model flat,C\r
.code\r
\r
-_SetJump PROC\r
+InternalAssertJumpBuffer PROTO C\r
+\r
+SetJump PROC\r
+ push [esp + 4]\r
+ call InternalAssertJumpBuffer\r
+ pop ecx\r
pop ecx\r
mov edx, [esp]\r
mov [edx], ebx\r
mov [edx + 20], ecx\r
xor eax, eax\r
jmp ecx\r
-_SetJump ENDP\r
+SetJump ENDP\r
\r
END\r
#pragma intrinsic (__break)\r
#pragma intrinsic (__mfa)\r
\r
+typedef struct {\r
+ UINT64 Status;\r
+ UINT64 r9;\r
+ UINT64 r10;\r
+ UINT64 r11;\r
+} PAL_PROC_RETURN;\r
+\r
+PAL_PROC_RETURN\r
+PalCallStatic (\r
+ IN CONST VOID *PalEntryPoint,\r
+ IN UINT64 Arg1,\r
+ IN UINT64 Arg2,\r
+ IN UINT64 Arg3,\r
+ IN UINT64 Arg4\r
+ );\r
+\r
/**\r
Generates a breakpoint on the CPU.\r
\r
EnableInterrupts ();\r
DisableInterrupts ();\r
}\r
+\r
+/**\r
+ Places the CPU in a sleep state until an interrupt is received.\r
+\r
+ Places the CPU in a sleep state until an interrupt is received. If interrupts\r
+ are disabled prior to calling this function, then the CPU will be placed in a\r
+ sleep state indefinitely.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuSleep (\r
+ VOID\r
+ )\r
+{\r
+ PalCallStatic (NULL, 29, 0, 0, 0);\r
+}\r
.proc CpuFlushTlb\r
.type CpuFlushTlb, @function\r
CpuFlushTlb::\r
- alloc loc0 = ar.pfs, 0, 2, 5, 0\r
+ alloc loc0 = ar.pfs, 0, 3, 5, 0\r
mov out0 = 0\r
mov out1 = 6\r
mov out2 = 0\r
mov out3 = 0\r
- mov out4 = 0\r
mov loc1 = b0\r
- br.call.sptk b0 = PalCallStatic\r
- rsm 1 << 14 // Disable interrupts\r
+ mov out4 = 0\r
+ brl.call.sptk b0 = PalCallStatic\r
+ mov loc2 = psr // save PSR\r
mov ar.pfs = loc0\r
extr.u r14 = r10, 32, 32 // r14 <- count1\r
+ rsm 1 << 14 // Disable interrupts\r
extr.u r15 = r11, 32, 32 // r15 <- stride1\r
extr.u r10 = r10, 0, 32 // r10 <- count2\r
- mov loc0 = psr\r
+ add r10 = -1, r10\r
extr.u r11 = r11, 0, 32 // r11 <- stride2\r
br.cond.sptk LoopPredicate\r
LoopOuter:\r
br.ctop.sptk Loop\r
add r9 = r15, r9 // r9 += stride1\r
LoopPredicate:\r
- cmp.ne p6, p7 = r0, r14 // count1 == 0?\r
+ cmp.ne p6 = r0, r14 // count1 == 0?\r
add r14 = -1, r14\r
(p6) br.cond.sptk LoopOuter\r
- mov psr.l = loc0\r
+ mov psr.l = loc2\r
mov b0 = loc1\r
br.ret.sptk.many b0\r
.endp\r
.type PalCallStatic, @function\r
.regstk 5, 0, 0, 0\r
PalCallStatic::\r
- cmp.ne p6, p7 = r0, in0\r
+ cmp.eq p6 = r0, in0\r
mov r31 = in4\r
mov r8 = ip\r
(p6) mov in0 = ar.k5\r
br.cond.sptk b7\r
PalProcReturn:\r
mov psr.l = in3\r
- cmp.eq p6, p7 = in0, in1 // in1 == PAL_COPY_PAL?\r
-(p6) cmp.eq p6, p7 = r0, r8 // Status == Success?\r
+ cmp.eq p6 = in0, in1 // in1 == PAL_COPY_PAL?\r
+(p6) cmp.eq p6 = r0, r8 // Status == Success?\r
+(p6) add in2 = r9, in2\r
(p6) mov ar.k5 = in2\r
mov b0 = in4\r
br.ret.sptk.many b0\r
--- /dev/null
+/// @file\r
+/// Contains an implementation of longjmp for the Itanium-based architecture.\r
+///\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution. The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: longjmp.s\r
+///\r
+///\r
+\r
+.auto\r
+.text\r
+\r
+.proc InternalLongJump\r
+.type InternalLongJump, @function\r
+.regstk 2, 0, 0, 0\r
+InternalLongJump::\r
+ add r10 = 0x10*20 + 8*14, in0\r
+ movl r2 = ~((((1 << 14) - 1) << 16) | 3)\r
+\r
+ ld8.nt1 r14 = [r10], -8*2 // BSP, skip PFS\r
+ mov r15 = ar.bspstore // BSPSTORE\r
+\r
+ ld8.nt1 r17 = [r10], -8 // UNAT after spill\r
+ mov r16 = ar.rsc // RSC\r
+ cmp.leu p6 = r14, r15\r
+\r
+ ld8.nt1 r18 = [r10], -8 // UNAT\r
+ ld8.nt1 r25 = [r10], -8 // b5\r
+ and r2 = r16, r2\r
+\r
+ ldf.fill.nt1 f2 = [in0], 0x10\r
+ ld8.nt1 r24 = [r10], -8 // b4\r
+ mov b5 = r25\r
+\r
+ mov ar.rsc = r2\r
+ ld8.nt1 r23 = [r10], -8 // b3\r
+ mov b4 = r24\r
+\r
+ ldf.fill.nt1 f3 = [in0], 0x10\r
+ mov ar.unat = r17\r
+(p6) br.spnt.many _skip_flushrs\r
+\r
+ flushrs\r
+ mov r15 = ar.bsp // New BSPSTORE\r
+\r
+_skip_flushrs:\r
+ mov r31 = ar.rnat // RNAT\r
+ loadrs\r
+\r
+ ldf.fill.nt1 f4 = [in0], 0x10\r
+ ld8.nt1 r22 = [r10], -8\r
+ dep r2 = -1, r14, 3, 6\r
+\r
+ ldf.fill.nt1 f5 = [in0], 0x10\r
+ ld8.nt1 r21 = [r10], -8\r
+ cmp.ltu p6 = r2, r15\r
+\r
+ ld8.nt1 r20 = [r10], -0x10 // skip sp\r
+(p6) ld8.nta r31 = [r2]\r
+ mov b3 = r23\r
+\r
+ ldf.fill.nt1 f16 = [in0], 0x10\r
+ ld8.fill.nt1 r7 = [r10], -8\r
+ mov b2 = r22\r
+\r
+ ldf.fill.nt1 f17 = [in0], 0x10\r
+ ld8.fill.nt1 r6 = [r10], -8\r
+ mov b1 = r21\r
+\r
+ ldf.fill.nt1 f18 = [in0], 0x10\r
+ ld8.fill.nt1 r5 = [r10], -8\r
+ mov b0 = r20\r
+\r
+ ldf.fill.nt1 f19 = [in0], 0x10\r
+ ld8.fill.nt1 r4 = [r10], 8*13\r
+\r
+ ldf.fill.nt1 f20 = [in0], 0x10\r
+ ld8.nt1 r19 = [r10], 0x10 // PFS\r
+\r
+ ldf.fill.nt1 f21 = [in0], 0x10\r
+ ld8.nt1 r26 = [r10], 8 // Predicate\r
+ mov ar.pfs = r19\r
+\r
+ ldf.fill.nt1 f22 = [in0], 0x10\r
+ ld8.nt1 r27 = [r10], 8 // LC\r
+ mov pr = r26, -1\r
+\r
+ ldf.fill.nt1 f23 = [in0], 0x10\r
+ ld8.nt1 r28 = [r10], -17*8 - 0x10\r
+ mov ar.lc = r27\r
+\r
+ ldf.fill.nt1 f24 = [in0], 0x10\r
+ ldf.fill.nt1 f25 = [in0], 0x10\r
+ mov r8 = in1\r
+\r
+ ldf.fill.nt1 f26 = [in0], 0x10\r
+ ldf.fill.nt1 f31 = [r10], -0x10\r
+\r
+ ldf.fill.nt1 f27 = [in0], 0x10\r
+ ldf.fill.nt1 f30 = [r10], -0x10\r
+\r
+ ldf.fill.nt1 f28 = [in0]\r
+ ldf.fill.nt1 f29 = [r10], 0x10*3 + 8*4\r
+\r
+ ld8.fill.nt1 sp = [r10]\r
+ mov ar.unat = r18\r
+\r
+ mov ar.bspstore = r14\r
+ mov ar.rnat = r31\r
+\r
+ invala\r
+ mov ar.rsc = r16\r
+ br.ret.sptk b0\r
+.endp\r
/// @file\r
-/// Contains an implementation of setjmp and longjmp for the\r
-/// Itanium-based architecture.\r
+/// Contains an implementation of longjmp for the Itanium-based architecture.\r
///\r
-/// Copyright (c) 2006, Intel Corporation \r
-/// All rights reserved. This program and the accompanying materials \r
-/// are licensed and made available under the terms and conditions of the BSD License \r
-/// which accompanies this distribution. The full text of the license may be found at \r
-/// http://opensource.org/licenses/bsd-license.php \r
-/// \r
-/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-/// \r
-/// Module Name: setjmp.s\r
+/// Copyright (c) 2006, Intel Corporation\r
+/// All rights reserved. This program and the accompanying materials\r
+/// are licensed and made available under the terms and conditions of the BSD License\r
+/// which accompanies this distribution. The full text of the license may be found at\r
+/// http://opensource.org/licenses/bsd-license.php\r
+///\r
+/// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+/// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+///\r
+/// Module Name: longjmp.s\r
///\r
///\r
\r
- .file "setjmp.s"\r
+.auto\r
+.text\r
\r
-#include "asm.h"\r
-#include "ia_64gen.h"\r
+.global InternalAssertJumpBuffer\r
+.type InternalAssertJumpBuffer, @function\r
\r
-/// int SetJump(struct jmp_buffer save)\r
-///\r
-/// Setup a non-local goto.\r
-///\r
-/// Description:\r
-///\r
-/// SetJump stores the current register set in the area pointed to\r
-/// by "save". It returns zero. Subsequent calls to "LongJump" will\r
-/// restore the registers and return non-zero to the same location.\r
-///\r
-/// On entry, r32 contains the pointer to the jmp_buffer\r
-///\r
+.proc SetJump\r
+.type SetJump, @function\r
+SetJump::\r
+ alloc loc0 = ar.pfs, 1, 2, 1, 0\r
+ mov loc1 = b0\r
+ mov out0 = in0\r
+\r
+ brl.call.sptk.many b0 = InternalAssertJumpBuffer\r
+\r
+ mov r14 = ar.unat\r
+ mov r15 = ar.bsp\r
+ add r10 = 0x10*20, in0\r
+\r
+ stf.spill.nta [in0] = f2, 0x10\r
+ st8.spill.nta [r10] = r4, 8\r
+ mov r21 = b1\r
+\r
+ stf.spill.nta [in0] = f3, 0x10\r
+ st8.spill.nta [r10] = r5, 8\r
+ mov r22 = b2\r
\r
-PROCEDURE_ENTRY(SetJump)\r
- //\r
- // Make sure buffer is aligned at 16byte boundary\r
- //\r
- mov r32 = r33 \r
+ stf.spill.nta [in0] = f4, 0x10\r
+ st8.spill.nta [r10] = r6, 8\r
+ mov r23 = b3\r
\r
- add r10 = -0x10,r0 ;; // mask the lower 4 bits\r
- and r32 = r32, r10;; \r
- add r32 = 0x10, r32;; // move to next 16 byte boundary\r
+ stf.spill.nta [in0] = f5, 0x10\r
+ st8.spill.nta [r10] = r7, 8\r
+ mov r24 = b4\r
\r
- add r10 = J_PREDS, r32 // skip Unats & pfs save area\r
- add r11 = J_BSP, r32\r
- //\r
- // save immediate context\r
- //\r
- mov r2 = ar.bsp // save backing store pointer\r
- mov r3 = pr // save predicates\r
- ;;\r
- //\r
- // save user Unat register\r
- //\r
- mov r16 = ar.lc // save loop count register\r
- mov r14 = ar.unat // save user Unat register\r
+ stf.spill.nta [in0] = f16, 0x10\r
+ st8.spill.nta [r10] = sp, 8\r
+ mov r25 = b5\r
\r
- st8 [r10] = r3, J_LC-J_PREDS\r
- st8 [r11] = r2, J_R4-J_BSP\r
- ;;\r
- st8 [r10] = r16, J_R5-J_LC\r
- st8 [r32] = r14, J_NATS // Note: Unat at the \r
- // beginning of the save area\r
- mov r15 = ar.pfs\r
- ;;\r
- //\r
- // save preserved general registers & NaT's\r
- //\r
- st8.spill [r11] = r4, J_R6-J_R4\r
- ;;\r
- st8.spill [r10] = r5, J_R7-J_R5 \r
- ;;\r
- st8.spill [r11] = r6, J_SP-J_R6\r
- ;;\r
- st8.spill [r10] = r7, J_F3-J_R7 \r
- ;;\r
- st8.spill [r11] = sp, J_F2-J_SP\r
- ;;\r
- //\r
- // save spilled Unat and pfs registers\r
- //\r
- mov r2 = ar.unat // save Unat register after spill\r
- ;;\r
- st8 [r32] = r2, J_PFS-J_NATS // save unat for spilled regs\r
- ;;\r
- st8 [r32] = r15 // save pfs\r
- //\r
- // save floating registers \r
- //\r
- stf.spill [r11] = f2, J_F4-J_F2\r
- stf.spill [r10] = f3, J_F5-J_F3 \r
- ;;\r
- stf.spill [r11] = f4, J_F16-J_F4\r
- stf.spill [r10] = f5, J_F17-J_F5 \r
- ;;\r
- stf.spill [r11] = f16, J_F18-J_F16\r
- stf.spill [r10] = f17, J_F19-J_F17 \r
- ;;\r
- stf.spill [r11] = f18, J_F20-J_F18\r
- stf.spill [r10] = f19, J_F21-J_F19 \r
- ;;\r
- stf.spill [r11] = f20, J_F22-J_F20\r
- stf.spill [r10] = f21, J_F23-J_F21 \r
- ;;\r
- stf.spill [r11] = f22, J_F24-J_F22\r
- stf.spill [r10] = f23, J_F25-J_F23 \r
- ;;\r
- stf.spill [r11] = f24, J_F26-J_F24\r
- stf.spill [r10] = f25, J_F27-J_F25 \r
- ;;\r
- stf.spill [r11] = f26, J_F28-J_F26\r
- stf.spill [r10] = f27, J_F29-J_F27 \r
- ;;\r
- stf.spill [r11] = f28, J_F30-J_F28\r
- stf.spill [r10] = f29, J_F31-J_F29 \r
- ;;\r
- stf.spill [r11] = f30, J_FPSR-J_F30\r
- stf.spill [r10] = f31, J_B0-J_F31 // size of f31 + fpsr\r
- //\r
- // save FPSR register & branch registers\r
- //\r
- mov r2 = ar.fpsr // save fpsr register\r
- mov r3 = b0 \r
- ;;\r
- st8 [r11] = r2, J_B1-J_FPSR\r
- st8 [r10] = r3, J_B2-J_B0\r
- mov r2 = b1\r
- mov r3 = b2 \r
- ;;\r
- st8 [r11] = r2, J_B3-J_B1\r
- st8 [r10] = r3, J_B4-J_B2\r
- mov r2 = b3\r
- mov r3 = b4 \r
- ;;\r
- st8 [r11] = r2, J_B5-J_B3\r
- st8 [r10] = r3\r
- mov r2 = b5 \r
- ;;\r
- st8 [r11] = r2\r
- ;;\r
- //\r
- // return\r
- //\r
- mov r8 = r0 // return 0 from setjmp\r
- mov ar.unat = r14 // restore unat\r
- br.ret.sptk b0\r
+ stf.spill.nta [in0] = f17, 0x10\r
+ st8.nta [r10] = loc1, 8\r
+ mov r16 = pr\r
\r
-PROCEDURE_EXIT(SetJump)\r
+ stf.spill.nta [in0] = f18, 0x10\r
+ st8.nta [r10] = r21, 8\r
+ mov r17 = ar.lc\r
\r
+ stf.spill.nta [in0] = f19, 0x10\r
+ st8.nta [r10] = r22, 8\r
\r
-//\r
-// void _LongJump(struct jmp_buffer *)\r
-//\r
-// Perform a non-local goto.\r
-//\r
-// Description:\r
-//\r
-// LongJump initializes the register set to the values saved by a\r
-// previous 'SetJump' and jumps to the return location saved by that\r
-// 'SetJump'. This has the effect of unwinding the stack and returning\r
-// for a second time to the 'SetJump'.\r
-//\r
+ stf.spill.nta [in0] = f20, 0x10\r
+ st8.nta [r10] = r23, 8\r
\r
-PROCEDURE_ENTRY(_LongJump)\r
- //\r
- // Make sure buffer is aligned at 16byte boundary\r
- //\r
- mov r32 = r33 \r
+ stf.spill.nta [in0] = f21, 0x10\r
+ st8.nta [r10] = r24, 8\r
\r
- add r10 = -0x10,r0 ;; // mask the lower 4 bits\r
- and r32 = r32, r10;; \r
- add r32 = 0x10, r32;; // move to next 16 byte boundary\r
+ stf.spill.nta [in0] = f22, 0x10\r
+ st8.nta [r10] = r25, 8\r
\r
- //\r
- // caching the return value as we do invala in the end\r
- //\r
-/// mov r8 = r33 // return value\r
- mov r8 = 1 // For now return hard coded 1\r
+ stf.spill.nta [in0] = f23, 0x10\r
+ mov r18 = ar.unat\r
\r
- //\r
- // get immediate context\r
- //\r
- mov r14 = ar.rsc // get user RSC conf \r
- add r10 = J_PFS, r32 // get address of pfs\r
- add r11 = J_NATS, r32\r
- ;;\r
- ld8 r15 = [r10], J_BSP-J_PFS // get pfs\r
- ld8 r2 = [r11], J_LC-J_NATS // get unat for spilled regs\r
- ;;\r
- mov ar.unat = r2\r
- ;;\r
- ld8 r16 = [r10], J_PREDS-J_BSP // get backing store pointer\r
- mov ar.rsc = r0 // put RSE in enforced lazy \r
- mov ar.pfs = r15\r
- ;;\r
- \r
- //\r
- // while returning from longjmp the BSPSTORE and BSP needs to be\r
- // same and discard all the registers allocated after we did\r
- // setjmp. Also, we need to generate the RNAT register since we\r
- // did not flushed the RSE on setjmp.\r
- //\r
- mov r17 = ar.bspstore // get current BSPSTORE\r
- ;;\r
- cmp.ltu p6,p7 = r17, r16 // is it less than BSP of \r
-(p6) br.spnt.few .flush_rse\r
- mov r19 = ar.rnat // get current RNAT\r
- ;;\r
- loadrs // invalidate dirty regs\r
- br.sptk.many .restore_rnat // restore RNAT\r
+ stf.spill.nta [in0] = f24, 0x10\r
+ st8.nta [r10] = r14, 8 // UNAT\r
\r
-.flush_rse:\r
- flushrs\r
- ;;\r
- mov r19 = ar.rnat // get current RNAT\r
- mov r17 = r16 // current BSPSTORE\r
- ;;\r
-.restore_rnat:\r
- //\r
- // check if RNAT is saved between saved BSP and curr BSPSTORE\r
- //\r
- dep r18 = 1,r16,3,6 // get RNAT address\r
- ;;\r
- cmp.ltu p8,p9 = r18, r17 // RNAT saved on RSE\r
- ;;\r
-(p8) ld8 r19 = [r18] // get RNAT from RSE\r
- ;;\r
- mov ar.bspstore = r16 // set new BSPSTORE \r
- ;;\r
- mov ar.rnat = r19 // restore RNAT\r
- mov ar.rsc = r14 // restore RSC conf\r
+ stf.spill.nta [in0] = f25, 0x10\r
+ st8.nta [r10] = r18, 8 // UNAT after spill\r
\r
+ stf.spill.nta [in0] = f26, 0x10\r
+ st8.nta [r10] = loc0, 8 // PFS\r
\r
- ld8 r3 = [r11], J_R4-J_LC // get lc register\r
- ld8 r2 = [r10], J_R5-J_PREDS // get predicates\r
- ;;\r
- mov pr = r2, -1\r
- mov ar.lc = r3\r
- //\r
- // restore preserved general registers & NaT's\r
- //\r
- ld8.fill r4 = [r11], J_R6-J_R4\r
- ;;\r
- ld8.fill r5 = [r10], J_R7-J_R5 \r
- ld8.fill r6 = [r11], J_SP-J_R6\r
- ;;\r
- ld8.fill r7 = [r10], J_F2-J_R7\r
- ld8.fill sp = [r11], J_F3-J_SP\r
- ;;\r
- //\r
- // restore floating registers \r
- //\r
- ldf.fill f2 = [r10], J_F4-J_F2\r
- ldf.fill f3 = [r11], J_F5-J_F3 \r
- ;;\r
- ldf.fill f4 = [r10], J_F16-J_F4\r
- ldf.fill f5 = [r11], J_F17-J_F5 \r
- ;;\r
- ldf.fill f16 = [r10], J_F18-J_F16\r
- ldf.fill f17 = [r11], J_F19-J_F17\r
- ;;\r
- ldf.fill f18 = [r10], J_F20-J_F18\r
- ldf.fill f19 = [r11], J_F21-J_F19\r
- ;;\r
- ldf.fill f20 = [r10], J_F22-J_F20\r
- ldf.fill f21 = [r11], J_F23-J_F21\r
- ;;\r
- ldf.fill f22 = [r10], J_F24-J_F22\r
- ldf.fill f23 = [r11], J_F25-J_F23 \r
- ;;\r
- ldf.fill f24 = [r10], J_F26-J_F24\r
- ldf.fill f25 = [r11], J_F27-J_F25\r
- ;;\r
- ldf.fill f26 = [r10], J_F28-J_F26\r
- ldf.fill f27 = [r11], J_F29-J_F27\r
- ;;\r
- ldf.fill f28 = [r10], J_F30-J_F28\r
- ldf.fill f29 = [r11], J_F31-J_F29 \r
- ;;\r
- ldf.fill f30 = [r10], J_FPSR-J_F30\r
- ldf.fill f31 = [r11], J_B0-J_F31 ;;\r
+ stf.spill.nta [in0] = f27, 0x10\r
+ st8.nta [r10] = r15, 8 // BSP\r
+ mov r8 = 0\r
\r
- //\r
- // restore branch registers and fpsr\r
- //\r
- ld8 r16 = [r10], J_B1-J_FPSR // get fpsr\r
- ld8 r17 = [r11], J_B2-J_B0 // get return pointer\r
- ;;\r
- mov ar.fpsr = r16\r
- mov b0 = r17\r
- ld8 r2 = [r10], J_B3-J_B1\r
- ld8 r3 = [r11], J_B4-J_B2\r
- ;;\r
- mov b1 = r2\r
- mov b2 = r3\r
- ld8 r2 = [r10], J_B5-J_B3\r
- ld8 r3 = [r11]\r
- ;;\r
- mov b3 = r2\r
- mov b4 = r3 \r
- ld8 r2 = [r10]\r
- ld8 r21 = [r32] // get user unat\r
- ;;\r
- mov b5 = r2\r
- mov ar.unat = r21\r
+ stf.spill.nta [in0] = f28, 0x10\r
+ mov r19 = ar.fpsr\r
\r
- //\r
- // invalidate ALAT\r
- //\r
- invala ;;\r
+ stf.spill.nta [in0] = f29, 0x10\r
+ st8.nta [r10] = r16, 8 // PR\r
+ mov ar.pfs = loc0\r
\r
- br.ret.sptk b0\r
-PROCEDURE_EXIT(_LongJump)\r
+ stf.spill.nta [in0] = f30, 0x10\r
+ st8.nta [r10] = r17, 8 // LC\r
+ mov b0 = loc1\r
\r
+ stf.spill.nta [in0] = f31, 0x10\r
+ st8.nta [r10] = r19 // FPSR\r
\r
+ mov ar.unat = r14\r
+ br.ret.sptk b0\r
+.endp SetJump\r
/** @file\r
- Long Jump functions. \r
+ Long Jump functions.\r
\r
Copyright (c) 2006, Intel Corporation\r
All rights reserved. This program and the accompanying materials\r
\r
VOID\r
EFIAPI\r
-_LongJump (\r
- IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
- IN UINTN Value\r
+InternalAssertJumpBuffer (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+InternalLongJump (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
+ IN UINTN Value\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
LongJump (\r
- IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
- IN UINTN Value\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer,\r
+ IN UINTN Value\r
)\r
{\r
- ASSERT (JumpBuffer != NULL);\r
- ASSERT (Value != 0);\r
- \r
- _LongJump (JumpBuffer, Value);\r
+ InternalAssertJumpBuffer (JumpBuffer);\r
+ InternalLongJump (JumpBuffer, Value);\r
}\r
--- /dev/null
+/** @file\r
+ Internal ASSERT () functions for SetJump.\r
+\r
+ Copyright (c) 2006, Intel Corporation\r
+ All rights reserved. This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ Module Name: SetJumpLongJump.c\r
+\r
+**/\r
+\r
+VOID\r
+EFIAPI\r
+InternalAssertJumpBuffer (\r
+ IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer\r
+ )\r
+{\r
+ ASSERT (JumpBuffer != NULL);\r
+\r
+#ifdef MDE_CPU_IPF\r
+ ASSERT (((UINTN)JumpBuffer & 0xf) == 0);\r
+#endif\r
+}\r
{\r
ASSERT (EntryPoint != NULL && NewStack != NULL);\r
\r
+#ifdef MDE_CPU_IPF\r
+ ASSERT (((UINTN)NewStack & 0xf) == 0);\r
+#endif\r
+\r
InternalSwitchStack (EntryPoint, Context1, Context2, NewStack);\r
}\r
--- /dev/null
+;------------------------------------------------------------------------------
+;
+; Copyright (c) 2006, Intel Corporation
+; All rights reserved. This program and the accompanying materials
+; are licensed and made available under the terms and conditions of the BSD License
+; which accompanies this distribution. The full text of the license may be found at
+; http://opensource.org/licenses/bsd-license.php
+;
+; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+;
+; Module Name:
+;
+; CpuId.Asm
+;
+; Abstract:
+;
+; AsmCpuid function
+;
+; Notes:
+;
+;------------------------------------------------------------------------------
+
+ .code
+
+;------------------------------------------------------------------------------
+; UINT32
+; EFIAPI
+; AsmCpuid (
+; IN UINT32 RegisterInEax,
+; IN UINT32 RegisterInEcx,
+; OUT UINT32 *RegisterOutEax OPTIONAL,
+; OUT UINT32 *RegisterOutEbx OPTIONAL,
+; OUT UINT32 *RegisterOutEcx OPTIONAL,
+; OUT UINT32 *RegisterOutEdx OPTIONAL
+; )
+;------------------------------------------------------------------------------
+AsmCpuidEx PROC USES rbx
+ mov eax, ecx
+ mov ecx, edx
+ push rax ; save Index on stack
+ cpuid
+ mov r10, [rsp + 38h]
+ test r10, r10
+ jz @F
+ mov [r10], ecx
+@@:
+ mov rcx, r8
+ jrcxz @F
+ mov [rcx], eax
+@@:
+ mov rcx, r9
+ jrcxz @F
+ mov [rcx], ebx
+@@:
+ mov rcx, [rsp + 40h]
+ jrcxz @F
+ mov [rcx], edx
+@@:
+ pop rax ; restore Index to rax as return value
+ ret
+AsmCpuidEx ENDP
+
+ END
\r
.code\r
\r
-_LongJump PROC\r
+IntenralLongJump PROC\r
mov rbx, [rcx]\r
mov rsp, [rcx + 8]\r
mov rbp, [rcx + 10h]\r
mov r15, [rcx + 40h]\r
mov rax, rdx\r
jmp qword ptr [rcx + 48h]\r
-_LongJump ENDP\r
+IntenralLongJump ENDP\r
\r
END\r
\r
.code\r
\r
+EXTERNDEF InternalAssertJumpBuffer:PROC\r
+\r
SetJump PROC\r
+ push rcx\r
+ add rsp, -20h\r
+ call InternalAssertJumpBuffer\r
+ add rsp, 20h\r
+ pop rcx\r
pop rdx\r
mov [rcx], rbx\r
mov [rcx + 8], rsp\r
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