+++ /dev/null
-/** @file\r
- Main PAL API's defined in Intel Itanium Architecture Software Developer's Manual.\r
-\r
- Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
- SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#ifndef __PAL_API_H__\r
-#define __PAL_API_H__\r
-\r
-#define PAL_SUCCESS 0x0\r
-\r
-///\r
-/// CacheType of PAL_CACHE_FLUSH.\r
-///\r
-#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r
-#define PAL_CACHE_FLUSH_DATA_ALL 2\r
-#define PAL_CACHE_FLUSH_ALL 3\r
-#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r
-\r
-\r
-///\r
-/// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
-///\r
-#define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0\r
-#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0\r
-#define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1\r
-#define PAL_CACHE_FLUSH_NO_INTERRUPT 0\r
-\r
-/**\r
- PAL Procedure - PAL_CACHE_FLUSH.\r
-\r
- Flush the instruction or data caches. It is required by Itanium processors.\r
- The PAL procedure supports the Static Registers calling\r
- convention. It could be called at virtual mode and physical\r
- mode.\r
-\r
- @param Index Index of PAL_CACHE_FLUSH within the\r
- list of PAL procedures.\r
- @param CacheType Unsigned 64-bit integer indicating\r
- which cache to flush.\r
- @param Operation Formatted bit vector indicating the\r
- operation of this call.\r
- @param ProgressIndicator Unsigned 64-bit integer specifying\r
- the starting position of the flush\r
- operation.\r
-\r
- @retval 2 Call completed without error, but a PMI\r
- was taken during the execution of this\r
- procedure.\r
- @retval 1 Call has not completed flushing due to\r
- a pending interrupt.\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error\r
-\r
- @return R9 Unsigned 64-bit integer specifying the vector\r
- number of the pending interrupt.\r
- @return R10 Unsigned 64-bit integer specifying the\r
- starting position of the flush operation.\r
- @return R11 Unsigned 64-bit integer specifying the vector\r
- number of the pending interrupt.\r
-\r
-**/\r
-#define PAL_CACHE_FLUSH 1\r
-\r
-\r
-///\r
-/// Attributes of PAL_CACHE_CONFIG_INFO1\r
-///\r
-#define PAL_CACHE_ATTR_WT 0\r
-#define PAL_CACHE_ATTR_WB 1\r
-\r
-///\r
-/// PAL_CACHE_CONFIG_INFO1.StoreHint\r
-///\r
-#define PAL_CACHE_STORE_TEMPORAL 0\r
-#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
-\r
-///\r
-/// PAL_CACHE_CONFIG_INFO1.StoreHint\r
-///\r
-#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
-#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
-\r
-///\r
-/// PAL_CACHE_CONFIG_INFO1.StoreHint\r
-///\r
-#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
-#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
-#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
-\r
-///\r
-/// Detail the characteristics of a given processor controlled\r
-/// cache in the cache hierarchy.\r
-///\r
-typedef struct {\r
- UINT64 IsUnified : 1;\r
- UINT64 Attributes : 2;\r
- UINT64 Associativity:8;\r
- UINT64 LineSize:8;\r
- UINT64 Stride:8;\r
- UINT64 StoreLatency:8;\r
- UINT64 StoreHint:8;\r
- UINT64 LoadHint:8;\r
-} PAL_CACHE_INFO_RETURN1;\r
-\r
-///\r
-/// Detail the characteristics of a given processor controlled\r
-/// cache in the cache hierarchy.\r
-///\r
-typedef struct {\r
- UINT64 CacheSize:32;\r
- UINT64 AliasBoundary:8;\r
- UINT64 TagLsBits:8;\r
- UINT64 TagMsBits:8;\r
-} PAL_CACHE_INFO_RETURN2;\r
-\r
-/**\r
- PAL Procedure - PAL_CACHE_INFO.\r
-\r
- Return detailed instruction or data cache information. It is\r
- required by Itanium processors. The PAL procedure supports the Static\r
- Registers calling convention. It could be called at virtual\r
- mode and physical mode.\r
-\r
- @param Index Index of PAL_CACHE_INFO within the list of\r
- PAL procedures.\r
- @param CacheLevel Unsigned 64-bit integer specifying the\r
- level in the cache hierarchy for which\r
- information is requested. This value must\r
- be between 0 and one less than the value\r
- returned in the cache_levels return value\r
- from PAL_CACHE_SUMMARY.\r
- @param CacheType Unsigned 64-bit integer with a value of 1\r
- for instruction cache and 2 for data or\r
- unified cache. All other values are\r
- reserved.\r
- @param Reserved Should be 0.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error\r
-\r
- @return R9 Detail the characteristics of a given\r
- processor controlled cache in the cache\r
- hierarchy. See PAL_CACHE_INFO_RETURN1.\r
- @return R10 Detail the characteristics of a given\r
- processor controlled cache in the cache\r
- hierarchy. See PAL_CACHE_INFO_RETURN2.\r
- @return R11 Reserved with 0.\r
-\r
-**/\r
-#define PAL_CACHE_INFO 2\r
-\r
-\r
-\r
-///\r
-/// Level of PAL_CACHE_INIT.\r
-///\r
-#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
-\r
-///\r
-/// CacheType\r
-///\r
-#define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1\r
-#define PAL_CACHE_INIT_TYPE_DATA 0x2\r
-#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3\r
-\r
-///\r
-/// Restrict of PAL_CACHE_INIT.\r
-///\r
-#define PAL_CACHE_INIT_NO_RESTRICT 0\r
-#define PAL_CACHE_INIT_RESTRICTED 1\r
-\r
-/**\r
- PAL Procedure - PAL_CACHE_INIT.\r
-\r
- Initialize the instruction or data caches. It is required by\r
- Itanium processors. The PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical mode.\r
-\r
- @param Index Index of PAL_CACHE_INIT within the list of PAL\r
- procedures.\r
- @param Level Unsigned 64-bit integer containing the level of\r
- cache to initialize. If the cache level can be\r
- initialized independently, only that level will\r
- be initialized. Otherwise\r
- implementation-dependent side-effects will\r
- occur.\r
- @param CacheType Unsigned 64-bit integer with a value of 1 to\r
- initialize the instruction cache, 2 to\r
- initialize the data cache, or 3 to\r
- initialize both. All other values are\r
- reserved.\r
- @param Restrict Unsigned 64-bit integer with a value of 0 or\r
- 1. All other values are reserved. If\r
- restrict is 1 and initializing the specified\r
- level and cache_type of the cache would\r
- cause side-effects, PAL_CACHE_INIT will\r
- return -4 instead of initializing the cache.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -4 Call could not initialize the specified\r
- level and cache_type of the cache without\r
- side-effects and restrict was 1.\r
-\r
-**/\r
-#define PAL_CACHE_INIT 3\r
-\r
-\r
-///\r
-/// PAL_CACHE_PROTECTION.Method.\r
-///\r
-#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
-#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
-#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
-#define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r
-\r
-\r
-\r
-///\r
-/// PAL_CACHE_PROTECTION.TagOrData.\r
-///\r
-#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
-#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
-#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
-#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r
-\r
-///\r
-/// 32-bit protection information structures.\r
-///\r
-typedef struct {\r
- UINT32 DataBits:8;\r
- UINT32 TagProtLsb:6;\r
- UINT32 TagProtMsb:6;\r
- UINT32 ProtBits:6;\r
- UINT32 Method:4;\r
- UINT32 TagOrData:2;\r
-} PAL_CACHE_PROTECTION;\r
-\r
-/**\r
- PAL Procedure - PAL_CACHE_PROT_INFO.\r
-\r
- Return instruction or data cache protection information. It is\r
- required by Itanium processors. The PAL procedure supports the Static\r
- Registers calling convention. It could be called at physical\r
- mode and Virtual mode.\r
-\r
- @param Index Index of PAL_CACHE_PROT_INFO within the list of\r
- PAL procedures.\r
- @param CacheLevel Unsigned 64-bit integer specifying the level\r
- in the cache hierarchy for which information\r
- is requested. This value must be between 0\r
- and one less than the value returned in the\r
- cache_levels return value from\r
- PAL_CACHE_SUMMARY.\r
- @param CacheType Unsigned 64-bit integer with a value of 1\r
- for instruction cache and 2 for data or\r
- unified cache. All other values are\r
- reserved.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Detail the characteristics of a given\r
- processor controlled cache in the cache\r
- hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
- @return R10 Detail the characteristics of a given\r
- processor controlled cache in the cache\r
- hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
- @return R11 Detail the characteristics of a given\r
- processor controlled cache in the cache\r
- hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
-\r
-**/\r
-#define PAL_CACHE_PROT_INFO 38\r
-\r
-typedef struct {\r
- UINT64 ThreadId : 16; ///< The thread identifier of the logical\r
- ///< processor for which information is being\r
- ///< returned. This value will be unique on a per core basis.\r
- UINT64 Reserved1: 16;\r
- UINT64 CoreId: 16; ///< The core identifier of the logical processor\r
- ///< for which information is being returned.\r
- ///< This value will be unique on a per physical\r
- ///< processor package basis.\r
- UINT64 Reserved2: 16;\r
-} PAL_PCOC_N_CACHE_INFO1;\r
-\r
-\r
-typedef struct {\r
- UINT64 LogicalAddress : 16; ///< Logical address: geographical address\r
- ///< of the logical processor for which\r
- ///< information is being returned. This is\r
- ///< the same value that is returned by the\r
- ///< PAL_FIXED_ADDR procedure when it is\r
- ///< called on the logical processor.\r
- UINT64 Reserved1: 16;\r
- UINT64 Reserved2: 32;\r
-} PAL_PCOC_N_CACHE_INFO2;\r
-\r
-/**\r
- PAL Procedure - PAL_CACHE_SHARED_INFO.\r
-\r
- Returns information on which logical processors share caches.\r
- It is optional. The PAL procedure supports the Static\r
- Registers calling convention. It could be called at physical\r
- mode and Virtual mode.\r
-\r
- @param Index Index of PAL_CACHE_SHARED_INFO within the list\r
- of PAL procedures.\r
- @param CacheLevel Unsigned 64-bit integer specifying the\r
- level in the cache hierarchy for which\r
- information is requested. This value must\r
- be between 0 and one less than the value\r
- returned in the cache_levels return value\r
- from PAL_CACHE_SUMMARY.\r
- @param CacheType Unsigned 64-bit integer with a value of 1\r
- for instruction cache and 2 for data or\r
- unified cache. All other values are\r
- reserved.\r
- @param ProcNumber Unsigned 64-bit integer that specifies for\r
- which logical processor information is\r
- being requested. This input argument must\r
- be zero for the first call to this\r
- procedure and can be a maximum value of\r
- one less than the number of logical\r
- processors sharing this cache, which is\r
- returned by the num_shared return value.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Unsigned integer that returns the number of\r
- logical processors that share the processor\r
- cache level and type, for which information was\r
- requested.\r
- @return R10 The format of PAL_PCOC_N_CACHE_INFO1.\r
- @return R11 The format of PAL_PCOC_N_CACHE_INFO2.\r
-\r
-**/\r
-#define PAL_CACHE_SHARED_INFO 43\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_CACHE_SUMMARY.\r
-\r
- Return a summary of the cache hierarchy. It is required by\r
- Itanium processors. The PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical mode and Virtual\r
- mode.\r
-\r
- @param Index Index of PAL_CACHE_SUMMARY within the list of\r
- PAL procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 CacheLevels Unsigned 64-bit integer denoting the\r
- number of levels of cache\r
- implemented by the processor.\r
- Strictly, this is the number of\r
- levels for which the cache\r
- controller is integrated into the\r
- processor (the cache SRAMs may be\r
- external to the processor).\r
- @return R10 UniqueCaches Unsigned 64-bit integer denoting the\r
- number of unique caches implemented\r
- by the processor. This has a maximum\r
- of 2*cache_levels, but may be less\r
- if any of the levels in the cache\r
- hierarchy are unified caches or do\r
- not have both instruction and data\r
- caches.\r
-\r
-**/\r
-#define PAL_CACHE_SUMMARY 4\r
-\r
-\r
-//\r
-// Virtual Memory Attributes implemented by processor.\r
-//\r
-#define PAL_MEMORY_ATTR_WB 0\r
-#define PAL_MEMORY_ATTR_WC 6\r
-#define PAL_MEMORY_ATTR_UC 4\r
-#define PAL_MEMORY_ATTR_UCE 5\r
-#define PAL_MEMORY_ATTR_NATPAGE 7\r
-\r
-/**\r
- PAL Procedure - PAL_MEM_ATTRIB.\r
-\r
- Return a list of supported memory attributes.. It is required\r
- by Itanium processors. The PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical mode and Virtual\r
- mode.\r
-\r
- @param Index Index of PAL_MEM_ATTRIB within the list of PAL\r
- procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Attributes 8-bit vector of memory attributes\r
- implemented by processor. See Virtual\r
- Memory Attributes above.\r
-\r
-**/\r
-\r
-#define PAL_MEM_ATTRIB 5\r
-\r
-/**\r
- PAL Procedure - PAL_PREFETCH_VISIBILITY.\r
-\r
- Used in architected sequence to transition pages from a\r
- cacheable, speculative attribute to an uncacheable attribute.\r
- It is required by Itanium processors. The PAL procedure supports the Static\r
- Registers calling convention. It could be called at physical\r
- mode and Virtual mode.\r
-\r
- @param Index Index of PAL_PREFETCH_VISIBILITY within the list\r
- of PAL procedures.\r
- @param TransitionType Unsigned integer specifying the type\r
- of memory attribute transition that is\r
- being performed.\r
-\r
- @retval 1 Call completed without error; this\r
- call is not necessary on remote\r
- processors.\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_PREFETCH_VISIBILITY 41\r
-\r
-/**\r
- PAL Procedure - PAL_PTCE_INFO.\r
-\r
- Return information needed for ptc.e instruction to purge\r
- entire TC. It is required by Itanium processors. The PAL procedure supports\r
- the Static Registers calling convention. It could be called at\r
- physical mode and Virtual mode.\r
-\r
- @param Index Index of PAL_PTCE_INFO within the list\r
- of PAL procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Unsigned 64-bit integer denoting the beginning\r
- address to be used by the first PTCE instruction\r
- in the purge loop.\r
- @return R10 Two unsigned 32-bit integers denoting the loop\r
- counts of the outer (loop 1) and inner (loop 2)\r
- purge loops. count1 (loop 1) is contained in bits\r
- 63:32 of the parameter, and count2 (loop 2) is\r
- contained in bits 31:0 of the parameter.\r
- @return R11 Two unsigned 32-bit integers denoting the loop\r
- strides of the outer (loop 1) and inner (loop 2)\r
- purge loops. stride1 (loop 1) is contained in bits\r
- 63:32 of the parameter, and stride2 (loop 2) is\r
- contained in bits 31:0 of the parameter.\r
-\r
-**/\r
-#define PAL_PTCE_INFO 6\r
-\r
-typedef struct {\r
- UINT64 NumberSets:8; ///< Unsigned 8-bit integer denoting the number\r
- ///< of hash sets for the specified level\r
- ///< (1=fully associative)\r
- UINT64 NumberWays:8; ///< Unsigned 8-bit integer denoting the\r
- ///< associativity of the specified level\r
- ///< (1=direct).\r
- UINT64 NumberEntries:16; ///< Unsigned 16-bit integer denoting the\r
- ///< number of entries in the specified TC.\r
- UINT64 PageSizeIsOptimized:1; ///< Flag denoting whether the\r
- ///< specified level is optimized for\r
- ///< the region's preferred page size\r
- ///< (1=optimized) tc_pages indicates\r
- ///< which page sizes are usable by\r
- ///< this translation cache.\r
- UINT64 TcIsUnified:1; ///< Flag denoting whether the specified TC is\r
- ///< unified (1=unified).\r
- UINT64 EntriesReduction:1; ///< Flag denoting whether installed\r
- ///< translation registers will reduce\r
- ///< the number of entries within the\r
- ///< specified TC.\r
-} PAL_TC_INFO;\r
-\r
-/**\r
- PAL Procedure - PAL_VM_INFO.\r
-\r
- Return detailed information about virtual memory features\r
- supported in the processor. It is required by Itanium processors. The PAL\r
- procedure supports the Static Registers calling convention. It\r
- could be called at physical mode and Virtual mode.\r
-\r
- @param Index Index of PAL_VM_INFO within the list\r
- of PAL procedures.\r
- @param TcLevel Unsigned 64-bit integer specifying the level\r
- in the TLB hierarchy for which information is\r
- required. This value must be between 0 and one\r
- less than the value returned in the\r
- vm_info_1.num_tc_levels return value from\r
- PAL_VM_SUMMARY.\r
- @param TcType Unsigned 64-bit integer with a value of 1 for\r
- instruction translation cache and 2 for data\r
- or unified translation cache. All other values\r
- are reserved.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 8-byte formatted value returning information\r
- about the specified TC. See PAL_TC_INFO above.\r
- @return R10 64-bit vector containing a bit for each page\r
- size supported in the specified TC, where bit\r
- position n indicates a page size of 2**n.\r
-\r
-**/\r
-#define PAL_VM_INFO 7\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_VM_PAGE_SIZE.\r
-\r
- Return virtual memory TC and hardware walker page sizes\r
- supported in the processor. It is required by Itanium processors. The PAL\r
- procedure supports the Static Registers calling convention. It\r
- could be called at physical mode and Virtual mode.\r
-\r
- @param Index Index of PAL_VM_PAGE_SIZE within the list\r
- of PAL procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 64-bit vector containing a bit for each\r
- architected page size that is supported for\r
- TLB insertions and region registers.\r
- @return R10 64-bit vector containing a bit for each\r
- architected page size supported for TLB purge\r
- operations.\r
-\r
-**/\r
-#define PAL_VM_PAGE_SIZE 34\r
-\r
-typedef struct {\r
- UINT64 WalkerPresent:1; ///< 1-bit flag indicating whether a hardware\r
- ///< TLB walker is implemented (1 = walker\r
- ///< present).\r
- UINT64 WidthOfPhysicalAddress: 7; ///< Unsigned 7-bit integer\r
- ///< denoting the number of bits of\r
- ///< physical address implemented.\r
- UINT64 WidthOfKey:8; ///< Unsigned 8-bit integer denoting the number\r
- ///< of bits mplemented in the PKR.key field.\r
- UINT64 MaxPkrIndex:8; ///< Unsigned 8-bit integer denoting the\r
- ///< maximum PKR index (number of PKRs-1).\r
- UINT64 HashTagId:8; ///< Unsigned 8-bit integer which uniquely\r
- ///< identifies the processor hash and tag\r
- ///< algorithm.\r
- UINT64 MaxDtrIndex:8; ///< Unsigned 8 bit integer denoting the\r
- ///< maximum data translation register index\r
- ///< (number of dtr entries - 1).\r
- UINT64 MaxItrIndex:8; ///< Unsigned 8 bit integer denoting the\r
- ///< maximum instruction translation register\r
- ///< index (number of itr entries - 1).\r
- UINT64 NumberOfUniqueTc:8; ///< Unsigned 8-bit integer denoting the\r
- ///< number of unique TCs implemented.\r
- ///< This is a maximum of\r
- ///< 2*num_tc_levels.\r
- UINT64 NumberOfTcLevels:8; ///< Unsigned 8-bit integer denoting the\r
- ///< number of TC levels.\r
-} PAL_VM_INFO1;\r
-\r
-typedef struct {\r
- UINT64 WidthOfVirtualAddress:8; ///< Unsigned 8-bit integer denoting\r
- ///< is the total number of virtual\r
- ///< address bits - 1.\r
- UINT64 WidthOfRid:8; ///< Unsigned 8-bit integer denoting the number\r
- ///< of bits implemented in the RR.rid field.\r
- UINT64 MaxPurgedTlbs:16; ///< Unsigned 16 bit integer denoting the\r
- ///< maximum number of concurrent outstanding\r
- ///< TLB purges allowed by the processor. A\r
- ///< value of 0 indicates one outstanding\r
- ///< purge allowed. A value of 216-1\r
- ///< indicates no limit on outstanding\r
- ///< purges. All other values indicate the\r
- ///< actual number of concurrent outstanding\r
- ///< purges allowed.\r
- UINT64 Reserved:32;\r
-} PAL_VM_INFO2;\r
-\r
-/**\r
- PAL Procedure - PAL_VM_SUMMARY.\r
-\r
- Return summary information about virtual memory features\r
- supported in the processor. It is required by Itanium processors. The PAL\r
- procedure supports the Static Registers calling convention. It\r
- could be called at physical mode and Virtual mode.\r
-\r
- @param Index Index of PAL_VM_SUMMARY within the list\r
- of PAL procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 8-byte formatted value returning global virtual\r
- memory information. See PAL_VM_INFO1 above.\r
- @return R10 8-byte formatted value returning global virtual\r
- memory information. See PAL_VM_INFO2 above.\r
-\r
-**/\r
-#define PAL_VM_SUMMARY 8\r
-\r
-\r
-//\r
-// Bit mask of TR_valid flag.\r
-//\r
-#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r
-#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r
-#define PAL_TR_DIRTY_IS_VALID BIT2\r
-#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_VM_TR_READ.\r
-\r
- Read contents of a translation register. It is required by\r
- Itanium processors. The PAL procedure supports the Stacked Register calling\r
- convention. It could be called at physical mode.\r
-\r
- @param Index Index of PAL_VM_TR_READ within the list\r
- of PAL procedures.\r
- @param RegNumber Unsigned 64-bit number denoting which TR to\r
- read.\r
- @param TrType Unsigned 64-bit number denoting whether to\r
- read an ITR (0) or DTR (1). All other values\r
- are reserved.\r
- @param TrBuffer 64-bit pointer to the 32-byte memory buffer in\r
- which translation data is returned.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Formatted bit vector denoting which fields are\r
- valid. See TR_valid above.\r
-\r
-**/\r
-#define PAL_VM_TR_READ 261\r
-\r
-\r
-\r
-\r
-//\r
-// Bit Mask of Processor Bus Fesatures .\r
-//\r
-\r
-/**\r
-\r
- When 0, bus data errors are detected and single bit errors are\r
- corrected. When 1, no error detection or correction is done.\r
-\r
-**/\r
-#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63\r
-\r
-\r
-/**\r
-\r
- When 0, bus address errors are signalled on the bus. When 1,\r
- no bus errors are signalled on the bus. If Disable Bus Address\r
- Error Checking is 1, this bit is ignored.\r
-\r
-**/\r
-#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62\r
-\r
-\r
-\r
-\r
-/**\r
-\r
- When 0, bus errors are detected, single bit errors are\r
- corrected., and a CMCI or MCA is generated internally to the\r
- processor. When 1, no bus address errors are detected or\r
- corrected.\r
-\r
-**/\r
-#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61\r
-\r
-\r
-/**\r
-\r
- When 0, bus protocol errors (BINIT#) are signaled by the\r
- processor on the bus. When 1, bus protocol errors (BINIT#) are\r
- not signaled on the bus. If Disable Bus Initialization Event\r
- Checking is 1, this bit is ignored.\r
-\r
-**/\r
-#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60\r
-\r
-\r
-/**\r
-\r
- When 0, bus protocol errors (BINIT#) are detected and sampled\r
- and an MCA is generated internally to the processor. When 1,\r
- the processor will ignore bus protocol error conditions\r
- (BINIT#).\r
-\r
-**/\r
-#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59\r
-\r
-\r
-\r
-/**\r
-\r
- When 0, BERR# is signalled if a bus error is detected. When 1,\r
- bus errors are not signalled on the bus.\r
-\r
-**/\r
-#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58\r
-\r
-\r
-\r
-\r
-/**\r
-\r
- When 0, BERR# is signalled when internal processor requestor\r
- initiated bus errors are detected. When 1, internal requester\r
- bus errors are not signalled on the bus.\r
-\r
-**/\r
-#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r
-\r
-\r
-/**\r
-\r
- When 0, the processor takes an MCA if BERR# is asserted. When\r
- 1, the processor ignores the BERR# signal.\r
-\r
-**/\r
-#define PAL_BUS_DISABLE_ERROR_CHECK BIT56\r
-\r
-\r
-/**\r
-\r
- When 0, the processor asserts BINIT# if it detects a parity\r
- error on the signals which identify the transactions to which\r
- this is a response. When 1, the processor ignores parity on\r
- these signals.\r
-\r
-**/\r
-#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r
-\r
-\r
-/**\r
-\r
- When 0, the in-order transaction queue is limited only by the\r
- number of hardware entries. When 1, the processor's in-order\r
- transactions queue is limited to one entry.\r
-\r
-**/\r
-#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r
-\r
-/**\r
-\r
- Enable a bus cache line replacement transaction when a cache\r
- line in the exclusive state is replaced from the highest level\r
- processor cache and is not present in the lower level processor\r
- caches. When 0, no bus cache line replacement transaction will\r
- be seen on the bus. When 1, bus cache line replacement\r
- transactions will be seen on the bus when the above condition is\r
- detected.\r
-\r
-**/\r
-#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53\r
-\r
-\r
-/**\r
-\r
- Enable a bus cache line replacement transaction when a cache\r
- line in the shared or exclusive state is replaced from the\r
- highest level processor cache and is not present in the lower\r
- level processor caches.\r
- When 0, no bus cache line replacement transaction will be seen\r
- on the bus. When 1, bus cache line replacement transactions\r
- will be seen on the bus when the above condition is detected.\r
-\r
-**/\r
-#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r
-\r
-\r
-\r
-/**\r
-\r
- When 0, the data bus is configured at the 2x data transfer\r
- rate.When 1, the data bus is configured at the 1x data\r
- transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r
- processor executes locked transactions atomically. When 1, the\r
- processor masks the bus lock signal and executes locked\r
- transactions as a non-atomic series of transactions.\r
-\r
-**/\r
-#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r
-\r
-/**\r
-\r
- When 0, the processor will deassert bus request when finished\r
- with each transaction. When 1, the processor will continue to\r
- assert bus request after it has finished, if it was the last\r
- agent to own the bus and if there are no other pending\r
- requests.\r
-\r
-**/\r
-#define PAL_BUS_REQUEST_BUS_PARKING BIT29\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_BUS_GET_FEATURES.\r
-\r
- Return configurable processor bus interface features and their\r
- current settings. It is required by Itanium processors. The PAL procedure\r
- supports the Stacked Register calling convention. It could be\r
- called at physical mode.\r
-\r
- @param Index Index of PAL_BUS_GET_FEATURES within the list\r
- of PAL procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 64-bit vector of features implemented.\r
- (1=implemented, 0=not implemented)\r
- @return R10 64-bit vector of current feature settings.\r
- @return R11 64-bit vector of features controllable by\r
- software. (1=controllable, 0= not controllable)\r
-\r
-**/\r
-#define PAL_BUS_GET_FEATURES 9\r
-\r
-/**\r
- PAL Procedure - PAL_BUS_SET_FEATURES.\r
-\r
- Enable or disable configurable features in processor bus\r
- interface. It is required by Itanium processors. The PAL procedure\r
- supports the Static Registers calling convention. It could be\r
- called at physical mode.\r
-\r
- @param Index Index of PAL_BUS_SET_FEATURES within the list\r
- of PAL procedures.\r
- @param FeatureSelect 64-bit vector denoting desired state of\r
- each feature (1=select, 0=non-select).\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_BUS_SET_FEATURES 10\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_DEBUG_INFO.\r
-\r
- Return the number of instruction and data breakpoint\r
- registers. It is required by Itanium processors. The\r
- PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical mode and virtual\r
- mode.\r
-\r
- @param Index Index of PAL_DEBUG_INFO within the list of PAL\r
- procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Unsigned 64-bit integer denoting the number of\r
- pairs of instruction debug registers implemented\r
- by the processor.\r
- @return R10 Unsigned 64-bit integer denoting the number of\r
- pairs of data debug registers implemented by the\r
- processor.\r
-\r
-**/\r
-#define PAL_DEBUG_INFO 11\r
-\r
-/**\r
- PAL Procedure - PAL_FIXED_ADDR.\r
-\r
- Return the fixed component of a processor's directed address.\r
- It is required by Itanium processors. The PAL\r
- procedure supports the Static Registers calling convention. It\r
- could be called at physical mode and virtual mode.\r
-\r
- @param Index Index of PAL_FIXED_ADDR within the list of PAL\r
- procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Fixed geographical address of this processor.\r
-\r
-**/\r
-#define PAL_FIXED_ADDR 12\r
-\r
-/**\r
- PAL Procedure - PAL_FREQ_BASE.\r
-\r
- Return the frequency of the output clock for use by the\r
- platform, if generated by the processor. It is optinal. The\r
- PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical mode and virtual\r
- mode.\r
-\r
- @param Index Index of PAL_FREQ_BASE within the list of PAL\r
- procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Base frequency of the platform if generated by the\r
- processor chip.\r
-\r
-**/\r
-#define PAL_FREQ_BASE 13\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_FREQ_RATIOS.\r
-\r
- Return ratio of processor, bus, and interval time counter to\r
- processor input clock or output clock for platform use, if\r
- generated by the processor. It is required by Itanium processors. The PAL\r
- procedure supports the Static Registers calling convention. It\r
- could be called at physical mode and virtual mode.\r
-\r
- @param Index Index of PAL_FREQ_RATIOS within the list of PAL\r
- procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Ratio of the processor frequency to the input\r
- clock of the processor, if the platform clock is\r
- generated externally or to the output clock to the\r
- platform, if the platform clock is generated by\r
- the processor.\r
- @return R10 Ratio of the bus frequency to the input clock of\r
- the processor, if the platform clock is generated\r
- externally or to the output clock to the platform,\r
- if the platform clock is generated by the\r
- processor.\r
- @return R11 Ratio of the interval timer counter rate to input\r
- clock of the processor, if the platform clock is\r
- generated externally or to the output clock to the\r
- platform, if the platform clock is generated by\r
- the processor.\r
-\r
-**/\r
-#define PAL_FREQ_RATIOS 14\r
-\r
-typedef struct {\r
- UINT64 NumberOfLogicalProcessors:16; ///< Total number of logical\r
- ///< processors on this physical\r
- ///< processor package that are\r
- ///< enabled.\r
- UINT64 ThreadsPerCore:8; ///< Number of threads per core.\r
- UINT64 Reserved1:8;\r
- UINT64 CoresPerProcessor:8; ///< Total number of cores on this\r
- ///< physical processor package.\r
- UINT64 Reserved2:8;\r
- UINT64 PhysicalProcessorPackageId:8; ///< Physical processor package\r
- ///< identifier which was\r
- ///< assigned at reset by the\r
- ///< platform or bus\r
- ///< controller. This value may\r
- ///< or may not be unique\r
- ///< across the entire platform\r
- ///< since it depends on the\r
- ///< platform vendor's policy.\r
- UINT64 Reserved3:8;\r
-} PAL_LOGICAL_PROCESSPR_OVERVIEW;\r
-\r
-typedef struct {\r
- UINT64 ThreadId:16; ///< The thread identifier of the logical\r
- ///< processor for which information is being\r
- ///< returned. This value will be unique on a per\r
- ///< core basis.\r
- UINT64 Reserved1:16;\r
- UINT64 CoreId:16; ///< The core identifier of the logical processor\r
- ///< for which information is being returned.\r
- ///< This value will be unique on a per physical\r
- ///< processor package basis.\r
- UINT64 Reserved2:16;\r
-} PAL_LOGICAL_PROCESSORN_INFO1;\r
-\r
-typedef struct {\r
- UINT64 LogicalAddress:16; ///< Geographical address of the logical\r
- ///< processor for which information is being\r
- ///< returned. This is the same value that is\r
- ///< returned by the PAL_FIXED_ADDR procedure\r
- ///< when it is called on the logical processor.\r
- UINT64 Reserved:48;\r
-} PAL_LOGICAL_PROCESSORN_INFO2;\r
-\r
-/**\r
- PAL Procedure - PAL_LOGICAL_TO_PHYSICAL.\r
-\r
- Return information on which logical processors map to a\r
- physical processor die. It is optinal. The PAL procedure\r
- supports the Static Registers calling convention. It could be\r
- called at physical mode and virtual mode.\r
-\r
- @param Index Index of PAL_LOGICAL_TO_PHYSICAL within the list of PAL\r
- procedures.\r
- @param ProcessorNumber Signed 64-bit integer that specifies\r
- for which logical processor\r
- information is being requested. When\r
- this input argument is -1, information\r
- is returned about the logical\r
- processor on which the procedure call\r
- is made. This input argument must be\r
- in the range of 1 up to one less than\r
- the number of logical processors\r
- returned by num_log in the\r
- log_overview return value.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 The format of PAL_LOGICAL_PROCESSPR_OVERVIEW.\r
- @return R10 The format of PAL_LOGICAL_PROCESSORN_INFO1.\r
- @return R11 The format of PAL_LOGICAL_PROCESSORN_INFO2.\r
-\r
-**/\r
-#define PAL_LOGICAL_TO_PHYSICAL 42\r
-\r
-typedef struct {\r
- UINT64 NumberOfPmcPairs:8; ///< Unsigned 8-bit number defining the\r
- ///< number of generic PMC/PMD pairs.\r
- UINT64 WidthOfCounter:8; ///< Unsigned 8-bit number in the range\r
- ///< 0:60 defining the number of\r
- ///< implemented counter bits.\r
- UINT64 TypeOfCycleCounting:8; ///< Unsigned 8-bit number defining the\r
- ///< event type for counting processor cycles.\r
- UINT64 TypeOfRetiredInstructionBundle:8; ///< Retired Unsigned 8-bit\r
- ///< number defining the\r
- ///< event type for retired\r
- ///< instruction bundles.\r
- UINT64 Reserved:32;\r
-} PAL_PERFORMANCE_INFO;\r
-\r
-/**\r
- PAL Procedure - PAL_PERF_MON_INFO.\r
-\r
- Return the number and type of performance monitors. It is\r
- required by Itanium processors. The PAL procedure supports the Static\r
- Registers calling convention. It could be called at physical\r
- mode and virtual mode.\r
-\r
- @param Index Index of PAL_PERF_MON_INFO within the list of\r
- PAL procedures.\r
- @param PerformanceBuffer An address to an 8-byte aligned\r
- 128-byte memory buffer.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Information about the performance monitors\r
- implemented. See PAL_PERFORMANCE_INFO;\r
-\r
-**/\r
-#define PAL_PERF_MON_INFO 15\r
-\r
-#define PAL_PLATFORM_ADDR_INTERRUPT_BLOCK_TOKEN 0x0\r
-#define PAL_PLATFORM_ADDR_IO_BLOCK_TOKEN 0x1\r
-\r
-/**\r
- PAL Procedure - PAL_PLATFORM_ADDR.\r
-\r
- Specify processor interrupt block address and I/O port space\r
- address. It is required by Itanium processors. The PAL procedure supports the\r
- Static Registers calling convention. It could be called at\r
- physical mode and virtual mode.\r
-\r
- @param Index Index of PAL_PLATFORM_ADDR within the list of\r
- PAL procedures.\r
- @param Type Unsigned 64-bit integer specifying the type of\r
- block. 0 indicates that the processor interrupt\r
- block pointer should be initialized. 1 indicates\r
- that the processor I/O block pointer should be\r
- initialized.\r
- @param Address Unsigned 64-bit integer specifying the address\r
- to which the processor I/O block or interrupt\r
- block shall be set. The address must specify\r
- an implemented physical address on the\r
- processor model, bit 63 is ignored.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure.\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_PLATFORM_ADDR 16\r
-\r
-typedef struct {\r
- UINT64 Reserved1:36;\r
- UINT64 FaultInUndefinedIns:1; ///< Bit36, No Unimplemented\r
- ///< instruction address reported as\r
- ///< fault. Denotes how the processor\r
- ///< reports the detection of\r
- ///< unimplemented instruction\r
- ///< addresses. When 1, the processor\r
- ///< reports an Unimplemented\r
- ///< Instruction Address fault on the\r
- ///< unimplemented address; when 0, it\r
- ///< reports an Unimplemented\r
- ///< Instruction Address trap on the\r
- ///< previous instruction in program\r
- ///< order. This feature may only be\r
- ///< interrogated by\r
- ///< PAL_PROC_GET_FEATURES. It may not\r
- ///< be enabled or disabled by\r
- ///< PAL_PROC_SET_FEATURES. The\r
- ///< corresponding argument is ignored.\r
-\r
- UINT64 NoPresentPmi:1; ///< Bit37, No INIT, PMI, and LINT pins\r
- ///< present. Denotes the absence of INIT,\r
- ///< PMI, LINT0 and LINT1 pins on the\r
- ///< processor. When 1, the pins are absent.\r
- ///< When 0, the pins are present. This\r
- ///< feature may only be interrogated by\r
- ///< PAL_PROC_GET_FEATURES. It may not be\r
- ///< enabled or disabled by\r
- ///< PAL_PROC_SET_FEATURES. The corresponding\r
- ///< argument is ignored.\r
-\r
- UINT64 NoSimpleImpInUndefinedIns:1; ///< Bit38, No Simple\r
- ///< implementation of\r
- ///< unimplemented instruction\r
- ///< addresses. Denotes how an\r
- ///< unimplemented instruction\r
- ///< address is recorded in IIP\r
- ///< on an Unimplemented\r
- ///< Instruction Address trap or\r
- ///< fault. When 1, the full\r
- ///< unimplemented address is\r
- ///< recorded in IIP; when 0, the\r
- ///< address is sign extended\r
- ///< (virtual addresses) or zero\r
- ///< extended (physical\r
- ///< addresses). This feature may\r
- ///< only be interrogated by\r
- ///< PAL_PROC_GET_FEATURES. It\r
- ///< may not be enabled or\r
- ///< disabled by\r
- ///< PAL_PROC_SET_FEATURES. The\r
- ///< corresponding argument is\r
- ///< ignored.\r
-\r
- UINT64 NoVariablePState:1; ///< Bit39, No Variable P-state\r
- ///< performance: A value of 1, indicates\r
- ///< that a processor implements\r
- ///< techniques to optimize performance\r
- ///< for the given P-state power budget\r
- ///< by dynamically varying the\r
- ///< frequency, such that maximum\r
- ///< performance is achieved for the\r
- ///< power budget. A value of 0,\r
- ///< indicates that P-states have no\r
- ///< frequency variation or very small\r
- ///< frequency variations for their given\r
- ///< power budget. This feature may only\r
- ///< be interrogated by\r
- ///< PAL_PROC_GET_FEATURES. it may not be\r
- ///< enabled or disabled by\r
- ///< PAL_PROC_SET_FEATURES. The\r
- ///< corresponding argument is ignored.\r
-\r
- UINT64 NoVM:1; ///< Bit40, No Virtual Machine features implemented.\r
- ///< Denotes whether PSR.vm is implemented. This\r
- ///< feature may only be interrogated by\r
- ///< PAL_PROC_GET_FEATURES. It may not be enabled or\r
- ///< disabled by PAL_PROC_SET_FEATURES. The\r
- ///< corresponding argument is ignored.\r
-\r
- UINT64 NoXipXpsrXfs:1; ///< Bit41, No XIP, XPSR, and XFS\r
- ///< implemented. Denotes whether XIP, XPSR,\r
- ///< and XFS are implemented for machine\r
- ///< check recovery. This feature may only be\r
- ///< interrogated by PAL_PROC_GET_FEATURES.\r
- ///< It may not be enabled or disabled by\r
- ///< PAL_PROC_SET_FEATURES. The corresponding\r
- ///< argument is ignored.\r
-\r
- UINT64 NoXr1ThroughXr3:1; ///< Bit42, No XR1 through XR3 implemented.\r
- ///< Denotes whether XR1 XR3 are\r
- ///< implemented for machine check\r
- ///< recovery. This feature may only be\r
- ///< interrogated by PAL_PROC_GET_FEATURES.\r
- ///< It may not be enabled or disabled by\r
- ///< PAL_PROC_SET_FEATURES. The\r
- ///< corresponding argument is ignored.\r
-\r
- UINT64 DisableDynamicPrediction:1; ///< Bit43, Disable Dynamic\r
- ///< Predicate Prediction. When\r
- ///< 0, the processor may predict\r
- ///< predicate results and\r
- ///< execute speculatively, but\r
- ///< may not commit results until\r
- ///< the actual predicates are\r
- ///< known. When 1, the processor\r
- ///< shall not execute predicated\r
- ///< instructions until the\r
- ///< actual predicates are known.\r
-\r
- UINT64 DisableSpontaneousDeferral:1; ///< Bit44, Disable Spontaneous\r
- ///< Deferral. When 1, the\r
- ///< processor may optionally\r
- ///< defer speculative loads\r
- ///< that do not encounter any\r
- ///< exception conditions, but\r
- ///< that trigger other\r
- ///< implementation-dependent\r
- ///< conditions (e.g., cache\r
- ///< miss). When 0, spontaneous\r
- ///< deferral is disabled.\r
-\r
- UINT64 DisableDynamicDataCachePrefetch:1; ///< Bit45, Disable Dynamic\r
- ///< Data Cache Prefetch.\r
- ///< When 0, the processor\r
- ///< may prefetch into the\r
- ///< caches any data which\r
- ///< has not been accessed\r
- ///< by instruction\r
- ///< execution, but which\r
- ///< is likely to be\r
- ///< accessed. When 1, no\r
- ///< data may be fetched\r
- ///< until it is needed for\r
- ///< instruction execution\r
- ///< or is fetched by an\r
- ///< lfetch instruction.\r
-\r
- UINT64 DisableDynamicInsCachePrefetch:1; ///< Bit46, Disable\r
- ///< DynamicInstruction Cache\r
- ///< Prefetch. When 0, the\r
- ///< processor may prefetch\r
- ///< into the caches any\r
- ///< instruction which has\r
- ///< not been executed, but\r
- ///< whose execution is\r
- ///< likely. When 1,\r
- ///< instructions may not be\r
- ///< fetched until needed or\r
- ///< hinted for execution.\r
- ///< (Prefetch for a hinted\r
- ///< branch is allowed even\r
- ///< when dynamic instruction\r
- ///< cache prefetch is\r
- ///< disabled.)\r
-\r
- UINT64 DisableBranchPrediction:1; ///< Bit47, Disable Dynamic branch\r
- ///< prediction. When 0, the\r
- ///< processor may predict branch\r
- ///< targets and speculatively\r
- ///< execute, but may not commit\r
- ///< results. When 1, the processor\r
- ///< must wait until branch targets\r
- ///< are known to execute.\r
- UINT64 Reserved2:4;\r
- UINT64 DisablePState:1; ///< Bit52, Disable P-states. When 1, the PAL\r
- ///< P-state procedures (PAL_PSTATE_INFO,\r
- ///< PAL_SET_PSTATE, PAL_GET_PSTATE) will\r
- ///< return with a status of -1\r
- ///< (Unimplemented procedure).\r
-\r
- UINT64 EnableMcaOnDataPoisoning:1; ///< Bit53, Enable MCA signaling\r
- ///< on data-poisoning event\r
- ///< detection. When 0, a CMCI\r
- ///< will be signaled on error\r
- ///< detection. When 1, an MCA\r
- ///< will be signaled on error\r
- ///< detection. If this feature\r
- ///< is not supported, then the\r
- ///< corresponding argument is\r
- ///< ignored when calling\r
- ///< PAL_PROC_SET_FEATURES. Note\r
- ///< that the functionality of\r
- ///< this bit is independent of\r
- ///< the setting in bit 60\r
- ///< (Enable CMCI promotion), and\r
- ///< that the bit 60 setting does\r
- ///< not affect CMCI signaling\r
- ///< for data-poisoning related\r
- ///< events. Volume 2: Processor\r
- ///< Abstraction Layer 2:431\r
- ///< PAL_PROC_GET_FEATURES\r
-\r
- UINT64 EnableVmsw:1; ///< Bit54, Enable the use of the vmsw\r
- ///< instruction. When 0, the vmsw instruction\r
- ///< causes a Virtualization fault when\r
- ///< executed at the most privileged level.\r
- ///< When 1, this bit will enable normal\r
- ///< operation of the vmsw instruction.\r
-\r
- UINT64 EnableEnvNotification:1; ///< Bit55, Enable external\r
- ///< notification when the processor\r
- ///< detects hardware errors caused\r
- ///< by environmental factors that\r
- ///< could cause loss of\r
- ///< deterministic behavior of the\r
- ///< processor. When 1, this bit will\r
- ///< enable external notification,\r
- ///< when 0 external notification is\r
- ///< not provided. The type of\r
- ///< external notification of these\r
- ///< errors is processor-dependent. A\r
- ///< loss of processor deterministic\r
- ///< behavior is considered to have\r
- ///< occurred if these\r
- ///< environmentally induced errors\r
- ///< cause the processor to deviate\r
- ///< from its normal execution and\r
- ///< eventually causes different\r
- ///< behavior which can be observed\r
- ///< at the processor bus pins.\r
- ///< Processor errors that do not\r
- ///< have this effects (i.e.,\r
- ///< software induced machine checks)\r
- ///< may or may not be promoted\r
- ///< depending on the processor\r
- ///< implementation.\r
-\r
- UINT64 DisableBinitWithTimeout:1; ///< Bit56, Disable a BINIT on\r
- ///< internal processor time-out.\r
- ///< When 0, the processor may\r
- ///< generate a BINIT on an\r
- ///< internal processor time-out.\r
- ///< When 1, the processor will not\r
- ///< generate a BINIT on an\r
- ///< internal processor time-out.\r
- ///< The event is silently ignored.\r
-\r
- UINT64 DisableDPM:1; ///< Bit57, Disable Dynamic Power Management\r
- ///< (DPM). When 0, the hardware may reduce\r
- ///< power consumption by removing the clock\r
- ///< input from idle functional units. When 1,\r
- ///< all functional units will receive clock\r
- ///< input, even when idle.\r
-\r
- UINT64 DisableCoherency:1; ///< Bit58, Disable Coherency. When 0,\r
- ///< the processor uses normal coherency\r
- ///< requests and responses. When 1, the\r
- ///< processor answers all requests as if\r
- ///< the line were not present.\r
-\r
- UINT64 DisableCache:1; ///< Bit59, Disable Cache. When 0, the\r
- ///< processor performs cast outs on\r
- ///< cacheable pages and issues and responds\r
- ///< to coherency requests normally. When 1,\r
- ///< the processor performs a memory access\r
- ///< for each reference regardless of cache\r
- ///< contents and issues no coherence\r
- ///< requests and responds as if the line\r
- ///< were not present. Cache contents cannot\r
- ///< be relied upon when the cache is\r
- ///< disabled. WARNING: Semaphore\r
- ///< instructions may not be atomic or may\r
- ///< cause Unsupported Data Reference faults\r
- ///< if caches are disabled.\r
-\r
- UINT64 EnableCmciPromotion:1; ///< Bit60, Enable CMCI promotion When\r
- ///< 1, Corrected Machine Check\r
- ///< Interrupts (CMCI) are promoted to\r
- ///< MCAs. They are also further\r
- ///< promoted to BERR if bit 39, Enable\r
- ///< MCA promotion, is also set and\r
- ///< they are promoted to BINIT if bit\r
- ///< 38, Enable MCA to BINIT promotion,\r
- ///< is also set. This bit has no\r
- ///< effect if MCA signalling is\r
- ///< disabled (see\r
- ///< PAL_BUS_GET/SET_FEATURES)\r
-\r
- UINT64 EnableMcaToBinitPromotion:1; ///< Bit61, Enable MCA to BINIT\r
- ///< promotion. When 1, machine\r
- ///< check aborts (MCAs) are\r
- ///< promoted to the Bus\r
- ///< Initialization signal, and\r
- ///< the BINIT pin is assert on\r
- ///< each occurrence of an MCA.\r
- ///< Setting this bit has no\r
- ///< effect if BINIT signalling\r
- ///< is disabled. (See\r
- ///< PAL_BUS_GET/SET_FEATURES)\r
-\r
- UINT64 EnableMcaPromotion:1; ///< Bit62, Enable MCA promotion. When\r
- ///< 1, machine check aborts (MCAs) are\r
- ///< promoted to the Bus Error signal,\r
- ///< and the BERR pin is assert on each\r
- ///< occurrence of an MCA. Setting this\r
- ///< bit has no effect if BERR\r
- ///< signalling is disabled. (See\r
- ///< PAL_BUS_GET/SET_FEATURES)\r
-\r
- UINT64 EnableBerrPromotion:1; ///< Bit63. Enable BERR promotion. When\r
- ///< 1, the Bus Error (BERR) signal is\r
- ///< promoted to the Bus Initialization\r
- ///< (BINIT) signal, and the BINIT pin\r
- ///< is asserted on the occurrence of\r
- ///< each Bus Error. Setting this bit\r
- ///< has no effect if BINIT signalling\r
- ///< is disabled. (See\r
- ///< PAL_BUS_GET/SET_FEATURES)\r
-} PAL_PROCESSOR_FEATURES;\r
-\r
-/**\r
- PAL Procedure - PAL_PROC_GET_FEATURES.\r
-\r
- Return configurable processor features and their current\r
- setting. It is required by Itanium processors. The PAL procedure supports the\r
- Static Registers calling convention. It could be called at\r
- physical mode and virtual mode.\r
-\r
- @param Index Index of PAL_PROC_GET_FEATURES within the list of\r
- PAL procedures.\r
- @param Reserved Reserved parameter.\r
- @param FeatureSet Feature set information is being requested\r
- for.\r
-\r
- @retval 1 Call completed without error; The\r
- feature_set passed is not supported but a\r
- feature_set of a larger value is supported.\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -8 feature_set passed is beyond the maximum\r
- feature_set supported\r
-\r
- @return R9 64-bit vector of features implemented. See\r
- PAL_PROCESSOR_FEATURES.\r
- @return R10 64-bit vector of current feature settings. See\r
- PAL_PROCESSOR_FEATURES.\r
- @return R11 64-bit vector of features controllable by\r
- software.\r
-\r
-**/\r
-#define PAL_PROC_GET_FEATURES 17\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_PROC_SET_FEATURES.\r
-\r
- Enable or disable configurable processor features. It is\r
- required by Itanium processors. The PAL procedure supports the Static\r
- Registers calling convention. It could be called at physical\r
- mode.\r
-\r
- @param Index Index of PAL_PROC_SET_FEATURES within the list of\r
- PAL procedures.\r
- @param FeatureSelect 64-bit vector denoting desired state of\r
- each feature (1=select, 0=non-select).\r
- @param FeatureSet Feature set to apply changes to. See\r
- PAL_PROC_GET_FEATURES for more information\r
- on feature sets.\r
-\r
- @retval 1 Call completed without error; The\r
- feature_set passed is not supported but a\r
- feature_set of a larger value is supported\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -8 feature_set passed is beyond the maximum\r
- feature_set supported\r
-\r
-**/\r
-#define PAL_PROC_SET_FEATURES 18\r
-\r
-\r
-//\r
-// Value of PAL_REGISTER_INFO.InfoRequest.\r
-//\r
-#define PAL_APPLICATION_REGISTER_IMPLEMENTED 0\r
-#define PAL_APPLICATION_REGISTER_READABLE 1\r
-#define PAL_CONTROL_REGISTER_IMPLEMENTED 2\r
-#define PAL_CONTROL_REGISTER_READABLE 3\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_REGISTER_INFO.\r
-\r
- Return AR and CR register information. It is required by Itanium processors.\r
- The PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical mode and virtual\r
- mode.\r
-\r
- @param Index Index of PAL_REGISTER_INFO within the list of\r
- PAL procedures.\r
- @param InfoRequest Unsigned 64-bit integer denoting what\r
- register information is requested. See\r
- PAL_REGISTER_INFO.InfoRequest above.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 64-bit vector denoting information for registers\r
- 0-63. Bit 0 is register 0, bit 63 is register 63.\r
- @return R10 64-bit vector denoting information for registers\r
- 64-127. Bit 0 is register 64, bit 63 is register\r
- 127.\r
-\r
-**/\r
-#define PAL_REGISTER_INFO 39\r
-\r
-/**\r
- PAL Procedure - PAL_RSE_INFO.\r
-\r
- Return RSE information. It is required by Itanium processors. The PAL\r
- procedure supports the Static Registers calling convention. It\r
- could be called at physical mode and virtual mode.\r
-\r
- @param Index Index of PAL_RSE_INFO within the list of\r
- PAL procedures.\r
- @param InfoRequest Unsigned 64-bit integer denoting what\r
- register information is requested. See\r
- PAL_REGISTER_INFO.InfoRequest above.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Number of physical stacked general registers.\r
- @return R10 RSE hints supported by processor.\r
-\r
-**/\r
-#define PAL_RSE_INFO 19\r
-\r
-typedef struct {\r
- UINT64 VersionOfPalB:16; ///< Is a 16-bit binary coded decimal (BCD)\r
- ///< number that provides identification\r
- ///< information about the PAL_B firmware.\r
- UINT64 Reserved1:8;\r
- UINT64 PalVendor:8; ///< Is an unsigned 8-bit integer indicating the\r
- ///< vendor of the PAL code.\r
- UINT64 VersionOfPalA:16; ///< Is a 16-bit binary coded decimal (BCD)\r
- ///< number that provides identification\r
- ///< information about the PAL_A firmware. In\r
- ///< the split PAL_A model, this return value\r
- ///< is the version number of the\r
- ///< processor-specific PAL_A. The generic\r
- ///< PAL_A version is not returned by this\r
- ///< procedure in the split PAL_A model.\r
- UINT64 Reserved2:16;\r
-} PAL_VERSION_INFO;\r
-\r
-/**\r
- PAL Procedure - PAL_VERSION.\r
-\r
- Return version of PAL code. It is required by Itanium processors. The PAL\r
- procedure supports the Static Registers calling convention. It\r
- could be called at physical mode and virtual mode.\r
-\r
- @param Index Index of PAL_VERSION within the list of\r
- PAL procedures.\r
- @param InfoRequest Unsigned 64-bit integer denoting what\r
- register information is requested. See\r
- PAL_REGISTER_INFO.InfoRequest above.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 8-byte formatted value returning the minimum PAL\r
- version needed for proper operation of the\r
- processor. See PAL_VERSION_INFO above.\r
- @return R10 8-byte formatted value returning the current PAL\r
- version running on the processor. See\r
- PAL_VERSION_INFO above.\r
-\r
-**/\r
-#define PAL_VERSION 20\r
-\r
-\r
-\r
-//\r
-// Vectors of PAL_MC_CLEAR_LOG.pending\r
-//\r
-#define PAL_MC_PENDING BIT0\r
-#define PAL_INIT_PENDING BIT1\r
-\r
-/**\r
- PAL Procedure - PAL_MC_CLEAR_LOG.\r
-\r
- Clear all error information from processor error logging\r
- registers. It is required by Itanium processors. The PAL procedure supports\r
- the Static Registers calling convention. It could be called at\r
- physical mode and virtual mode.\r
-\r
- @param Index Index of PAL_MC_CLEAR_LOG within the list of\r
- PAL procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 64-bit vector denoting whether an event is\r
- pending. See PAL_MC_CLEAR_LOG.pending above.\r
-\r
-**/\r
-#define PAL_MC_CLEAR_LOG 21\r
-\r
-/**\r
- PAL Procedure - PAL_MC_DRAIN.\r
-\r
- Ensure that all operations that could cause an MCA have\r
- completed. It is required by Itanium processors. The PAL procedure supports\r
- the Static Registers calling convention. It could be called at\r
- physical mode and virtual mode.\r
-\r
- @param Index Index of PAL_MC_DRAIN within the list of PAL\r
- procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_MC_DRAIN 22\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_MC_DYNAMIC_STATE.\r
-\r
- Return Processor Dynamic State for logging by SAL. It is\r
- optional. The PAL procedure supports the Static Registers\r
- calling convention. It could be called at physical mode.\r
-\r
- @param Index Index of PAL_MC_DYNAMIC_STATE within the list of PAL\r
- procedures.\r
- @param Offset Offset of the next 8 bytes of Dynamic Processor\r
- State to return. (multiple of 8).\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure.\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Unsigned 64-bit integer denoting bytes of Dynamic\r
- Processor State returned.\r
- @return R10 Next 8 bytes of Dynamic Processor State.\r
-\r
-**/\r
-#define PAL_MC_DYNAMIC_STATE 24\r
-\r
-\r
-\r
-//\r
-// Values of PAL_MC_ERROR_INFO.InfoIndex.\r
-//\r
-#define PAL_PROCESSOR_ERROR_MAP 0\r
-#define PAL_PROCESSOR_STATE_PARAM 1\r
-#define PAL_STRUCTURE_SPECIFIC_ERROR 2\r
-\r
-typedef struct {\r
- UINT64 CoreId:4; ///< Bit3:0, Processor core ID (default is 0 for\r
- ///< processors with a single core)\r
-\r
- UINT64 ThreadId:4; ///< Bit7:4, Logical thread ID (default is 0 for\r
- ///< processors that execute a single thread)\r
-\r
- UINT64 InfoOfInsCache:4; ///< Bit11:8, Error information is\r
- ///< available for 1st, 2nd, 3rd, and 4th\r
- ///< level instruction caches.\r
-\r
- UINT64 InfoOfDataCache:4; ///< Bit15:12, Error information is\r
- ///< available for 1st, 2nd, 3rd, and 4th\r
- ///< level data/unified caches.\r
-\r
- UINT64 InfoOfInsTlb:4; ///< Bit19:16 Error information is available\r
- ///< for 1st, 2nd, 3rd, and 4th level\r
- ///< instruction TLB.\r
-\r
- UINT64 InfoOfDataTlb:4; ///< Bit23:20, Error information is available\r
- ///< for 1st, 2nd, 3rd, and 4th level\r
- ///< data/unified TLB\r
-\r
- UINT64 InfoOfProcessorBus:4; ///< Bit27:24 Error information is\r
- ///< available for the 1st, 2nd, 3rd,\r
- ///< and 4th level processor bus\r
- ///< hierarchy.\r
- UINT64 InfoOfRegisterFile:4; ///< Bit31:28 Error information is\r
- ///< available on register file\r
- ///< structures.\r
- UINT64 InfoOfMicroArch:4; ///< Bit47:32, Error information is\r
- ///< available on micro-architectural\r
- ///< structures.\r
- UINT64 Reserved:16;\r
-} PAL_MC_ERROR_INFO_LEVEL_INDEX;\r
-\r
-//\r
-// Value of PAL_MC_ERROR_INFO.ErrorTypeIndex\r
-//\r
-#define PAL_ERR_INFO_BY_LEVEL_INDEX 0\r
-#define PAL_ERR_INFO_TARGET_ADDRESS 1\r
-#define PAL_ERR_INFO_REQUESTER_IDENTIFIER 2\r
-#define PAL_ERR_INFO_REPONSER_INDENTIFIER 3\r
-#define PAL_ERR_INFO_PRECISE_INSTRUCTION_POINTER 4\r
-\r
-typedef struct {\r
- UINT64 Operation:4; ///< Bit3:0, Type of cache operation that caused\r
- ///< the machine check: 0 - unknown or internal\r
- ///< error 1 - load 2 - store 3 - instruction\r
- ///< fetch or instruction prefetch 4 - data\r
- ///< prefetch (both hardware and software) 5 -\r
- ///< snoop (coherency check) 6 - cast out\r
- ///< (explicit or implicit write-back of a cache\r
- ///< line) 7 - move in (cache line fill)\r
-\r
- UINT64 FailedCacheLevel:2; ///< Bit5:4 Level of cache where the\r
- ///< error occurred. A value of 0\r
- ///< indicates the first level of cache.\r
- UINT64 Reserved1:2;\r
- UINT64 FailedInDataPart:1; ///< Bit8, Failure located in the data part of the cache line.\r
- UINT64 FailedInTagPart:1; ///< Bit9, Failure located in the tag part of the cache line.\r
- UINT64 FailedInDataCache:1; ///< Bit10, Failure located in the data cache\r
-\r
- UINT64 FailedInInsCache:1; ///< Bit11, Failure located in the\r
- ///< instruction cache.\r
-\r
- UINT64 Mesi:3; ///< Bit14:12, 0 - cache line is invalid. 1 - cache\r
- ///< line is held shared. 2 - cache line is held\r
- ///< exclusive. 3 - cache line is modified. All other\r
- ///< values are reserved.\r
-\r
- UINT64 MesiIsValid:1; ///< Bit15, The mesi field in the cache_check\r
- ///< parameter is valid.\r
-\r
- UINT64 FailedWay:5; ///< Bit20:16, Failure located in the way of\r
- ///< the cache indicated by this value.\r
-\r
- UINT64 WayIndexIsValid:1; ///< Bit21, The way and index field in the\r
- ///< cache_check parameter is valid.\r
-\r
- UINT64 Reserved2:1;\r
- UINT64 MultipleBitsError:1; ///< Bit23, A multiple-bit error was\r
- ///< detected, and data was poisoned for\r
- ///< the corresponding cache line during\r
- ///< castout.\r
- UINT64 Reserved3:8;\r
- UINT64 IndexOfCacheLineError:20; ///< Bit51:32, Index of the cache\r
- ///< line where the error occurred.\r
- UINT64 Reserved4:2;\r
-\r
- UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value\r
- ///< is set to zero, the instruction that\r
- ///< generated the machine check was an\r
- ///< Intel Itanium instruction. If this bit\r
- ///< is set to one, the instruction that\r
- ///< generated the machine check was IA-32\r
- ///< instruction.\r
-\r
- UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the\r
- ///< cache_check parameter is valid.\r
-\r
- UINT64 PrivilegeLevel:2; ///< Bit57:56, Privilege level. The\r
- ///< privilege level of the instruction\r
- ///< bundle responsible for generating the\r
- ///< machine check.\r
-\r
- UINT64 PrivilegeLevelIsValide:1; ///< Bit58, The pl field of the\r
- ///< cache_check parameter is\r
- ///< valid.\r
-\r
- UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit\r
- ///< is set to one to indicate that the machine\r
- ///< check has been corrected.\r
-\r
- UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:\r
- ///< This bit is set to one to\r
- ///< indicate that a valid target\r
- ///< address has been logged.\r
-\r
- UINT64 RequesterIdentifier:1; ///< Bit61, Requester identifier: This\r
- ///< bit is set to one to indicate that\r
- ///< a valid requester identifier has\r
- ///< been logged.\r
-\r
- UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This\r
- ///< bit is set to one to indicate that\r
- ///< a valid responder identifier has\r
- ///< been logged.\r
-\r
- UINT64 PreciseInsPointer:1; ///< Bit63, Precise instruction pointer.\r
- ///< This bit is set to one to indicate\r
- ///< that a valid precise instruction\r
- ///< pointer has been logged.\r
-\r
-} PAL_CACHE_CHECK_INFO;\r
-\r
-\r
-typedef struct {\r
- UINT64 FailedSlot:8; ///< Bit7:0, Slot number of the translation\r
- ///< register where the failure occurred.\r
- UINT64 FailedSlotIsValid:1; ///< Bit8, The tr_slot field in the\r
- ///< TLB_check parameter is valid.\r
- UINT64 Reserved1 :1;\r
- UINT64 TlbLevel:2; ///< Bit11:10, The level of the TLB where the\r
- ///< error occurred. A value of 0 indicates the\r
- ///< first level of TLB\r
- UINT64 Reserved2 :4;\r
-\r
- UINT64 FailedInDataTr:1; ///< Bit16, Error occurred in the data\r
- ///< translation registers.\r
-\r
- UINT64 FailedInInsTr:1; ///< Bit17, Error occurred in the instruction\r
- ///< translation registers\r
-\r
- UINT64 FailedInDataTc:1; ///< Bit18, Error occurred in data\r
- ///< translation cache.\r
-\r
- UINT64 FailedInInsTc:1; ///< Bit19, Error occurred in the instruction\r
- ///< translation cache.\r
-\r
- UINT64 FailedOperation:4; ///< Bit23:20, Type of cache operation that\r
- ///< caused the machine check: 0 - unknown\r
- ///< 1 - TLB access due to load instruction\r
- ///< 2 - TLB access due to store\r
- ///< instruction 3 - TLB access due to\r
- ///< instruction fetch or instruction\r
- ///< prefetch 4 - TLB access due to data\r
- ///< prefetch (both hardware and software)\r
- ///< 5 - TLB shoot down access 6 - TLB\r
- ///< probe instruction (probe, tpa) 7 -\r
- ///< move in (VHPT fill) 8 - purge (insert\r
- ///< operation that purges entries or a TLB\r
- ///< purge instruction) All other values\r
- ///< are reserved.\r
-\r
- UINT64 Reserved3:30;\r
- UINT64 InstructionSet:1; ///< Bit54, Instruction set. If this value\r
- ///< is set to zero, the instruction that\r
- ///< generated the machine check was an\r
- ///< Intel Itanium instruction. If this bit\r
- ///< is set to one, the instruction that\r
- ///< generated the machine check was IA-32\r
- ///< instruction.\r
-\r
- UINT64 InstructionSetIsValid:1; ///< Bit55, The is field in the\r
- ///< TLB_check parameter is valid.\r
-\r
- UINT64 PrivelegeLevel:2; ///< Bit57:56, Privilege level. The\r
- ///< privilege level of the instruction\r
- ///< bundle responsible for generating the\r
- ///< machine check.\r
-\r
- UINT64 PrivelegeLevelIsValid:1; ///< Bit58, The pl field of the\r
- ///< TLB_check parameter is valid.\r
-\r
- UINT64 McCorrected:1; ///< Bit59, Machine check corrected: This bit\r
- ///< is set to one to indicate that the machine\r
- ///< check has been corrected.\r
-\r
- UINT64 TargetAddressIsValid:1; ///< Bit60, Target address is valid:\r
- ///< This bit is set to one to\r
- ///< indicate that a valid target\r
- ///< address has been logged.\r
-\r
- UINT64 RequesterIdentifier:1; ///< Bit61 Requester identifier: This\r
- ///< bit is set to one to indicate that\r
- ///< a valid requester identifier has\r
- ///< been logged.\r
-\r
- UINT64 ResponserIdentifier:1; ///< Bit62, Responder identifier: This\r
- ///< bit is set to one to indicate that\r
- ///< a valid responder identifier has\r
- ///< been logged.\r
-\r
- UINT64 PreciseInsPointer:1; ///< Bit63 Precise instruction pointer.\r
- ///< This bit is set to one to indicate\r
- ///< that a valid precise instruction\r
- ///< pointer has been logged.\r
-} PAL_TLB_CHECK_INFO;\r
-\r
-/**\r
- PAL Procedure - PAL_MC_ERROR_INFO.\r
-\r
- Return Processor Machine Check Information and Processor\r
- Static State for logging by SAL. It is required by Itanium processors. The\r
- PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical and virtual mode.\r
-\r
- @param Index Index of PAL_MC_ERROR_INFO within the list of PAL\r
- procedures.\r
- @param InfoIndex Unsigned 64-bit integer identifying the\r
- error information that is being requested.\r
- See PAL_MC_ERROR_INFO.InfoIndex.\r
- @param LevelIndex 8-byte formatted value identifying the\r
- structure to return error information\r
- on. See PAL_MC_ERROR_INFO_LEVEL_INDEX.\r
- @param ErrorTypeIndex Unsigned 64-bit integer denoting the\r
- type of error information that is\r
- being requested for the structure\r
- identified in LevelIndex.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -6 Argument was valid, but no error\r
- information was available\r
-\r
- @return R9 Error information returned. The format of this\r
- value is dependant on the input values passed.\r
- @return R10 If this value is zero, all the error information\r
- specified by err_type_index has been returned. If\r
- this value is one, more structure-specific error\r
- information is available and the caller needs to\r
- make this procedure call again with level_index\r
- unchanged and err_type_index, incremented.\r
-\r
-**/\r
-#define PAL_MC_ERROR_INFO 25\r
-\r
-/**\r
- PAL Procedure - PAL_MC_EXPECTED.\r
-\r
- Set/Reset Expected Machine Check Indicator. It is required by\r
- Itanium processors. The PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical mode.\r
-\r
- @param Index Index of PAL_MC_EXPECTED within the list of PAL\r
- procedures.\r
- @param Expected Unsigned integer with a value of 0 or 1 to\r
- set or reset the hardware resource\r
- PALE_CHECK examines for expected machine\r
- checks.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Unsigned integer denoting whether a machine check\r
- was previously expected.\r
-\r
-**/\r
-#define PAL_MC_EXPECTED 23\r
-\r
-/**\r
- PAL Procedure - PAL_MC_REGISTER_MEM.\r
-\r
- Register min-state save area with PAL for machine checks and\r
- inits. It is required by Itanium processors. The PAL procedure supports the\r
- Static Registers calling convention. It could be called at\r
- physical mode.\r
-\r
- @param Index Index of PAL_MC_REGISTER_MEM within the list of PAL\r
- procedures.\r
- @param Address Physical address of the buffer to be\r
- registered with PAL.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_MC_REGISTER_MEM 27\r
-\r
-/**\r
- PAL Procedure - PAL_MC_RESUME.\r
-\r
- Restore minimal architected state and return to interrupted\r
- process. It is required by Itanium processors. The PAL procedure supports the\r
- Static Registers calling convention. It could be called at\r
- physical mode.\r
-\r
- @param Index Index of PAL_MC_RESUME within the list of PAL\r
- procedures.\r
- @param SetCmci Unsigned 64 bit integer denoting whether to\r
- set the CMC interrupt. A value of 0 indicates\r
- not to set the interrupt, a value of 1\r
- indicated to set the interrupt, and all other\r
- values are reserved.\r
- @param SavePtr Physical address of min-state save area used\r
- to used to restore processor state.\r
- @param NewContext Unsigned 64-bit integer denoting whether\r
- the caller is returning to a new context.\r
- A value of 0 indicates the caller is\r
- returning to the interrupted context, a\r
- value of 1 indicates that the caller is\r
- returning to a new context.\r
-\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_MC_RESUME 26\r
-\r
-/**\r
- PAL Procedure - PAL_HALT.\r
-\r
- Enter the low-power HALT state or an implementation-dependent\r
- low-power state. It is optinal. The PAL procedure supports the\r
- Static Registers calling convention. It could be called at\r
- physical mode.\r
-\r
- @param Index Index of PAL_HALT within the list of PAL\r
- procedures.\r
- @param HaltState Unsigned 64-bit integer denoting low power\r
- state requested.\r
- @param IoDetailPtr 8-byte aligned physical address pointer to\r
- information on the type of I/O\r
- (load/store) requested.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Value returned if a load instruction is requested\r
- in the io_detail_ptr\r
-\r
-**/\r
-#define PAL_HALT 28\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_HALT_INFO.\r
-\r
- Return the low power capabilities of the processor. It is\r
- required by Itanium processors. The PAL procedure supports the\r
- Stacked Registers calling convention. It could be called at\r
- physical and virtual mode.\r
-\r
- @param Index Index of PAL_HALT_INFO within the list of PAL\r
- procedures.\r
- @param PowerBuffer 64-bit pointer to a 64-byte buffer aligned\r
- on an 8-byte boundary.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_HALT_INFO 257\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_HALT_LIGHT.\r
-\r
- Enter the low power LIGHT HALT state. It is required by\r
- Itanium processors. The PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical and virtual mode.\r
-\r
- @param Index Index of PAL_HALT_LIGHT within the list of PAL\r
- procedures.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_HALT_LIGHT 29\r
-\r
-/**\r
- PAL Procedure - PAL_CACHE_LINE_INIT.\r
-\r
- Initialize tags and data of a cache line for processor\r
- testing. It is required by Itanium processors. The PAL procedure supports the\r
- Static Registers calling convention. It could be called at\r
- physical and virtual mode.\r
-\r
- @param Index Index of PAL_CACHE_LINE_INIT within the list of PAL\r
- procedures.\r
- @param Address Unsigned 64-bit integer value denoting the\r
- physical address from which the physical page\r
- number is to be generated. The address must be\r
- an implemented physical address, bit 63 must\r
- be zero.\r
- @param DataValue 64-bit data value which is used to\r
- initialize the cache line.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_CACHE_LINE_INIT 31\r
-\r
-/**\r
- PAL Procedure - PAL_CACHE_READ.\r
-\r
- Read tag and data of a cache line for diagnostic testing. It\r
- is optional. The PAL procedure supports the\r
- Satcked Registers calling convention. It could be called at\r
- physical mode.\r
-\r
- @param Index Index of PAL_CACHE_READ within the list of PAL\r
- procedures.\r
- @param LineId 8-byte formatted value describing where in the\r
- cache to read the data.\r
- @param Address 64-bit 8-byte aligned physical address from\r
- which to read the data. The address must be an\r
- implemented physical address on the processor\r
- model with bit 63 set to zero.\r
-\r
- @retval 1 The word at address was found in the\r
- cache, but the line was invalid.\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -5 The word at address was not found in the\r
- cache.\r
- @retval -7 The operation requested is not supported\r
- for this cache_type and level.\r
-\r
- @return R9 Right-justified value returned from the cache\r
- line.\r
- @return R10 The number of bits returned in data.\r
- @return R11 The status of the cache line.\r
-\r
-**/\r
-#define PAL_CACHE_READ 259\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_CACHE_WRITE.\r
-\r
- Write tag and data of a cache for diagnostic testing. It is\r
- optional. The PAL procedure supports the Satcked Registers\r
- calling convention. It could be called at physical mode.\r
-\r
- @param Index Index of PAL_CACHE_WRITE within the list of PAL\r
- procedures.\r
- @param LineId 8-byte formatted value describing where in the\r
- cache to write the data.\r
- @param Address 64-bit 8-byte aligned physical address at\r
- which the data should be written. The address\r
- must be an implemented physical address on the\r
- processor model with bit 63 set to 0.\r
- @param Data Unsigned 64-bit integer value to write into\r
- the specified part of the cache.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -7 The operation requested is not supported\r
- for this cache_type and level.\r
-\r
-**/\r
-#define PAL_CACHE_WRITE 260\r
-\r
-/**\r
- PAL Procedure - PAL_TEST_INFO.\r
-\r
- Returns alignment and size requirements needed for the memory\r
- buffer passed to the PAL_TEST_PROC procedure as well as\r
- information on self-test control words for the processor self\r
- tests. It is required by Itanium processors. The PAL procedure supports the\r
- Static Registers calling convention. It could be called at\r
- physical mode.\r
-\r
- @param Index Index of PAL_TEST_INFO within the list of PAL\r
- procedures.\r
- @param TestPhase Unsigned integer that specifies which phase\r
- of the processor self-test information is\r
- being requested on. A value of 0 indicates\r
- the phase two of the processor self-test and\r
- a value of 1 indicates phase one of the\r
- processor self-test. All other values are\r
- reserved.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Unsigned 64-bit integer denoting the number of\r
- bytes of main memory needed to perform the second\r
- phase of processor self-test.\r
- @return R10 Unsigned 64-bit integer denoting the alignment\r
- required for the memory buffer.\r
- @return R11 48-bit wide bit-field indicating if control of\r
- the processor self-tests is supported and which\r
- bits of the test_control field are defined for\r
- use.\r
-\r
-**/\r
-#define PAL_TEST_INFO 37\r
-\r
-typedef struct {\r
- UINT64 BufferSize:56; ///< Indicates the size in bytes of the memory\r
- ///< buffer that is passed to this procedure.\r
- ///< BufferSize must be greater than or equal in\r
- ///< size to the bytes_needed return value from\r
- ///< PAL_TEST_INFO, otherwise this procedure will\r
- ///< return with an invalid argument return\r
- ///< value.\r
-\r
- UINT64 TestPhase:8; ///< Defines which phase of the processor\r
- ///< self-tests are requested to be run. A value\r
- ///< of zero indicates to run phase two of the\r
- ///< processor self-tests. Phase two of the\r
- ///< processor self-tests are ones that require\r
- ///< external memory to execute correctly. A\r
- ///< value of one indicates to run phase one of\r
- ///< the processor self-tests. Phase one of the\r
- ///< processor self-tests are tests run during\r
- ///< PALE_RESET and do not depend on external\r
- ///< memory to run correctly. When the caller\r
- ///< requests to have phase one of the processor\r
- ///< self-test run via this procedure call, a\r
- ///< memory buffer may be needed to save and\r
- ///< restore state as required by the PAL calling\r
- ///< conventions. The procedure PAL_TEST_INFO\r
- ///< informs the caller about the requirements of\r
- ///< the memory buffer.\r
-} PAL_TEST_INFO_INFO;\r
-\r
-typedef struct {\r
- UINT64 TestControl:47; ///< This is an ordered implementation-specific\r
- ///< control word that allows the user control\r
- ///< over the length and runtime of the\r
- ///< processor self-tests. This control word is\r
- ///< ordered from the longest running tests up\r
- ///< to the shortest running tests with bit 0\r
- ///< controlling the longest running test. PAL\r
- ///< may not implement all 47-bits of the\r
- ///< test_control word. PAL communicates if a\r
- ///< bit provides control by placing a zero in\r
- ///< that bit. If a bit provides no control,\r
- ///< PAL will place a one in it. PAL will have\r
- ///< two sets of test_control bits for the two\r
- ///< phases of the processor self-test. PAL\r
- ///< provides information about implemented\r
- ///< test_control bits at the hand-off from PAL\r
- ///< to SAL for the firmware recovery check.\r
- ///< These test_control bits provide control\r
- ///< for phase one of processor self-test. It\r
- ///< also provides this information via the PAL\r
- ///< procedure call PAL_TEST_INFO for both the\r
- ///< phase one and phase two processor tests\r
- ///< depending on which information the caller\r
- ///< is requesting. PAL interprets these bits\r
- ///< as input parameters on two occasions. The\r
- ///< first time is when SAL passes control back\r
- ///< to PAL after the firmware recovery check.\r
- ///< The second time is when a call to\r
- ///< PAL_TEST_PROC is made. When PAL interprets\r
- ///< these bits it will only interpret\r
- ///< implemented test_control bits and will\r
- ///< ignore the values located in the\r
- ///< unimplemented test_control bits. PAL\r
- ///< interprets the implemented bits such that\r
- ///< if a bit contains a zero, this indicates\r
- ///< to run the test. If a bit contains a one,\r
- ///< this indicates to PAL to skip the test. If\r
- ///< the cs bit indicates that control is not\r
- ///< available, the test_control bits will be\r
- ///< ignored or generate an illegal argument in\r
- ///< procedure calls if the caller sets these\r
- ///< bits.\r
-\r
- UINT64 ControlSupport:1; ///< This bit defines if an implementation\r
- ///< supports control of the PAL self-tests\r
- ///< via the self-test control word. If\r
- ///< this bit is 0, the implementation does\r
- ///< not support control of the processor\r
- ///< self-tests via the self-test control\r
- ///< word. If this bit is 1, the\r
- ///< implementation does support control of\r
- ///< the processor self-tests via the\r
- ///< self-test control word. If control is\r
- ///< not supported, GR37 will be ignored at\r
- ///< the hand-off between SAL and PAL after\r
- ///< the firmware recovery check and the\r
- ///< PAL procedures related to the\r
- ///< processor self-tests may return\r
- ///< illegal arguments if a user tries to\r
- ///< use the self-test control features.\r
- UINT64 Reserved:16;\r
-} PAL_SELF_TEST_CONTROL;\r
-\r
-typedef struct {\r
- UINT64 Attributes:8; ///< Specifies the memory attributes that are\r
- ///< allowed to be used with the memory buffer\r
- ///< passed to this procedure. The attributes\r
- ///< parameter is a vector where each bit\r
- ///< represents one of the virtual memory\r
- ///< attributes defined by the architecture.See\r
- ///< MEMORY_AATRIBUTES. The caller is required\r
- ///< to support the cacheable attribute for the\r
- ///< memory buffer, otherwise an invalid\r
- ///< argument will be returned.\r
- UINT64 Reserved:8;\r
- UINT64 TestControl:48; ///< Is the self-test control word\r
- ///< corresponding to the test_phase passed.\r
- ///< This test_control directs the coverage and\r
- ///< runtime of the processor self-tests\r
- ///< specified by the test_phase input\r
- ///< argument. Information on if this\r
- ///< feature is implemented and the number of\r
- ///< bits supported can be obtained by the\r
- ///< PAL_TEST_INFO procedure call. If this\r
- ///< feature is implemented by the processor,\r
- ///< the caller can selectively skip parts of\r
- ///< the processor self-test by setting\r
- ///< test_control bits to a one. If a bit has a\r
- ///< zero, this test will be run. The values in\r
- ///< the unimplemented bits are ignored. If\r
- ///< PAL_TEST_INFO indicated that the self-test\r
- ///< control word is not implemented, this\r
- ///< procedure will return with an invalid\r
- ///< argument status if the caller sets any of\r
- ///< the test_control bits. See\r
- ///< PAL_SELF_TEST_CONTROL.\r
-} PAL_TEST_CONTROL;\r
-\r
-/**\r
- PAL Procedure - PAL_TEST_PROC.\r
-\r
- Perform late processor self test. It is required by Itanium processors. The\r
- PAL procedure supports the Static Registers calling\r
- convention. It could be called at physical mode.\r
-\r
- @param Index Index of PAL_TEST_PROC within the list of PAL\r
- procedures.\r
- @param TestAddress 64-bit physical address of main memory\r
- area to be used by processor self-test.\r
- The memory region passed must be\r
- cacheable, bit 63 must be zero.\r
- @param TestInfo Input argument specifying the size of the\r
- memory buffer passed and the phase of the\r
- processor self-test that should be run. See\r
- PAL_TEST_INFO.\r
- @param TestParam Input argument specifying the self-test\r
- control word and the allowable memory\r
- attributes that can be used with the memory\r
- buffer. See PAL_TEST_CONTROL.\r
-\r
- @retval 1 Call completed without error, but hardware\r
- failures occurred during self-test.\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Formatted 8-byte value denoting the state of the\r
- processor after self-test\r
-\r
-**/\r
-#define PAL_TEST_PROC 258\r
-\r
-typedef struct {\r
- UINT32 NumberOfInterruptControllers; ///< Number of interrupt\r
- ///< controllers currently\r
- ///< enabled on the system.\r
-\r
- UINT32 NumberOfProcessors; ///< Number of processors currently\r
- ///< enabled on the system.\r
-} PAL_PLATFORM_INFO;\r
-\r
-/**\r
- PAL Procedure - PAL_COPY_INFO.\r
-\r
- Return information needed to relocate PAL procedures and PAL\r
- PMI code to memory. It is required by Itanium processors. The PAL procedure\r
- supports the Static Registers calling convention. It could be\r
- called at physical mode.\r
-\r
- @param Index Index of PAL_COPY_INFO within the list of PAL\r
- procedures.\r
- @param CopyType Unsigned integer denoting type of procedures\r
- for which copy information is requested.\r
- @param PlatformInfo 8-byte formatted value describing the\r
- number of processors and the number of\r
- interrupt controllers currently enabled\r
- on the system. See PAL_PLATFORM_INFO.\r
- @param McaProcStateInfo Unsigned integer denoting the number\r
- of bytes that SAL needs for the\r
- min-state save area for each\r
- processor.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Unsigned integer denoting the number of bytes of\r
- PAL information that must be copied to main\r
- memory.\r
- @return R10 Unsigned integer denoting the starting alignment\r
- of the data to be copied.\r
-\r
-**/\r
-#define PAL_COPY_INFO 30\r
-\r
-/**\r
- PAL Procedure - PAL_COPY_PAL.\r
-\r
- Relocate PAL procedures and PAL PMI code to memory. It is\r
- required by Itanium processors. The PAL procedure supports the Stacked\r
- Registers calling convention. It could be called at physical\r
- mode.\r
-\r
- @param Index Index of PAL_COPY_PAL within the list of PAL\r
- procedures.\r
- @param TargetAddress Physical address of a memory buffer to\r
- copy relocatable PAL procedures and PAL\r
- PMI code.\r
- @param AllocSize Unsigned integer denoting the size of the\r
- buffer passed by SAL for the copy operation.\r
- @param CopyOption Unsigned integer indicating whether\r
- relocatable PAL code and PAL PMI code\r
- should be copied from firmware address\r
- space to main memory.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Unsigned integer denoting the offset of PAL_PROC\r
- in the relocatable segment copied.\r
-\r
-**/\r
-#define PAL_COPY_PAL 256\r
-\r
-/**\r
- PAL Procedure - PAL_ENTER_IA_32_ENV.\r
-\r
- Enter IA-32 System environment. It is optional. The PAL\r
- procedure supports the Static Registers calling convention.\r
- It could be called at physical mode.\r
-\r
- Note: Since this is a special call, it does not follow the PAL\r
- static register calling convention. GR28 contains the index of\r
- PAL_ENTER_IA_32_ENV within the list of PAL procedures. All other\r
- input arguments including GR29-GR31 are setup by SAL to values\r
- as required by the IA-32 operating system defined in Table\r
- 11-67. The registers that are designated as preserved, scratch,\r
- input arguments and procedure return values by the static\r
- procedure calling convention are not followed by this call. For\r
- instance, GR5 and GR6 need not be preserved since these are\r
- regarded as scratch by the IA-32 operating system. Note: In an\r
- MP system, this call must be COMPLETED on the first CPU to enter\r
- the IA-32 System Environment (may or may not be the BSP) prior\r
- to being called on the remaining processors in the MP system.\r
-\r
- @param Index GR28 contains the index of the\r
- PAL_ENTER_IA_32_ENV call within the list of PAL\r
- procedures.\r
-\r
-\r
- @retval The status is returned in GR4.\r
- -1 - Un-implemented procedure 0 JMPE detected\r
- at privilege level\r
-\r
- 0 - 1 SAL allocated buffer for IA-32 System\r
- Environment operation is too small\r
-\r
- 2 - IA-32 Firmware Checksum Error\r
-\r
- 3 - SAL allocated buffer for IA-32 System\r
- Environment operation is not properly aligned\r
-\r
- 4 - Error in SAL MP Info Table\r
-\r
- 5 - Error in SAL Memory Descriptor Table\r
-\r
- 6 - Error in SAL System Table\r
-\r
- 7 - Inconsistent IA-32 state\r
-\r
- 8 - IA-32 Firmware Internal Error\r
-\r
- 9 - IA-32 Soft Reset (Note: remaining register\r
- state is undefined for this termination\r
- reason)\r
-\r
- 10 - Machine Check Error\r
-\r
- 11 - Error in SAL I/O Intercept Table\r
-\r
- 12 - Processor exit due to other processor in\r
- MP system terminating the IA32 system\r
- environment. (Note: remaining register state\r
- is undefined for this termination reason.)\r
-\r
- 13 - Itanium architecture-based state\r
- corruption by either SAL PMI handler or I/O\r
- Intercept callback function.\r
-\r
-\r
-**/\r
-#define PAL_ENTER_IA_32_ENV 33\r
-\r
-/**\r
- PAL Procedure - PAL_PMI_ENTRYPOINT.\r
-\r
- Register PMI memory entrypoints with processor. It is required\r
- by Itanium processors. The PAL procedure supports the Stacked Registers\r
- calling convention. It could be called at physical mode.\r
-\r
- @param Index Index of PAL_PMI_ENTRYPOINT within the list of\r
- PAL procedures.\r
- @param SalPmiEntry 256-byte aligned physical address of SAL\r
- PMI entrypoint in memory.\r
-\r
- @retval 0 Call completed without error\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
-**/\r
-#define PAL_PMI_ENTRYPOINT 32\r
-\r
-\r
-/**\r
-\r
- The ASCII brand identification string will be copied to the\r
- address specified in the address input argument. The processor\r
- brand identification string is defined to be a maximum of 128\r
- characters long; 127 bytes will contain characters and the 128th\r
- byte is defined to be NULL (0). A processor may return less than\r
- the 127 ASCII characters as long as the string is null\r
- terminated. The string length will be placed in the brand_info\r
- return argument.\r
-\r
-**/\r
-#define PAL_BRAND_INFO_ID_REQUEST 0\r
-\r
-/**\r
- PAL Procedure - PAL_BRAND_INFO.\r
-\r
- Provides processor branding information. It is optional by\r
- Itanium processors. The PAL procedure supports the Stacked Registers calling\r
- convention. It could be called at physical and Virtual mode.\r
-\r
- @param Index Index of PAL_BRAND_INFO within the list of PAL\r
- procedures.\r
- @param InfoRequest Unsigned 64-bit integer specifying the\r
- information that is being requested. (See\r
- PAL_BRAND_INFO_ID_REQUEST)\r
- @param Address Unsigned 64-bit integer specifying the\r
- address of the 128-byte block to which the\r
- processor brand string shall be written.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -6 Input argument is not implemented.\r
-\r
- @return R9 Brand information returned. The format of this\r
- value is dependent on the input values passed.\r
-\r
-**/\r
-#define PAL_BRAND_INFO 274\r
-\r
-/**\r
- PAL Procedure - PAL_GET_HW_POLICY.\r
-\r
- Returns the current hardware resource sharing policy of the\r
- processor. It is optional by Itanium processors. The PAL procedure supports\r
- the Static Registers calling convention. It could be called at\r
- physical and Virtual mode.\r
-\r
-\r
- @param Index Index of PAL_GET_HW_POLICY within the list of PAL\r
- procedures.\r
- @param ProcessorNumber Unsigned 64-bit integer that specifies\r
- for which logical processor\r
- information is being requested. This\r
- input argument must be zero for the\r
- first call to this procedure and can\r
- be a maximum value of one less than\r
- the number of logical processors\r
- impacted by the hardware resource\r
- sharing policy, which is returned by\r
- the R10 return value.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
- @return R9 Unsigned 64-bit integer representing the current\r
- hardware resource sharing policy.\r
- @return R10 Unsigned 64-bit integer that returns the number\r
- of logical processors impacted by the policy\r
- input argument.\r
- @return R11 Unsigned 64-bit integer containing the logical\r
- address of one of the logical processors\r
- impacted by policy modification.\r
-\r
-**/\r
-#define PAL_GET_HW_POLICY 48\r
-\r
-\r
-//\r
-// Value of PAL_SET_HW_POLICY.Policy\r
-//\r
-#define PAL_SET_HW_POLICY_PERFORMANCE 0\r
-#define PAL_SET_HW_POLICY_FAIRNESS 1\r
-#define PAL_SET_HW_POLICY_HIGH_PRIORITY 2\r
-#define PAL_SET_HW_POLICY_EXCLUSIVE_HIGH_PRIORITY 3\r
-\r
-/**\r
- PAL Procedure - PAL_SET_HW_POLICY.\r
-\r
- Sets the current hardware resource sharing policy of the\r
- processor. It is optional by Itanium processors. The PAL procedure supports\r
- the Static Registers calling convention. It could be called at\r
- physical and Virtual mode.\r
-\r
- @param Index Index of PAL_SET_HW_POLICY within the list of PAL\r
- procedures.\r
- @param Policy Unsigned 64-bit integer specifying the hardware\r
- resource sharing policy the caller is setting.\r
- See Value of PAL_SET_HW_POLICY.Policy above.\r
-\r
- @retval 1 Call completed successfully but could not\r
- change the hardware policy since a\r
- competing logical processor is set in\r
- exclusive high priority.\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
-**/\r
-#define PAL_SET_HW_POLICY 49\r
-\r
-typedef struct {\r
- UINT64 Mode:3; ///< Bit2:0, Indicates the mode of operation for this\r
- ///< procedure: 0 - Query mode 1 - Error inject mode\r
- ///< (err_inj should also be specified) 2 - Cancel\r
- ///< outstanding trigger. All other fields in\r
- ///< PAL_MC_ERROR_TYPE_INFO,\r
- ///< PAL_MC_ERROR_STRUCTURE_INFO and\r
- ///< PAL_MC_ERROR_DATA_BUFFER are ignored. All other\r
- ///< values are reserved.\r
-\r
- UINT64 ErrorInjection:3; ///< Bit5:3, indicates the mode of error\r
- ///< injection: 0 - Error inject only (no\r
- ///< error consumption) 1 - Error inject\r
- ///< and consume All other values are\r
- ///< reserved.\r
-\r
- UINT64 ErrorSeverity:2; ///< Bit7:6, indicates the severity desired\r
- ///< for error injection/query. Definitions\r
- ///< of the different error severity types\r
- ///< 0 - Corrected error 1 - Recoverable\r
- ///< error 2 - Fatal error 3 - Reserved\r
-\r
- UINT64 ErrorStructure:5; ///< Bit12:8, Indicates the structure\r
- ///< identification for error\r
- ///< injection/query: 0 - Any structure\r
- ///< (cannot be used during query mode).\r
- ///< When selected, the structure type used\r
- ///< for error injection is determined by\r
- ///< PAL. 1 - Cache 2 - TLB 3 - Register\r
- ///< file 4 - Bus/System interconnect 5-15\r
- ///< - Reserved 16-31 - Processor\r
- ///< specific error injection\r
- ///< capabilities.ErrorDataBuffer is used\r
- ///< to specify error types. Please refer\r
- ///< to the processor specific\r
- ///< documentation for additional details.\r
-\r
- UINT64 StructureHierarchy:3; ///< Bit15:13, Indicates the structure\r
- ///< hierarchy for error\r
- ///< injection/query: 0 - Any level of\r
- ///< hierarchy (cannot be used during\r
- ///< query mode). When selected, the\r
- ///< structure hierarchy used for error\r
- ///< injection is determined by PAL. 1\r
- ///< - Error structure hierarchy\r
- ///< level-1 2 - Error structure\r
- ///< hierarchy level-2 3 - Error\r
- ///< structure hierarchy level-3 4 -\r
- ///< Error structure hierarchy level-4\r
- ///< All other values are reserved.\r
-\r
- UINT64 Reserved:32; ///< Reserved 47:16 Reserved\r
-\r
- UINT64 ImplSpec:16; ///< Bit63:48, Processor specific error injection capabilities.\r
-} PAL_MC_ERROR_TYPE_INFO;\r
-\r
-typedef struct {\r
- UINT64 StructInfoIsValid:1; ///< Bit0 When 1, indicates that the\r
- ///< structure information fields\r
- ///< (c_t,cl_p,cl_id) are valid and\r
- ///< should be used for error injection.\r
- ///< When 0, the structure information\r
- ///< fields are ignored, and the values\r
- ///< of these fields used for error\r
- ///< injection are\r
- ///< implementation-specific.\r
-\r
- UINT64 CacheType:2; ///< Bit2:1 Indicates which cache should be used\r
- ///< for error injection: 0 - Reserved 1 -\r
- ///< Instruction cache 2 - Data or unified cache\r
- ///< 3 - Reserved\r
-\r
- UINT64 PortionOfCacheLine:3; ///< Bit5:3 Indicates the portion of the\r
- ///< cache line where the error should\r
- ///< be injected: 0 - Reserved 1 - Tag\r
- ///< 2 - Data 3 - mesi All other\r
- ///< values are reserved.\r
-\r
- UINT64 Mechanism:3; ///< Bit8:6 Indicates which mechanism is used to\r
- ///< identify the cache line to be used for error\r
- ///< injection: 0 - Reserved 1 - Virtual address\r
- ///< provided in the inj_addr field of the buffer\r
- ///< pointed to by err_data_buffer should be used\r
- ///< to identify the cache line for error\r
- ///< injection. 2 - Physical address provided in\r
- ///< the inj_addr field of the buffer pointed to\r
- ///< by err_data_buffershould be used to identify\r
- ///< the cache line for error injection. 3 - way\r
- ///< and index fields provided in err_data_buffer\r
- ///< should be used to identify the cache line\r
- ///< for error injection. All other values are\r
- ///< reserved.\r
-\r
- UINT64 DataPoisonOfCacheLine:1; ///< Bit9 When 1, indicates that a\r
- ///< multiple bit, non-correctable\r
- ///< error should be injected in the\r
- ///< cache line specified by cl_id.\r
- ///< If this injected error is not\r
- ///< consumed, it may eventually\r
- ///< cause a data-poisoning event\r
- ///< resulting in a corrected error\r
- ///< signal, when the associated\r
- ///< cache line is cast out (implicit\r
- ///< or explicit write-back of the\r
- ///< cache line). The error severity\r
- ///< specified by err_sev in\r
- ///< err_type_info must be set to 0\r
- ///< (corrected error) when this bit\r
- ///< is set.\r
-\r
- UINT64 Reserved1:22;\r
-\r
- UINT64 TrigerInfoIsValid:1; ///< Bit32 When 1, indicates that the\r
- ///< trigger information fields (trigger,\r
- ///< trigger_pl) are valid and should be\r
- ///< used for error injection. When 0,\r
- ///< the trigger information fields are\r
- ///< ignored and error injection is\r
- ///< performed immediately.\r
-\r
- UINT64 Triger:4; ///< Bit36:33 Indicates the operation type to be\r
- ///< used as the error trigger condition. The\r
- ///< address corresponding to the trigger is\r
- ///< specified in the trigger_addr field of the\r
- ///< buffer pointed to by err_data_buffer: 0 -\r
- ///< Instruction memory access. The trigger match\r
- ///< conditions for this operation type are similar\r
- ///< to the IBR address breakpoint match conditions\r
- ///< 1 - Data memory access. The trigger match\r
- ///< conditions for this operation type are similar\r
- ///< to the DBR address breakpoint match conditions\r
- ///< All other values are reserved.\r
-\r
- UINT64 PrivilegeOfTriger:3; ///< Bit39:37 Indicates the privilege\r
- ///< level of the context during which\r
- ///< the error should be injected: 0 -\r
- ///< privilege level 0 1 - privilege\r
- ///< level 1 2 - privilege level 2 3 -\r
- ///< privilege level 3 All other values\r
- ///< are reserved. If the implementation\r
- ///< does not support privilege level\r
- ///< qualifier for triggers (i.e. if\r
- ///< trigger_pl is 0 in the capabilities\r
- ///< vector), this field is ignored and\r
- ///< triggers can be taken at any\r
- ///< privilege level.\r
-\r
- UINT64 Reserved2:24;\r
-} PAL_MC_ERROR_STRUCT_INFO;\r
-\r
-/**\r
-\r
- Buffer Pointed to by err_data_buffer - TLB\r
-\r
-**/\r
-typedef struct {\r
- UINT64 TrigerAddress;\r
- UINT64 VirtualPageNumber:52;\r
- UINT64 Reserved1:8;\r
- UINT64 RegionId:24;\r
- UINT64 Reserved2:40;\r
-} PAL_MC_ERROR_DATA_BUFFER_TLB;\r
-\r
-/**\r
- PAL Procedure - PAL_MC_ERROR_INJECT.\r
-\r
- Injects the requested processor error or returns information\r
- on the supported injection capabilities for this particular\r
- processor implementation. It is optional by Itanium processors. The PAL\r
- procedure supports the Stacked Registers calling convention.\r
- It could be called at physical and Virtual mode.\r
-\r
- @param Index Index of PAL_MC_ERROR_INJECT within the list of PAL\r
- procedures.\r
- @param ErrorTypeInfo Unsigned 64-bit integer specifying the\r
- first level error information which\r
- identifies the error structure and\r
- corresponding structure hierarchy, and\r
- the error severity.\r
- @param ErrorStructInfo Unsigned 64-bit integer identifying\r
- the optional structure specific\r
- information that provides the second\r
- level details for the requested error.\r
- @param ErrorDataBuffer 64-bit physical address of a buffer\r
- providing additional parameters for\r
- the requested error. The address of\r
- this buffer must be 8-byte aligned.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -4 Call completed with error; the requested\r
- error could not be injected due to failure in\r
- locating the target location in the specified\r
- structure.\r
- @retval -5 Argument was valid, but requested error\r
- injection capability is not supported.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
- @return R9 64-bit vector specifying the supported error\r
- injection capabilities for the input argument\r
- combination of struct_hier, err_struct and\r
- err_sev fields in ErrorTypeInfo.\r
- @return R10 64-bit vector specifying the architectural\r
- resources that are used by the procedure.\r
-\r
-**/\r
-#define PAL_MC_ERROR_INJECT 276\r
-\r
-\r
-//\r
-// Types of PAL_GET_PSTATE.Type\r
-//\r
-#define PAL_GET_PSTATE_RECENT 0\r
-#define PAL_GET_PSTATE_AVERAGE_NEW_START 1\r
-#define PAL_GET_PSTATE_AVERAGE 2\r
-#define PAL_GET_PSTATE_NOW 3\r
-\r
-/**\r
- PAL Procedure - PAL_GET_PSTATE.\r
-\r
- Returns the performance index of the processor. It is optional\r
- by Itanium processors. The PAL procedure supports the Stacked Registers\r
- calling convention. It could be called at physical and Virtual\r
- mode.\r
-\r
- @param Index Index of PAL_GET_PSTATE within the list of PAL\r
- procedures.\r
- @param Type Type of performance_index value to be returned\r
- by this procedure.See PAL_GET_PSTATE.Type above.\r
-\r
- @retval 1 Call completed without error, but accuracy\r
- of performance index has been impacted by a\r
- thermal throttling event, or a\r
- hardware-initiated event.\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
- @return R9 Unsigned integer denoting the processor\r
- performance for the time duration since the last\r
- PAL_GET_PSTATE procedure call was made. The\r
- value returned is between 0 and 100, and is\r
- relative to the performance index of the highest\r
- available P-state.\r
-\r
-**/\r
-#define PAL_GET_PSTATE 262\r
-\r
-/**\r
-\r
- Layout of PAL_PSTATE_INFO.PStateBuffer\r
-\r
-**/\r
-typedef struct {\r
- UINT32 PerformanceIndex:7;\r
- UINT32 Reserved1:5;\r
- UINT32 TypicalPowerDissipation:20;\r
- UINT32 TransitionLatency1;\r
- UINT32 TransitionLatency2;\r
- UINT32 Reserved2;\r
-} PAL_PSTATE_INFO_BUFFER;\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_PSTATE_INFO.\r
-\r
- Returns information about the P-states supported by the\r
- processor. It is optional by Itanium processors. The PAL procedure supports\r
- the Static Registers calling convention. It could be called\r
- at physical and Virtual mode.\r
-\r
- @param Index Index of PAL_PSTATE_INFO within the list of PAL\r
- procedures.\r
- @param PStateBuffer 64-bit pointer to a 256-byte buffer\r
- aligned on an 8-byte boundary. See\r
- PAL_PSTATE_INFO_BUFFER above.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
-\r
- @return R9 Unsigned integer denoting the number of P-states\r
- supported. The maximum value of this field is 16.\r
- @return R10 Dependency domain information\r
-\r
-**/\r
-#define PAL_PSTATE_INFO 44\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_SET_PSTATE.\r
-\r
- To request a processor transition to a given P-state. It is\r
- optional by Itanium processors. The PAL procedure supports the Stacked\r
- Registers calling convention. It could be called at physical\r
- and Virtual mode.\r
-\r
- @param Index Index of PAL_SET_PSTATE within the list of PAL\r
- procedures.\r
- @param PState Unsigned integer denoting the processor\r
- P-state being requested.\r
- @param ForcePState Unsigned integer denoting whether the\r
- P-state change should be forced for the\r
- logical processor.\r
-\r
- @retval 1 Call completed without error, but\r
- transition request was not accepted\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
-**/\r
-#define PAL_SET_PSTATE 263\r
-\r
-/**\r
- PAL Procedure - PAL_SHUTDOWN.\r
-\r
- Put the logical processor into a low power state which can be\r
- exited only by a reset event. It is optional by Itanium processors. The PAL\r
- procedure supports the Static Registers calling convention. It\r
- could be called at physical mode.\r
-\r
- @param Index Index of PAL_SHUTDOWN within the list of PAL\r
- procedures.\r
- @param NotifyPlatform 8-byte aligned physical address\r
- pointer providing details on how to\r
- optionally notify the platform that\r
- the processor is entering a shutdown\r
- state.\r
-\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
-**/\r
-#define PAL_SHUTDOWN 45\r
-\r
-/**\r
-\r
- Layout of PAL_MEMORY_BUFFER.ControlWord\r
-\r
-**/\r
-typedef struct {\r
- UINT64 Registration:1;\r
- UINT64 ProbeInterrupt:1;\r
- UINT64 Reserved:62;\r
-} PAL_MEMORY_CONTROL_WORD;\r
-\r
-/**\r
- PAL Procedure - PAL_MEMORY_BUFFER.\r
-\r
- Provides cacheable memory to PAL for exclusive use during\r
- runtime. It is optional by Itanium processors. The PAL procedure supports the\r
- Static Registers calling convention. It could be called at\r
- physical mode.\r
-\r
- @param Index Index of PAL_MEMORY_BUFFER within the list of PAL\r
- procedures.\r
- @param BaseAddress Physical address of the memory buffer\r
- allocated for PAL use.\r
- @param AllocSize Unsigned integer denoting the size of the\r
- memory buffer.\r
- @param ControlWord Formatted bit vector that provides control\r
- options for this procedure. See\r
- PAL_MEMORY_CONTROL_WORD above.\r
-\r
- @retval 1 Call has not completed a buffer relocation\r
- due to a pending interrupt\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
- @return R9 Returns the minimum size of the memory buffer\r
- required if the alloc_size input argument was\r
- not large enough.\r
-\r
-**/\r
-#define PAL_MEMORY_BUFFER 277\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_VP_CREATE.\r
-\r
- Initializes a new vpd for the operation of a new virtual\r
- processor in the virtual environment. It is optional by Itanium processors.\r
- The PAL procedure supports the Stacked Registers calling\r
- convention. It could be called at Virtual mode.\r
-\r
- @param Index Index of PAL_VP_CREATE within the list of PAL\r
- procedures.\r
- @param Vpd 64-bit host virtual pointer to the Virtual\r
- Processor Descriptor (VPD).\r
- @param HostIva 64-bit host virtual pointer to the host IVT\r
- for the virtual processor\r
- @param OptionalHandler 64-bit non-zero host-virtual pointer\r
- to an optional handler for\r
- virtualization intercepts.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
-**/\r
-#define PAL_VP_CREATE 265\r
-\r
-/**\r
-\r
- Virtual Environment Information Parameter\r
-\r
-**/\r
-typedef struct {\r
- UINT64 Reserved1:8;\r
- UINT64 Opcode:1;\r
- UINT64 Reserved:53;\r
-} PAL_VP_ENV_INFO_RETURN;\r
-\r
-/**\r
- PAL Procedure - PAL_VP_ENV_INFO.\r
-\r
- Returns the parameters needed to enter a virtual environment.\r
- It is optional by Itanium processors. The PAL procedure supports the Stacked\r
- Registers calling convention. It could be called at Virtual\r
- mode.\r
-\r
- @param Index Index of PAL_VP_ENV_INFO within the list of PAL\r
- procedures.\r
- @param Vpd 64-bit host virtual pointer to the Virtual\r
- Processor Descriptor (VPD).\r
- @param HostIva 64-bit host virtual pointer to the host IVT\r
- for the virtual processor\r
- @param OptionalHandler 64-bit non-zero host-virtual pointer\r
- to an optional handler for\r
- virtualization intercepts.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
- @return R9 Unsigned integer denoting the number of bytes\r
- required by the PAL virtual environment buffer\r
- during PAL_VP_INIT_ENV\r
- @return R10 64-bit vector of virtual environment\r
- information. See PAL_VP_ENV_INFO_RETURN.\r
-\r
-\r
-**/\r
-#define PAL_VP_ENV_INFO 266\r
-\r
-/**\r
- PAL Procedure - PAL_VP_EXIT_ENV.\r
-\r
- Allows a logical processor to exit a virtual environment.\r
- It is optional by Itanium processors. The PAL procedure supports the Stacked\r
- Registers calling convention. It could be called at Virtual\r
- mode.\r
-\r
- @param Index Index of PAL_VP_EXIT_ENV within the list of PAL\r
- procedures.\r
- @param Iva Optional 64-bit host virtual pointer to the IVT\r
- when this procedure is done\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
-**/\r
-#define PAL_VP_EXIT_ENV 267\r
-\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_VP_INIT_ENV.\r
-\r
- Allows a logical processor to enter a virtual environment. It\r
- is optional by Itanium processors. The PAL procedure supports the Stacked\r
- Registers calling convention. It could be called at Virtual\r
- mode.\r
-\r
- @param Index Index of PAL_VP_INIT_ENV within the list of PAL\r
- procedures.\r
- @param ConfigOptions 64-bit vector of global configuration\r
- settings.\r
- @param PhysicalBase Host physical base address of a block of\r
- contiguous physical memory for the PAL\r
- virtual environment buffer 1) This\r
- memory area must be allocated by the VMM\r
- and be 4K aligned. The first logical\r
- processor to enter the environment will\r
- initialize the physical block for\r
- virtualization operations.\r
- @param VirtualBase Host virtual base address of the\r
- corresponding physical memory block for\r
- the PAL virtual environment buffer : The\r
- VMM must maintain the host virtual to host\r
- physical data and instruction translations\r
- in TRs for addresses within the allocated\r
- address space. Logical processors in this\r
- virtual environment will use this address\r
- when transitioning to virtual mode\r
- operations.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
- @return R9 Virtualization Service Address - VSA specifies\r
- the virtual base address of the PAL\r
- virtualization services in this virtual\r
- environment.\r
-\r
-\r
-**/\r
-#define PAL_VP_INIT_ENV 268\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_VP_REGISTER.\r
-\r
- Register a different host IVT and/or a different optional\r
- virtualization intercept handler for the virtual processor\r
- specified by vpd. It is optional by Itanium processors. The PAL procedure\r
- supports the Stacked Registers calling convention. It could be\r
- called at Virtual mode.\r
-\r
- @param Index Index of PAL_VP_REGISTER within the list of PAL\r
- procedures.\r
- @param Vpd 64-bit host virtual pointer to the Virtual\r
- Processor Descriptor (VPD) host_iva 64-bit host\r
- virtual pointer to the host IVT for the virtual\r
- processor\r
- @param OptionalHandler 64-bit non-zero host-virtual pointer\r
- to an optional handler for\r
- virtualization intercepts.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
-**/\r
-#define PAL_VP_REGISTER 269\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_VP_RESTORE.\r
-\r
- Restores virtual processor state for the specified vpd on the\r
- logical processor. It is optional by Itanium processors. The PAL procedure\r
- supports the Stacked Registers calling convention. It could be\r
- called at Virtual mode.\r
-\r
- @param Index Index of PAL_VP_RESTORE within the list of PAL\r
- procedures.\r
- @param Vpd 64-bit host virtual pointer to the Virtual\r
- Processor Descriptor (VPD) host_iva 64-bit host\r
- virtual pointer to the host IVT for the virtual\r
- processor\r
- @param PalVector Vector specifies PAL procedure\r
- implementation-specific state to be\r
- restored.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
-**/\r
-#define PAL_VP_RESTORE 270\r
-\r
-/**\r
- PAL Procedure - PAL_VP_SAVE.\r
-\r
- Saves virtual processor state for the specified vpd on the\r
- logical processor. It is optional by Itanium processors. The PAL procedure\r
- supports the Stacked Registers calling convention. It could be\r
- called at Virtual mode.\r
-\r
- @param Index Index of PAL_VP_SAVE within the list of PAL\r
- procedures.\r
- @param Vpd 64-bit host virtual pointer to the Virtual\r
- Processor Descriptor (VPD) host_iva 64-bit host\r
- virtual pointer to the host IVT for the virtual\r
- processor\r
- @param PalVector Vector specifies PAL procedure\r
- implementation-specific state to be\r
- restored.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
-**/\r
-#define PAL_VP_SAVE 271\r
-\r
-\r
-/**\r
- PAL Procedure - PAL_VP_TERMINATE.\r
-\r
- Terminates operation for the specified virtual processor. It\r
- is optional by Itanium processors. The PAL procedure supports the Stacked\r
- Registers calling convention. It could be called at Virtual\r
- mode.\r
-\r
- @param Index Index of PAL_VP_TERMINATE within the list of PAL\r
- procedures.\r
- @param Vpd 64-bit host virtual pointer to the Virtual\r
- Processor Descriptor (VPD)\r
- @param Iva Optional 64-bit host virtual pointer to the IVT\r
- when this procedure is done.\r
-\r
- @retval 0 Call completed without error\r
- @retval -1 Unimplemented procedure\r
- @retval -2 Invalid argument\r
- @retval -3 Call completed with error.\r
- @retval -9 Call requires PAL memory buffer.\r
-\r
-**/\r
-#define PAL_VP_TERMINATE 272\r
-\r
-#endif\r
+++ /dev/null
-/** @file\r
- Main SAL API's defined in Intel Itanium Processor Family System Abstraction\r
- Layer Specification Revision 3.2 (December 2003)\r
-\r
-Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
-SPDX-License-Identifier: BSD-2-Clause-Patent\r
-\r
-**/\r
-\r
-#ifndef __SAL_API_H__\r
-#define __SAL_API_H__\r
-\r
-///\r
-/// SAL return status type\r
-///\r
-typedef INTN EFI_SAL_STATUS;\r
-\r
-///\r
-/// Call completed without error.\r
-///\r
-#define EFI_SAL_SUCCESS ((EFI_SAL_STATUS) 0)\r
-///\r
-/// Call completed without error, but some information was lost due to overflow.\r
-///\r
-#define EFI_SAL_OVERFLOW ((EFI_SAL_STATUS) 1)\r
-///\r
-/// Call completed without error; effect a warm boot of the system to complete the update.\r
-///\r
-#define EFI_SAL_WARM_BOOT_NEEDED ((EFI_SAL_STATUS) 2)\r
-///\r
-/// More information is available for retrieval.\r
-///\r
-#define EFI_SAL_MORE_RECORDS ((EFI_SAL_STATUS) 3)\r
-///\r
-/// Not implemented.\r
-///\r
-#define EFI_SAL_NOT_IMPLEMENTED ((EFI_SAL_STATUS) - 1)\r
-///\r
-/// Invalid Argument.\r
-///\r
-#define EFI_SAL_INVALID_ARGUMENT ((EFI_SAL_STATUS) - 2)\r
-///\r
-/// Call completed without error.\r
-///\r
-#define EFI_SAL_ERROR ((EFI_SAL_STATUS) - 3)\r
-///\r
-/// Virtual address not registered.\r
-///\r
-#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
-///\r
-/// No information available.\r
-///\r
-#define EFI_SAL_NO_INFORMATION ((EFI_SAL_STATUS) - 5)\r
-///\r
-/// Scratch buffer required.\r
-///\r
-#define EFI_SAL_NOT_ENOUGH_SCRATCH ((EFI_SAL_STATUS) - 9)\r
-\r
-///\r
-/// Return registers from SAL.\r
-///\r
-typedef struct {\r
- ///\r
- /// SAL return status value in r8.\r
- ///\r
- EFI_SAL_STATUS Status;\r
- ///\r
- /// SAL returned value in r9.\r
- ///\r
- UINTN r9;\r
- ///\r
- /// SAL returned value in r10.\r
- ///\r
- UINTN r10;\r
- ///\r
- /// SAL returned value in r11.\r
- ///\r
- UINTN r11;\r
-} SAL_RETURN_REGS;\r
-\r
-/**\r
- Prototype of SAL procedures.\r
-\r
- @param FunctionId Functional identifier.\r
- The upper 32 bits are ignored and only the lower 32 bits\r
- are used. The following functional identifiers are defined:\r
- 0x01XXXXXX - Architected SAL functional group.\r
- 0x02XXXXXX to 0x03XXXXXX - OEM SAL functional group. Each OEM is\r
- allowed to use the entire range in the 0x02XXXXXX to 0x03XXXXXX range.\r
- 0x04XXXXXX to 0xFFFFFFFF - Reserved.\r
- @param Arg1 The first parameter of the architected/OEM specific SAL functions.\r
- @param Arg2 The second parameter of the architected/OEM specific SAL functions.\r
- @param Arg3 The third parameter passed to the ESAL function based.\r
- @param Arg4 The fourth parameter passed to the ESAL function based.\r
- @param Arg5 The fifth parameter passed to the ESAL function based.\r
- @param Arg6 The sixth parameter passed to the ESAL function.\r
- @param Arg7 The seventh parameter passed to the ESAL function based.\r
-\r
- @return r8 Return status: positive number indicates successful,\r
- negative number indicates failure.\r
- r9 Other return parameter in r9.\r
- r10 Other return parameter in r10.\r
- r11 Other return parameter in r11.\r
-\r
-**/\r
-typedef\r
-SAL_RETURN_REGS\r
-(EFIAPI *SAL_PROC)(\r
- IN UINT64 FunctionId,\r
- IN UINT64 Arg1,\r
- IN UINT64 Arg2,\r
- IN UINT64 Arg3,\r
- IN UINT64 Arg4,\r
- IN UINT64 Arg5,\r
- IN UINT64 Arg6,\r
- IN UINT64 Arg7\r
- );\r
-\r
-//\r
-// SAL Procedure FunctionId definition\r
-//\r
-\r
-///\r
-/// Register software code locations with SAL.\r
-///\r
-#define EFI_SAL_SET_VECTORS 0x01000000\r
-///\r
-/// Return Machine State information obtained by SAL.\r
-///\r
-#define EFI_SAL_GET_STATE_INFO 0x01000001\r
-///\r
-/// Obtain size of Machine State information.\r
-///\r
-#define EFI_SAL_GET_STATE_INFO_SIZE 0x01000002\r
-///\r
-/// Clear Machine State information.\r
-///\r
-#define EFI_SAL_CLEAR_STATE_INFO 0x01000003\r
-///\r
-/// Cause the processor to go into a spin loop within SAL.\r
-///\r
-#define EFI_SAL_MC_RENDEZ 0x01000004\r
-///\r
-/// Register the machine check interface layer with SAL.\r
-///\r
-#define EFI_SAL_MC_SET_PARAMS 0x01000005\r
-///\r
-/// Register the physical addresses of locations needed by SAL.\r
-///\r
-#define EFI_SAL_REGISTER_PHYSICAL_ADDR 0x01000006\r
-///\r
-/// Flush the instruction or data caches.\r
-///\r
-#define EFI_SAL_CACHE_FLUSH 0x01000008\r
-///\r
-/// Initialize the instruction and data caches.\r
-///\r
-#define EFI_SAL_CACHE_INIT 0x01000009\r
-///\r
-/// Read from the PCI configuration space.\r
-///\r
-#define EFI_SAL_PCI_CONFIG_READ 0x01000010\r
-///\r
-/// Write to the PCI configuration space.\r
-///\r
-#define EFI_SAL_PCI_CONFIG_WRITE 0x01000011\r
-///\r
-/// Return the base frequency of the platform.\r
-///\r
-#define EFI_SAL_FREQ_BASE 0x01000012\r
-///\r
-/// Returns information on the physical processor mapping within the platform.\r
-///\r
-#define EFI_SAL_PHYSICAL_ID_INFO 0x01000013\r
-///\r
-/// Update the contents of firmware blocks.\r
-///\r
-#define EFI_SAL_UPDATE_PAL 0x01000020\r
-\r
-#define EFI_SAL_FUNCTION_ID_MASK 0x0000ffff\r
-#define EFI_SAL_MAX_SAL_FUNCTION_ID 0x00000021\r
-\r
-//\r
-// SAL Procedure parameter definitions\r
-// Not much point in using typedefs or enums because all params\r
-// are UINT64 and the entry point is common\r
-//\r
-\r
-//\r
-// Parameter of EFI_SAL_SET_VECTORS\r
-//\r
-// Vector type\r
-//\r
-#define EFI_SAL_SET_MCA_VECTOR 0x0\r
-#define EFI_SAL_SET_INIT_VECTOR 0x1\r
-#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR 0x2\r
-///\r
-/// The format of a length_cs_n argument.\r
-///\r
-typedef struct {\r
- UINT64 Length : 32;\r
- UINT64 ChecksumValid : 1;\r
- UINT64 Reserved1 : 7;\r
- UINT64 ByteChecksum : 8;\r
- UINT64 Reserved2 : 16;\r
-} SAL_SET_VECTORS_CS_N;\r
-\r
-//\r
-// Parameter of EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE, and EFI_SAL_CLEAR_STATE_INFO\r
-//\r
-// Type of information\r
-//\r
-#define EFI_SAL_MCA_STATE_INFO 0x0\r
-#define EFI_SAL_INIT_STATE_INFO 0x1\r
-#define EFI_SAL_CMC_STATE_INFO 0x2\r
-#define EFI_SAL_CP_STATE_INFO 0x3\r
-\r
-//\r
-// Parameter of EFI_SAL_MC_SET_PARAMS\r
-//\r
-// Unsigned 64-bit integer value for the parameter type of the machine check interface\r
-//\r
-#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
-#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
-#define EFI_SAL_MC_SET_CPE_PARAM 0x3\r
-//\r
-// Unsigned 64-bit integer value indicating whether interrupt vector or\r
-// memory address is specified\r
-//\r
-#define EFI_SAL_MC_SET_INTR_PARAM 0x1\r
-#define EFI_SAL_MC_SET_MEM_PARAM 0x2\r
-\r
-//\r
-// Parameter of EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
-//\r
-// The encoded value of the entity whose physical address is registered\r
-//\r
-#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
-\r
-//\r
-// Parameter of EFI_SAL_CACHE_FLUSH\r
-//\r
-// Unsigned 64-bit integer denoting type of cache flush operation\r
-//\r
-#define EFI_SAL_FLUSH_I_CACHE 0x01\r
-#define EFI_SAL_FLUSH_D_CACHE 0x02\r
-#define EFI_SAL_FLUSH_BOTH_CACHE 0x03\r
-#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
-\r
-//\r
-// Parameter of EFI_SAL_PCI_CONFIG_READ and EFI_SAL_PCI_CONFIG_WRITE\r
-//\r
-// PCI config size\r
-//\r
-#define EFI_SAL_PCI_CONFIG_ONE_BYTE 0x1\r
-#define EFI_SAL_PCI_CONFIG_TWO_BYTES 0x2\r
-#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
-//\r
-// The type of PCI configuration address\r
-//\r
-#define EFI_SAL_PCI_COMPATIBLE_ADDRESS 0x0\r
-#define EFI_SAL_PCI_EXTENDED_REGISTER_ADDRESS 0x1\r
-///\r
-/// The format of PCI Compatible Address.\r
-///\r
-typedef struct {\r
- UINT64 Register : 8;\r
- UINT64 Function : 3;\r
- UINT64 Device : 5;\r
- UINT64 Bus : 8;\r
- UINT64 Segment : 8;\r
- UINT64 Reserved : 32;\r
-} SAL_PCI_ADDRESS;\r
-///\r
-/// The format of Extended Register Address.\r
-///\r
-typedef struct {\r
- UINT64 Register : 8;\r
- UINT64 ExtendedRegister : 4;\r
- UINT64 Function : 3;\r
- UINT64 Device : 5;\r
- UINT64 Bus : 8;\r
- UINT64 Segment : 16;\r
- UINT64 Reserved : 20;\r
-} SAL_PCI_EXTENDED_REGISTER_ADDRESS;\r
-\r
-//\r
-// Parameter of EFI_SAL_FREQ_BASE\r
-//\r
-// Unsigned 64-bit integer specifying the type of clock source\r
-//\r
-#define EFI_SAL_CPU_INPUT_FREQ_BASE 0x0\r
-#define EFI_SAL_PLATFORM_IT_FREQ_BASE 0x1\r
-#define EFI_SAL_PLATFORM_RTC_FREQ_BASE 0x2\r
-\r
-//\r
-// Parameter and return value of EFI_SAL_UPDATE_PAL\r
-//\r
-// Return parameter provides additional information on the\r
-// failure when the status field contains a value of -3,\r
-// returned in r9.\r
-//\r
-#define EFI_SAL_UPDATE_BAD_PAL_VERSION ((UINT64) -1)\r
-#define EFI_SAL_UPDATE_PAL_AUTH_FAIL ((UINT64) -2)\r
-#define EFI_SAL_UPDATE_PAL_BAD_TYPE ((UINT64) -3)\r
-#define EFI_SAL_UPDATE_PAL_READONLY ((UINT64) -4)\r
-#define EFI_SAL_UPDATE_PAL_WRITE_FAIL ((UINT64) -10)\r
-#define EFI_SAL_UPDATE_PAL_ERASE_FAIL ((UINT64) -11)\r
-#define EFI_SAL_UPDATE_PAL_READ_FAIL ((UINT64) -12)\r
-#define EFI_SAL_UPDATE_PAL_CANT_FIT ((UINT64) -13)\r
-///\r
-/// 64-byte header of update data block.\r
-///\r
-typedef struct {\r
- UINT32 Size;\r
- UINT32 MmddyyyyDate;\r
- UINT16 Version;\r
- UINT8 Type;\r
- UINT8 Reserved[5];\r
- UINT64 FwVendorId;\r
- UINT8 Reserved2[40];\r
-} SAL_UPDATE_PAL_DATA_BLOCK;\r
-///\r
-/// Data structure pointed by the parameter param_buf.\r
-/// It is a 16-byte aligned data structure in memory with a length of 32 bytes\r
-/// that describes the new firmware. This information is organized in the form\r
-/// of a linked list with each element describing one firmware component.\r
-///\r
-typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
- struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
- struct SAL_UPDATE_PAL_DATA_BLOCK *DataBlock;\r
- UINT8 StoreChecksum;\r
- UINT8 Reserved[15];\r
-} SAL_UPDATE_PAL_INFO_BLOCK;\r
-\r
-///\r
-/// SAL System Table Definitions.\r
-///\r
-#pragma pack(1)\r
-typedef struct {\r
- ///\r
- /// The ASCII string representation of "SST_" that confirms the presence of the table.\r
- ///\r
- UINT32 Signature;\r
- ///\r
- /// The length of the entire table in bytes, starting from offset zero and including the\r
- /// header and all entries indicated by the EntryCount field.\r
- ///\r
- UINT32 Length;\r
- ///\r
- /// The revision number of the Itanium Processor Family System Abstraction Layer\r
- /// Specification supported by the SAL implementation, in binary coded decimal (BCD) format.\r
- ///\r
- UINT16 SalRevision;\r
- ///\r
- /// The number of entries in the variable portion of the table.\r
- ///\r
- UINT16 EntryCount;\r
- ///\r
- /// A modulo checksum of the entire table and the entries following this table.\r
- ///\r
- UINT8 CheckSum;\r
- ///\r
- /// Unused, must be zero.\r
- ///\r
- UINT8 Reserved[7];\r
- ///\r
- /// Version Number of the SAL_A firmware implementation in BCD format.\r
- ///\r
- UINT16 SalAVersion;\r
- ///\r
- /// Version Number of the SAL_B firmware implementation in BCD format.\r
- ///\r
- UINT16 SalBVersion;\r
- ///\r
- /// An ASCII identification string which uniquely identifies the manufacturer\r
- /// of the system hardware.\r
- ///\r
- UINT8 OemId[32];\r
- ///\r
- /// An ASCII identification string which uniquely identifies a family of\r
- /// compatible products from the manufacturer.\r
- ///\r
- UINT8 ProductId[32];\r
- ///\r
- /// Unused, must be zero.\r
- ///\r
- UINT8 Reserved2[8];\r
-} SAL_SYSTEM_TABLE_HEADER;\r
-\r
-#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
-#define EFI_SAL_REVISION 0x0320\r
-//\r
-// SAL System Types\r
-//\r
-#define EFI_SAL_ST_ENTRY_POINT 0\r
-#define EFI_SAL_ST_MEMORY_DESCRIPTOR 1\r
-#define EFI_SAL_ST_PLATFORM_FEATURES 2\r
-#define EFI_SAL_ST_TR_USAGE 3\r
-#define EFI_SAL_ST_PTC 4\r
-#define EFI_SAL_ST_AP_WAKEUP 5\r
-\r
-//\r
-// SAL System Type Sizes\r
-//\r
-#define EFI_SAL_ST_ENTRY_POINT_SIZE 48\r
-#define EFI_SAL_ST_MEMORY_DESCRIPTOR_SIZE 32\r
-#define EFI_SAL_ST_PLATFORM_FEATURES_SIZE 16\r
-#define EFI_SAL_ST_TR_USAGE_SIZE 32\r
-#define EFI_SAL_ST_PTC_SIZE 16\r
-#define EFI_SAL_ST_AP_WAKEUP_SIZE 16\r
-\r
-///\r
-/// Format of Entrypoint Descriptor Entry.\r
-///\r
-typedef struct {\r
- UINT8 Type; ///< Type here should be 0.\r
- UINT8 Reserved[7];\r
- UINT64 PalProcEntry;\r
- UINT64 SalProcEntry;\r
- UINT64 SalGlobalDataPointer;\r
- UINT64 Reserved2[2];\r
-} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
-\r
-///\r
-/// Format of Platform Features Descriptor Entry.\r
-///\r
-typedef struct {\r
- UINT8 Type; ///< Type here should be 2.\r
- UINT8 PlatformFeatures;\r
- UINT8 Reserved[14];\r
-} SAL_ST_PLATFORM_FEATURES;\r
-\r
-//\r
-// Value of Platform Feature List\r
-//\r
-#define SAL_PLAT_FEAT_BUS_LOCK 0x01\r
-#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
-#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
-\r
-///\r
-/// Format of Translation Register Descriptor Entry.\r
-///\r
-typedef struct {\r
- UINT8 Type; ///< Type here should be 3.\r
- UINT8 TRType;\r
- UINT8 TRNumber;\r
- UINT8 Reserved[5];\r
- UINT64 VirtualAddress;\r
- UINT64 EncodedPageSize;\r
- UINT64 Reserved1;\r
-} SAL_ST_TR_DECRIPTOR;\r
-\r
-//\r
-// Type of Translation Register\r
-//\r
-#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
-#define EFI_SAL_ST_TR_USAGE_DATA 01\r
-\r
-///\r
-/// Definition of Coherence Domain Information.\r
-///\r
-typedef struct {\r
- UINT64 NumberOfProcessors;\r
- UINT64 LocalIDRegister;\r
-} SAL_COHERENCE_DOMAIN_INFO;\r
-\r
-///\r
-/// Format of Purge Translation Cache Coherence Domain Entry.\r
-///\r
-typedef struct {\r
- UINT8 Type; ///< Type here should be 4.\r
- UINT8 Reserved[3];\r
- UINT32 NumberOfDomains;\r
- SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
-} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
-\r
-///\r
-/// Format of Application Processor Wake-Up Descriptor Entry.\r
-///\r
-typedef struct {\r
- UINT8 Type; ///< Type here should be 5.\r
- UINT8 WakeUpType;\r
- UINT8 Reserved[6];\r
- UINT64 ExternalInterruptVector;\r
-} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
-\r
-///\r
-/// Format of Firmware Interface Table (FIT) Entry.\r
-///\r
-typedef struct {\r
- UINT64 Address;\r
- UINT8 Size[3];\r
- UINT8 Reserved;\r
- UINT16 Revision;\r
- UINT8 Type : 7;\r
- UINT8 CheckSumValid : 1;\r
- UINT8 CheckSum;\r
-} EFI_SAL_FIT_ENTRY;\r
-//\r
-// FIT Types\r
-//\r
-#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
-#define EFI_SAL_FIT_PAL_B_TYPE 0x01\r
-//\r
-// Type from 0x02 to 0x0D is reserved.\r
-//\r
-#define EFI_SAL_FIT_PROCESSOR_SPECIFIC_PAL_A_TYPE 0x0E\r
-#define EFI_SAL_FIT_PAL_A_TYPE 0x0F\r
-//\r
-// OEM-defined type range is from 0x10 to 0x7E.\r
-// Here we defined the PEI_CORE type as 0x10\r
-//\r
-#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
-#define EFI_SAL_FIT_UNUSED_TYPE 0x7F\r
-\r
-//\r
-// FIT Entry\r
-//\r
-#define EFI_SAL_FIT_ENTRY_PTR (0x100000000 - 32) // 4GB - 24\r
-#define EFI_SAL_FIT_PALA_ENTRY (0x100000000 - 48) // 4GB - 32\r
-#define EFI_SAL_FIT_PALB_TYPE 01\r
-\r
-//\r
-// Following definitions are for Error Record Structure\r
-//\r
-\r
-///\r
-/// Format of TimeStamp field in Record Header.\r
-///\r
-typedef struct {\r
- UINT8 Seconds;\r
- UINT8 Minutes;\r
- UINT8 Hours;\r
- UINT8 Reserved;\r
- UINT8 Day;\r
- UINT8 Month;\r
- UINT8 Year;\r
- UINT8 Century;\r
-} SAL_TIME_STAMP;\r
-///\r
-/// Definition of Record Header.\r
-///\r
-typedef struct {\r
- UINT64 RecordId;\r
- UINT16 Revision;\r
- UINT8 ErrorSeverity;\r
- UINT8 ValidationBits;\r
- UINT32 RecordLength;\r
- SAL_TIME_STAMP TimeStamp;\r
- UINT8 OemPlatformId[16];\r
-} SAL_RECORD_HEADER;\r
-///\r
-/// Definition of Section Header.\r
-///\r
-typedef struct {\r
- GUID Guid;\r
- UINT16 Revision;\r
- UINT8 ErrorRecoveryInfo;\r
- UINT8 Reserved;\r
- UINT32 SectionLength;\r
-} SAL_SEC_HEADER;\r
-\r
-///\r
-/// GUID of Processor Machine Check Errors.\r
-///\r
-#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
- { \\r
- 0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
- }\r
-//\r
-// Bit masks for valid bits of MOD_ERROR_INFO\r
-//\r
-#define CHECK_INFO_VALID_BIT_MASK 0x1\r
-#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
-#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
-#define TARGER_ID_VALID_BIT_MASK 0x8\r
-#define PRECISE_IP_VALID_BIT_MASK 0x10\r
-///\r
-/// Definition of MOD_ERROR_INFO_STRUCT.\r
-///\r
-typedef struct {\r
- UINT64 InfoValid : 1;\r
- UINT64 ReqValid : 1;\r
- UINT64 RespValid : 1;\r
- UINT64 TargetValid : 1;\r
- UINT64 IpValid : 1;\r
- UINT64 Reserved : 59;\r
- UINT64 Info;\r
- UINT64 Req;\r
- UINT64 Resp;\r
- UINT64 Target;\r
- UINT64 Ip;\r
-} MOD_ERROR_INFO;\r
-///\r
-/// Definition of CPUID_INFO_STRUCT.\r
-///\r
-typedef struct {\r
- UINT8 CpuidInfo[40];\r
- UINT8 Reserved;\r
-} CPUID_INFO;\r
-\r
-typedef struct {\r
- UINT64 FrLow;\r
- UINT64 FrHigh;\r
-} FR_STRUCT;\r
-//\r
-// Bit masks for PSI_STATIC_STRUCT.ValidFieldBits\r
-//\r
-#define MIN_STATE_VALID_BIT_MASK 0x1\r
-#define BR_VALID_BIT_MASK 0x2\r
-#define CR_VALID_BIT_MASK 0x4\r
-#define AR_VALID_BIT_MASK 0x8\r
-#define RR_VALID_BIT_MASK 0x10\r
-#define FR_VALID_BIT_MASK 0x20\r
-///\r
-/// Definition of PSI_STATIC_STRUCT.\r
-///\r
-typedef struct {\r
- UINT64 ValidFieldBits;\r
- UINT8 MinStateInfo[1024];\r
- UINT64 Br[8];\r
- UINT64 Cr[128];\r
- UINT64 Ar[128];\r
- UINT64 Rr[8];\r
- FR_STRUCT Fr[128];\r
-} PSI_STATIC_STRUCT;\r
-//\r
-// Bit masks for SAL_PROCESSOR_ERROR_RECORD.ValidationBits\r
-//\r
-#define PROC_ERROR_MAP_VALID_BIT_MASK 0x1\r
-#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
-#define PROC_CR_LID_VALID_BIT_MASK 0x4\r
-#define PROC_STATIC_STRUCT_VALID_BIT_MASK 0x8\r
-#define CPU_INFO_VALID_BIT_MASK 0x1000000\r
-///\r
-/// Definition of Processor Machine Check Error Record.\r
-///\r
-typedef struct {\r
- SAL_SEC_HEADER SectionHeader;\r
- UINT64 ValidationBits;\r
- UINT64 ProcErrorMap;\r
- UINT64 ProcStateParameter;\r
- UINT64 ProcCrLid;\r
- MOD_ERROR_INFO CacheError[15];\r
- MOD_ERROR_INFO TlbError[15];\r
- MOD_ERROR_INFO BusError[15];\r
- MOD_ERROR_INFO RegFileCheck[15];\r
- MOD_ERROR_INFO MsCheck[15];\r
- CPUID_INFO CpuInfo;\r
- PSI_STATIC_STRUCT PsiValidData;\r
-} SAL_PROCESSOR_ERROR_RECORD;\r
-\r
-///\r
-/// GUID of Platform Memory Device Error Info.\r
-///\r
-#define SAL_MEMORY_ERROR_RECORD_INFO \\r
- { \\r
- 0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
- }\r
-//\r
-// Bit masks for SAL_MEMORY_ERROR_RECORD.ValidationBits\r
-//\r
-#define MEMORY_ERROR_STATUS_VALID_BIT_MASK 0x1\r
-#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK 0x2\r
-#define MEMORY_ADDR_BIT_MASK 0x4\r
-#define MEMORY_NODE_VALID_BIT_MASK 0x8\r
-#define MEMORY_CARD_VALID_BIT_MASK 0x10\r
-#define MEMORY_MODULE_VALID_BIT_MASK 0x20\r
-#define MEMORY_BANK_VALID_BIT_MASK 0x40\r
-#define MEMORY_DEVICE_VALID_BIT_MASK 0x80\r
-#define MEMORY_ROW_VALID_BIT_MASK 0x100\r
-#define MEMORY_COLUMN_VALID_BIT_MASK 0x200\r
-#define MEMORY_BIT_POSITION_VALID_BIT_MASK 0x400\r
-#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x800\r
-#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x1000\r
-#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK 0x2000\r
-#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK 0x4000\r
-#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK 0x8000\r
-#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x10000\r
-///\r
-/// Definition of Platform Memory Device Error Info Record.\r
-///\r
-typedef struct {\r
- SAL_SEC_HEADER SectionHeader;\r
- UINT64 ValidationBits;\r
- UINT64 MemErrorStatus;\r
- UINT64 MemPhysicalAddress;\r
- UINT64 MemPhysicalAddressMask;\r
- UINT16 MemNode;\r
- UINT16 MemCard;\r
- UINT16 MemModule;\r
- UINT16 MemBank;\r
- UINT16 MemDevice;\r
- UINT16 MemRow;\r
- UINT16 MemColumn;\r
- UINT16 MemBitPosition;\r
- UINT64 ModRequestorId;\r
- UINT64 ModResponderId;\r
- UINT64 ModTargetId;\r
- UINT64 BusSpecificData;\r
- UINT8 MemPlatformOemId[16];\r
-} SAL_MEMORY_ERROR_RECORD;\r
-\r
-///\r
-/// GUID of Platform PCI Bus Error Info.\r
-///\r
-#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
- { \\r
- 0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
- }\r
-//\r
-// Bit masks for SAL_PCI_BUS_ERROR_RECORD.ValidationBits\r
-//\r
-#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK 0x1\r
-#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK 0x2\r
-#define PCI_BUS_ID_VALID_BIT_MASK 0x4\r
-#define PCI_BUS_ADDRESS_VALID_BIT_MASK 0x8\r
-#define PCI_BUS_DATA_VALID_BIT_MASK 0x10\r
-#define PCI_BUS_CMD_VALID_BIT_MASK 0x20\r
-#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK 0x40\r
-#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK 0x80\r
-#define PCI_BUS_TARGET_VALID_BIT_MASK 0x100\r
-#define PCI_BUS_OEM_ID_VALID_BIT_MASK 0x200\r
-#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK 0x400\r
-\r
-///\r
-/// Designated PCI Bus identifier.\r
-///\r
-typedef struct {\r
- UINT8 BusNumber;\r
- UINT8 SegmentNumber;\r
-} PCI_BUS_ID;\r
-\r
-///\r
-/// Definition of Platform PCI Bus Error Info Record.\r
-///\r
-typedef struct {\r
- SAL_SEC_HEADER SectionHeader;\r
- UINT64 ValidationBits;\r
- UINT64 PciBusErrorStatus;\r
- UINT16 PciBusErrorType;\r
- PCI_BUS_ID PciBusId;\r
- UINT32 Reserved;\r
- UINT64 PciBusAddress;\r
- UINT64 PciBusData;\r
- UINT64 PciBusCommand;\r
- UINT64 PciBusRequestorId;\r
- UINT64 PciBusResponderId;\r
- UINT64 PciBusTargetId;\r
- UINT8 PciBusOemId[16];\r
-} SAL_PCI_BUS_ERROR_RECORD;\r
-\r
-///\r
-/// GUID of Platform PCI Component Error Info.\r
-///\r
-#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
- { \\r
- 0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
- }\r
-//\r
-// Bit masks for SAL_PCI_COMPONENT_ERROR_RECORD.ValidationBits\r
-//\r
-#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK 0x1\r
-#define PCI_COMP_INFO_VALID_BIT_MASK 0x2\r
-#define PCI_COMP_MEM_NUM_VALID_BIT_MASK 0x4\r
-#define PCI_COMP_IO_NUM_VALID_BIT_MASK 0x8\r
-#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK 0x10\r
-#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
-///\r
-/// Format of PCI Component Information to identify the device.\r
-///\r
-typedef struct {\r
- UINT16 VendorId;\r
- UINT16 DeviceId;\r
- UINT8 ClassCode[3];\r
- UINT8 FunctionNumber;\r
- UINT8 DeviceNumber;\r
- UINT8 BusNumber;\r
- UINT8 SegmentNumber;\r
- UINT8 Reserved[5];\r
-} PCI_COMP_INFO;\r
-///\r
-/// Definition of Platform PCI Component Error Info.\r
-///\r
-typedef struct {\r
- SAL_SEC_HEADER SectionHeader;\r
- UINT64 ValidationBits;\r
- UINT64 PciComponentErrorStatus;\r
- PCI_COMP_INFO PciComponentInfo;\r
- UINT32 PciComponentMemNum;\r
- UINT32 PciComponentIoNum;\r
- UINT8 PciBusOemId[16];\r
-} SAL_PCI_COMPONENT_ERROR_RECORD;\r
-\r
-///\r
-/// Platform SEL Device Error Info.\r
-///\r
-#define SAL_SEL_DEVICE_ERROR_RECORD_INFO \\r
- { \\r
- 0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
- }\r
-//\r
-// Bit masks for SAL_SEL_DEVICE_ERROR_RECORD.ValidationBits\r
-//\r
-#define SEL_RECORD_ID_VALID_BIT_MASK 0x1;\r
-#define SEL_RECORD_TYPE_VALID_BIT_MASK 0x2;\r
-#define SEL_GENERATOR_ID_VALID_BIT_MASK 0x4;\r
-#define SEL_EVM_REV_VALID_BIT_MASK 0x8;\r
-#define SEL_SENSOR_TYPE_VALID_BIT_MASK 0x10;\r
-#define SEL_SENSOR_NUM_VALID_BIT_MASK 0x20;\r
-#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
-#define SEL_EVENT_DATA1_VALID_BIT_MASK 0x80;\r
-#define SEL_EVENT_DATA2_VALID_BIT_MASK 0x100;\r
-#define SEL_EVENT_DATA3_VALID_BIT_MASK 0x200;\r
-///\r
-/// Definition of Platform SEL Device Error Info Record.\r
-///\r
-typedef struct {\r
- SAL_SEC_HEADER SectionHeader;\r
- UINT64 ValidationBits;\r
- UINT16 SelRecordId;\r
- UINT8 SelRecordType;\r
- UINT32 TimeStamp;\r
- UINT16 GeneratorId;\r
- UINT8 EvmRevision;\r
- UINT8 SensorType;\r
- UINT8 SensorNum;\r
- UINT8 EventDirType;\r
- UINT8 Data1;\r
- UINT8 Data2;\r
- UINT8 Data3;\r
-} SAL_SEL_DEVICE_ERROR_RECORD;\r
-\r
-///\r
-/// GUID of Platform SMBIOS Device Error Info.\r
-///\r
-#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
- { \\r
- 0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
- }\r
-//\r
-// Bit masks for SAL_SMBIOS_DEVICE_ERROR_RECORD.ValidationBits\r
-//\r
-#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK 0x1\r
-#define SMBIOS_LENGTH_VALID_BIT_MASK 0x2\r
-#define SMBIOS_TIME_STAMP_VALID_BIT_MASK 0x4\r
-#define SMBIOS_DATA_VALID_BIT_MASK 0x8\r
-///\r
-/// Definition of Platform SMBIOS Device Error Info Record.\r
-///\r
-typedef struct {\r
- SAL_SEC_HEADER SectionHeader;\r
- UINT64 ValidationBits;\r
- UINT8 SmbiosEventType;\r
- UINT8 SmbiosLength;\r
- UINT8 SmbiosBcdTimeStamp[6];\r
-} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
-\r
-///\r
-/// GUID of Platform Specific Error Info.\r
-///\r
-#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
- { \\r
- 0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
- }\r
-//\r
-// Bit masks for SAL_PLATFORM_SPECIFIC_ERROR_RECORD.ValidationBits\r
-//\r
-#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK 0x1\r
-#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK 0x2\r
-#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK 0x4\r
-#define PLATFORM_TARGET_VALID_BIT_MASK 0x8\r
-#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK 0x10\r
-#define PLATFORM_OEM_ID_VALID_BIT_MASK 0x20\r
-#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
-#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
-///\r
-/// Definition of Platform Specific Error Info Record.\r
-///\r
-typedef struct {\r
- SAL_SEC_HEADER SectionHeader;\r
- UINT64 ValidationBits;\r
- UINT64 PlatformErrorStatus;\r
- UINT64 PlatformRequestorId;\r
- UINT64 PlatformResponderId;\r
- UINT64 PlatformTargetId;\r
- UINT64 PlatformBusSpecificData;\r
- UINT8 OemComponentId[16];\r
-} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
-\r
-///\r
-/// Union of all the possible SAL Error Record Types.\r
-///\r
-typedef union {\r
- SAL_RECORD_HEADER *RecordHeader;\r
- SAL_PROCESSOR_ERROR_RECORD *SalProcessorRecord;\r
- SAL_PCI_BUS_ERROR_RECORD *SalPciBusRecord;\r
- SAL_PCI_COMPONENT_ERROR_RECORD *SalPciComponentRecord;\r
- SAL_SEL_DEVICE_ERROR_RECORD *ImpiRecord;\r
- SAL_SMBIOS_DEVICE_ERROR_RECORD *SmbiosRecord;\r
- SAL_PLATFORM_SPECIFIC_ERROR_RECORD *PlatformRecord;\r
- SAL_MEMORY_ERROR_RECORD *MemoryRecord;\r
- UINT8 *Raw;\r
-} SAL_ERROR_RECORDS_POINTERS;\r
-\r
-#pragma pack()\r
-\r
-#endif\r
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