PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf\r
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf\r
DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf\r
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf\r
\r
################################################################################\r
#\r
[Components.common]\r
OptionRomPkg/AtapiPassThruDxe/AtapiPassThruDxe.inf\r
OptionRomPkg/CirrusLogic5430Dxe/CirrusLogic5430Dxe.inf\r
+ OptionRomPkg/UndiRuntimeDxe/UndiRuntimeDxe.inf\r
\r
--- /dev/null
+/** @file\r
+ Provides the basic UNID functions.\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "Undi32.h"\r
+\r
+//\r
+// Global variables defined in this file\r
+//\r
+UNDI_CALL_TABLE api_table[PXE_OPCODE_LAST_VALID+1] = { \\r
+ {PXE_CPBSIZE_NOT_USED,PXE_DBSIZE_NOT_USED,0, (UINT16)(ANY_STATE),UNDI_GetState },\\r
+ {(UINT16)(DONT_CHECK),PXE_DBSIZE_NOT_USED,0,(UINT16)(ANY_STATE),UNDI_Start },\\r
+ {PXE_CPBSIZE_NOT_USED,PXE_DBSIZE_NOT_USED,0,MUST_BE_STARTED,UNDI_Stop },\\r
+ {PXE_CPBSIZE_NOT_USED,sizeof(PXE_DB_GET_INIT_INFO),0,MUST_BE_STARTED, UNDI_GetInitInfo },\\r
+ {PXE_CPBSIZE_NOT_USED,sizeof(PXE_DB_GET_CONFIG_INFO),0,MUST_BE_STARTED, UNDI_GetConfigInfo },\\r
+ {sizeof(PXE_CPB_INITIALIZE),(UINT16)(DONT_CHECK),(UINT16)(DONT_CHECK),MUST_BE_STARTED,UNDI_Initialize },\\r
+ {PXE_CPBSIZE_NOT_USED,PXE_DBSIZE_NOT_USED,(UINT16)(DONT_CHECK), MUST_BE_INITIALIZED,UNDI_Reset },\\r
+ {PXE_CPBSIZE_NOT_USED,PXE_DBSIZE_NOT_USED,0, MUST_BE_INITIALIZED,UNDI_Shutdown },\\r
+ {PXE_CPBSIZE_NOT_USED,PXE_DBSIZE_NOT_USED,(UINT16)(DONT_CHECK), MUST_BE_INITIALIZED,UNDI_Interrupt },\\r
+ {(UINT16)(DONT_CHECK),(UINT16)(DONT_CHECK),(UINT16)(DONT_CHECK), MUST_BE_INITIALIZED, UNDI_RecFilter },\\r
+ {(UINT16)(DONT_CHECK),(UINT16)(DONT_CHECK),(UINT16)(DONT_CHECK), MUST_BE_INITIALIZED, UNDI_StnAddr },\\r
+ {PXE_CPBSIZE_NOT_USED, (UINT16)(DONT_CHECK), (UINT16)(DONT_CHECK), MUST_BE_INITIALIZED, UNDI_Statistics },\\r
+ {sizeof(PXE_CPB_MCAST_IP_TO_MAC),sizeof(PXE_DB_MCAST_IP_TO_MAC), (UINT16)(DONT_CHECK),MUST_BE_INITIALIZED, UNDI_ip2mac },\\r
+ {(UINT16)(DONT_CHECK),(UINT16)(DONT_CHECK),(UINT16)(DONT_CHECK), MUST_BE_INITIALIZED, UNDI_NVData },\\r
+ {PXE_CPBSIZE_NOT_USED,(UINT16)(DONT_CHECK),(UINT16)(DONT_CHECK), MUST_BE_INITIALIZED, UNDI_Status },\\r
+ {(UINT16)(DONT_CHECK),PXE_DBSIZE_NOT_USED,(UINT16)(DONT_CHECK), MUST_BE_INITIALIZED, UNDI_FillHeader },\\r
+ {(UINT16)(DONT_CHECK),PXE_DBSIZE_NOT_USED,(UINT16)(DONT_CHECK), MUST_BE_INITIALIZED, UNDI_Transmit },\\r
+ {sizeof(PXE_CPB_RECEIVE),sizeof(PXE_DB_RECEIVE),0,MUST_BE_INITIALIZED, UNDI_Receive } \\r
+};\r
+\r
+//\r
+// end of global variables\r
+//\r
+\r
+\r
+/**\r
+ This routine determines the operational state of the UNDI. It updates the state flags in the\r
+ Command Descriptor Block based on information derived from the AdapterInfo instance data.\r
+ To ensure the command has completed successfully, CdbPtr->StatCode will contain the result of\r
+ the command execution.\r
+ The CdbPtr->StatFlags will contain a STOPPED, STARTED, or INITIALIZED state once the command\r
+ has successfully completed.\r
+ Keep in mind the AdapterInfo->State is the active state of the adapter (based on software\r
+ interrogation), and the CdbPtr->StateFlags is the passed back information that is reflected\r
+ to the caller of the UNDI API.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_GetState (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ CdbPtr->StatFlags = (PXE_STATFLAGS) (CdbPtr->StatFlags | AdapterInfo->State);\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to change the operational state of the UNDI from stopped to started.\r
+ It will do this as long as the adapter's state is PXE_STATFLAGS_GET_STATE_STOPPED, otherwise\r
+ the CdbPtr->StatFlags will reflect a command failure, and the CdbPtr->StatCode will reflect the\r
+ UNDI as having already been started.\r
+ This routine is modified to reflect the undi 1.1 specification changes. The\r
+ changes in the spec are mainly in the callback routines, the new spec adds\r
+ 3 more callbacks and a unique id.\r
+ Since this UNDI supports both old and new undi specifications,\r
+ The NIC's data structure is filled in with the callback routines (depending\r
+ on the version) pointed to in the caller's CpbPtr. This seeds the Delay,\r
+ Virt2Phys, Block, and Mem_IO for old and new versions and Map_Mem, UnMap_Mem\r
+ and Sync_Mem routines and a unique id variable for the new version.\r
+ This is the function which an external entity (SNP, O/S, etc) would call\r
+ to provide it's I/O abstraction to the UNDI.\r
+ It's final action is to change the AdapterInfo->State to PXE_STATFLAGS_GET_STATE_STARTED.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Start (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ PXE_CPB_START_30 *CpbPtr;\r
+ PXE_CPB_START_31 *CpbPtr_31;\r
+\r
+ //\r
+ // check if it is already started.\r
+ //\r
+ if (AdapterInfo->State != PXE_STATFLAGS_GET_STATE_STOPPED) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_ALREADY_STARTED;\r
+ return ;\r
+ }\r
+\r
+ if (CdbPtr->CPBsize != sizeof(PXE_CPB_START_30) &&\r
+ CdbPtr->CPBsize != sizeof(PXE_CPB_START_31)) {\r
+\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ CpbPtr = (PXE_CPB_START_30 *) (UINTN) (CdbPtr->CPBaddr);\r
+ CpbPtr_31 = (PXE_CPB_START_31 *) (UINTN) (CdbPtr->CPBaddr);\r
+\r
+ if (AdapterInfo->VersionFlag == 0x30) {\r
+ AdapterInfo->Delay_30 = (bsptr_30) (UINTN) CpbPtr->Delay;\r
+ AdapterInfo->Virt2Phys_30 = (virtphys_30) (UINTN) CpbPtr->Virt2Phys;\r
+ AdapterInfo->Block_30 = (block_30) (UINTN) CpbPtr->Block;\r
+ //\r
+ // patch for old buggy 3.0 code:\r
+ // In EFI1.0 undi used to provide the full (absolute) I/O address to the\r
+ // i/o calls and SNP used to provide a callback that used GlobalIoFncs and\r
+ // everything worked fine! In EFI 1.1, UNDI is not using the full\r
+ // i/o or memory address to access the device, The base values for the i/o\r
+ // and memory address is abstracted by the device specific PciIoFncs and\r
+ // UNDI only uses the offset values. Since UNDI3.0 cannot provide any\r
+ // identification to SNP, SNP cannot use nic specific PciIoFncs callback!\r
+ //\r
+ // To fix this and make undi3.0 work with SNP in EFI1.1 we\r
+ // use a TmpMemIo function that is defined in init.c\r
+ // This breaks the runtime driver feature of undi, but what to do\r
+ // if we have to provide the 3.0 compatibility (including the 3.0 bugs)\r
+ //\r
+ // This TmpMemIo function also takes a UniqueId parameter\r
+ // (as in undi3.1 design) and so initialize the UniqueId as well here\r
+ // Note: AdapterInfo->Mem_Io_30 is just filled for consistency with other\r
+ // parameters but never used, we only use Mem_Io field in the In/Out routines\r
+ // inside e100b.c.\r
+ //\r
+ AdapterInfo->Mem_Io_30 = (mem_io_30) (UINTN) CpbPtr->Mem_IO;\r
+ AdapterInfo->Mem_Io = (mem_io) (UINTN) TmpMemIo;\r
+ AdapterInfo->Unique_ID = (UINT64) (UINTN) AdapterInfo;\r
+\r
+ } else {\r
+ AdapterInfo->Delay = (bsptr) (UINTN) CpbPtr_31->Delay;\r
+ AdapterInfo->Virt2Phys = (virtphys) (UINTN) CpbPtr_31->Virt2Phys;\r
+ AdapterInfo->Block = (block) (UINTN) CpbPtr_31->Block;\r
+ AdapterInfo->Mem_Io = (mem_io) (UINTN) CpbPtr_31->Mem_IO;\r
+\r
+ AdapterInfo->Map_Mem = (map_mem) (UINTN) CpbPtr_31->Map_Mem;\r
+ AdapterInfo->UnMap_Mem = (unmap_mem) (UINTN) CpbPtr_31->UnMap_Mem;\r
+ AdapterInfo->Sync_Mem = (sync_mem) (UINTN) CpbPtr_31->Sync_Mem;\r
+ AdapterInfo->Unique_ID = CpbPtr_31->Unique_ID;\r
+ }\r
+\r
+ AdapterInfo->State = PXE_STATFLAGS_GET_STATE_STARTED;\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to change the operational state of the UNDI from started to stopped.\r
+ It will not do this if the adapter's state is PXE_STATFLAGS_GET_STATE_INITIALIZED, otherwise\r
+ the CdbPtr->StatFlags will reflect a command failure, and the CdbPtr->StatCode will reflect the\r
+ UNDI as having already not been shut down.\r
+ The NIC's data structure will have the Delay, Virt2Phys, and Block, pointers zero'd out..\r
+ It's final action is to change the AdapterInfo->State to PXE_STATFLAGS_GET_STATE_STOPPED.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Stop (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ if (AdapterInfo->State == PXE_STATFLAGS_GET_STATE_INITIALIZED) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_NOT_SHUTDOWN;\r
+ return ;\r
+ }\r
+\r
+ AdapterInfo->Delay_30 = 0;\r
+ AdapterInfo->Virt2Phys_30 = 0;\r
+ AdapterInfo->Block_30 = 0;\r
+\r
+ AdapterInfo->Delay = 0;\r
+ AdapterInfo->Virt2Phys = 0;\r
+ AdapterInfo->Block = 0;\r
+\r
+ AdapterInfo->Map_Mem = 0;\r
+ AdapterInfo->UnMap_Mem = 0;\r
+ AdapterInfo->Sync_Mem = 0;\r
+\r
+ AdapterInfo->State = PXE_STATFLAGS_GET_STATE_STOPPED;\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to retrieve the initialization information that is needed by drivers and\r
+ applications to initialize the UNDI. This will fill in data in the Data Block structure that is\r
+ pointed to by the caller's CdbPtr->DBaddr. The fields filled in are as follows:\r
+ MemoryRequired, FrameDataLen, LinkSpeeds[0-3], NvCount, NvWidth, MediaHeaderLen, HWaddrLen,\r
+ MCastFilterCnt, TxBufCnt, TxBufSize, RxBufCnt, RxBufSize, IFtype, Duplex, and LoopBack.\r
+ In addition, the CdbPtr->StatFlags ORs in that this NIC supports cable detection. (APRIORI knowledge)\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_GetInitInfo (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ PXE_DB_GET_INIT_INFO *DbPtr;\r
+\r
+ DbPtr = (PXE_DB_GET_INIT_INFO *) (UINTN) (CdbPtr->DBaddr);\r
+\r
+ DbPtr->MemoryRequired = MEMORY_NEEDED;\r
+ DbPtr->FrameDataLen = PXE_MAX_TXRX_UNIT_ETHER;\r
+ DbPtr->LinkSpeeds[0] = 10;\r
+ DbPtr->LinkSpeeds[1] = 100;\r
+ DbPtr->LinkSpeeds[2] = DbPtr->LinkSpeeds[3] = 0;\r
+ DbPtr->NvCount = MAX_EEPROM_LEN;\r
+ DbPtr->NvWidth = 4;\r
+ DbPtr->MediaHeaderLen = PXE_MAC_HEADER_LEN_ETHER;\r
+ DbPtr->HWaddrLen = PXE_HWADDR_LEN_ETHER;\r
+ DbPtr->MCastFilterCnt = MAX_MCAST_ADDRESS_CNT;\r
+\r
+ DbPtr->TxBufCnt = TX_BUFFER_COUNT;\r
+ DbPtr->TxBufSize = sizeof (TxCB);\r
+ DbPtr->RxBufCnt = RX_BUFFER_COUNT;\r
+ DbPtr->RxBufSize = sizeof (RxFD);\r
+\r
+ DbPtr->IFtype = PXE_IFTYPE_ETHERNET;\r
+ DbPtr->SupportedDuplexModes = PXE_DUPLEX_ENABLE_FULL_SUPPORTED |\r
+ PXE_DUPLEX_FORCE_FULL_SUPPORTED;\r
+ DbPtr->SupportedLoopBackModes = PXE_LOOPBACK_INTERNAL_SUPPORTED |\r
+ PXE_LOOPBACK_EXTERNAL_SUPPORTED;\r
+\r
+ CdbPtr->StatFlags |= PXE_STATFLAGS_CABLE_DETECT_SUPPORTED;\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to retrieve the configuration information about the NIC being controlled by\r
+ this driver. This will fill in data in the Data Block structure that is pointed to by the caller's CdbPtr->DBaddr.\r
+ The fields filled in are as follows:\r
+ DbPtr->pci.BusType, DbPtr->pci.Bus, DbPtr->pci.Device, and DbPtr->pci.\r
+ In addition, the DbPtr->pci.Config.Dword[0-63] grabs a copy of this NIC's PCI configuration space.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_GetConfigInfo (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT16 Index;\r
+ PXE_DB_GET_CONFIG_INFO *DbPtr;\r
+\r
+ DbPtr = (PXE_DB_GET_CONFIG_INFO *) (UINTN) (CdbPtr->DBaddr);\r
+\r
+ DbPtr->pci.BusType = PXE_BUSTYPE_PCI;\r
+ DbPtr->pci.Bus = AdapterInfo->Bus;\r
+ DbPtr->pci.Device = AdapterInfo->Device;\r
+ DbPtr->pci.Function = AdapterInfo->Function;\r
+\r
+ for (Index = 0; Index < MAX_PCI_CONFIG_LEN; Index++) {\r
+ DbPtr->pci.Config.Dword[Index] = AdapterInfo->Config[Index];\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine resets the network adapter and initializes the UNDI using the parameters supplied in\r
+ the CPB. This command must be issued before the network adapter can be setup to transmit and\r
+ receive packets.\r
+ Once the memory requirements of the UNDI are obtained by using the GetInitInfo command, a block\r
+ of non-swappable memory may need to be allocated. The address of this memory must be passed to\r
+ UNDI during the Initialize in the CPB. This memory is used primarily for transmit and receive buffers.\r
+ The fields CableDetect, LinkSpeed, Duplex, LoopBack, MemoryPtr, and MemoryLength are set with information\r
+ that was passed in the CPB and the NIC is initialized.\r
+ If the NIC initialization fails, the CdbPtr->StatFlags are updated with PXE_STATFLAGS_COMMAND_FAILED\r
+ Otherwise, AdapterInfo->State is updated with PXE_STATFLAGS_GET_STATE_INITIALIZED showing the state of\r
+ the UNDI is now initialized.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Initialize (\r
+ IN PXE_CDB *CdbPtr,\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ PXE_CPB_INITIALIZE *CpbPtr;\r
+\r
+ if ((CdbPtr->OpFlags != PXE_OPFLAGS_INITIALIZE_DETECT_CABLE) &&\r
+ (CdbPtr->OpFlags != PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE)) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // check if it is already initialized\r
+ //\r
+ if (AdapterInfo->State == PXE_STATFLAGS_GET_STATE_INITIALIZED) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_ALREADY_INITIALIZED;\r
+ return ;\r
+ }\r
+\r
+ CpbPtr = (PXE_CPB_INITIALIZE *) (UINTN) CdbPtr->CPBaddr;\r
+\r
+ if (CpbPtr->MemoryLength < (UINT32) MEMORY_NEEDED) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CPB;\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // default behaviour is to detect the cable, if the 3rd param is 1,\r
+ // do not do that\r
+ //\r
+ AdapterInfo->CableDetect = (UINT8) ((CdbPtr->OpFlags == (UINT16) PXE_OPFLAGS_INITIALIZE_DO_NOT_DETECT_CABLE) ? (UINT8) 0 : (UINT8) 1);\r
+ AdapterInfo->LinkSpeedReq = (UINT16) CpbPtr->LinkSpeed;\r
+ AdapterInfo->DuplexReq = CpbPtr->DuplexMode;\r
+ AdapterInfo->LoopBack = CpbPtr->LoopBackMode;\r
+ AdapterInfo->MemoryPtr = CpbPtr->MemoryAddr;\r
+ AdapterInfo->MemoryLength = CpbPtr->MemoryLength;\r
+\r
+ CdbPtr->StatCode = (PXE_STATCODE) E100bInit (AdapterInfo);\r
+\r
+ if (CdbPtr->StatCode != PXE_STATCODE_SUCCESS) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ } else {\r
+ AdapterInfo->State = PXE_STATFLAGS_GET_STATE_INITIALIZED;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine resets the network adapter and initializes the UNDI using the parameters supplied in\r
+ the CPB. The transmit and receive queues are emptied and any pending interrupts are cleared.\r
+ If the NIC reset fails, the CdbPtr->StatFlags are updated with PXE_STATFLAGS_COMMAND_FAILED\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Reset (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ if (CdbPtr->OpFlags != PXE_OPFLAGS_NOT_USED &&\r
+ CdbPtr->OpFlags != PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS &&\r
+ CdbPtr->OpFlags != PXE_OPFLAGS_RESET_DISABLE_FILTERS ) {\r
+\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ CdbPtr->StatCode = (UINT16) E100bReset (AdapterInfo, CdbPtr->OpFlags);\r
+\r
+ if (CdbPtr->StatCode != PXE_STATCODE_SUCCESS) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ This routine resets the network adapter and leaves it in a safe state for another driver to\r
+ initialize. Any pending transmits or receives are lost. Receive filters and external\r
+ interrupt enables are disabled. Once the UNDI has been shutdown, it can then be stopped\r
+ or initialized again.\r
+ If the NIC reset fails, the CdbPtr->StatFlags are updated with PXE_STATFLAGS_COMMAND_FAILED\r
+ Otherwise, AdapterInfo->State is updated with PXE_STATFLAGS_GET_STATE_STARTED showing the state of\r
+ the NIC as being started.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Shutdown (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ //\r
+ // do the shutdown stuff here\r
+ //\r
+ CdbPtr->StatCode = (UINT16) E100bShutdown (AdapterInfo);\r
+\r
+ if (CdbPtr->StatCode != PXE_STATCODE_SUCCESS) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ } else {\r
+ AdapterInfo->State = PXE_STATFLAGS_GET_STATE_STARTED;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine can be used to read and/or change the current external interrupt enable\r
+ settings. Disabling an external interrupt enable prevents and external (hardware)\r
+ interrupt from being signaled by the network device. Internally the interrupt events\r
+ can still be polled by using the UNDI_GetState command.\r
+ The resulting information on the interrupt state will be passed back in the CdbPtr->StatFlags.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Interrupt (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT8 IntMask;\r
+\r
+ IntMask = (UINT8)(UINTN)(CdbPtr->OpFlags & (PXE_OPFLAGS_INTERRUPT_RECEIVE |\r
+ PXE_OPFLAGS_INTERRUPT_TRANSMIT |\r
+ PXE_OPFLAGS_INTERRUPT_COMMAND |\r
+ PXE_OPFLAGS_INTERRUPT_SOFTWARE));\r
+\r
+ switch (CdbPtr->OpFlags & PXE_OPFLAGS_INTERRUPT_OPMASK) {\r
+ case PXE_OPFLAGS_INTERRUPT_READ:\r
+ break;\r
+\r
+ case PXE_OPFLAGS_INTERRUPT_ENABLE:\r
+ if (IntMask == 0) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ AdapterInfo->int_mask = IntMask;\r
+ E100bSetInterruptState (AdapterInfo);\r
+ break;\r
+\r
+ case PXE_OPFLAGS_INTERRUPT_DISABLE:\r
+ if (IntMask != 0) {\r
+ AdapterInfo->int_mask = (UINT16) (AdapterInfo->int_mask & ~(IntMask));\r
+ E100bSetInterruptState (AdapterInfo);\r
+ break;\r
+ }\r
+\r
+ //\r
+ // else fall thru.\r
+ //\r
+ default:\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ if ((AdapterInfo->int_mask & PXE_OPFLAGS_INTERRUPT_RECEIVE) != 0) {\r
+ CdbPtr->StatFlags |= PXE_STATFLAGS_INTERRUPT_RECEIVE;\r
+\r
+ }\r
+\r
+ if ((AdapterInfo->int_mask & PXE_OPFLAGS_INTERRUPT_TRANSMIT) != 0) {\r
+ CdbPtr->StatFlags |= PXE_STATFLAGS_INTERRUPT_TRANSMIT;\r
+\r
+ }\r
+\r
+ if ((AdapterInfo->int_mask & PXE_OPFLAGS_INTERRUPT_COMMAND) != 0) {\r
+ CdbPtr->StatFlags |= PXE_STATFLAGS_INTERRUPT_COMMAND;\r
+\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to read and change receive filters and, if supported, read\r
+ and change multicast MAC address filter list.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_RecFilter (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT16 NewFilter;\r
+ UINT16 OpFlags;\r
+ PXE_DB_RECEIVE_FILTERS *DbPtr;\r
+ UINT8 *MacAddr;\r
+ UINTN MacCount;\r
+ UINT16 Index;\r
+ UINT16 copy_len;\r
+ UINT8 *ptr1;\r
+ UINT8 *ptr2;\r
+ OpFlags = CdbPtr->OpFlags;\r
+ NewFilter = (UINT16) (OpFlags & 0x1F);\r
+\r
+ switch (OpFlags & PXE_OPFLAGS_RECEIVE_FILTER_OPMASK) {\r
+ case PXE_OPFLAGS_RECEIVE_FILTER_READ:\r
+\r
+ //\r
+ // not expecting a cpb, not expecting any filter bits\r
+ //\r
+ if ((NewFilter != 0) || (CdbPtr->CPBsize != 0)) {\r
+ goto BadCdb;\r
+\r
+ }\r
+\r
+ if ((NewFilter & PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST) == 0) {\r
+ goto JustRead;\r
+\r
+ }\r
+\r
+ NewFilter = (UINT16) (NewFilter | AdapterInfo->Rx_Filter);\r
+ //\r
+ // all other flags are ignored except mcast_reset\r
+ //\r
+ break;\r
+\r
+ case PXE_OPFLAGS_RECEIVE_FILTER_ENABLE:\r
+ //\r
+ // there should be atleast one other filter bit set.\r
+ //\r
+ if (NewFilter == 0) {\r
+ //\r
+ // nothing to enable\r
+ //\r
+ goto BadCdb;\r
+ }\r
+\r
+ if (CdbPtr->CPBsize != 0) {\r
+ //\r
+ // this must be a multicast address list!\r
+ // don't accept the list unless selective_mcast is set\r
+ // don't accept confusing mcast settings with this\r
+ //\r
+ if (((NewFilter & PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST) == 0) ||\r
+ ((NewFilter & PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST) != 0) ||\r
+ ((NewFilter & PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST) != 0) ||\r
+ ((CdbPtr->CPBsize % sizeof (PXE_MAC_ADDR)) != 0) ) {\r
+ goto BadCdb;\r
+ }\r
+\r
+ MacAddr = (UINT8 *) ((UINTN) (CdbPtr->CPBaddr));\r
+ MacCount = CdbPtr->CPBsize / sizeof (PXE_MAC_ADDR);\r
+\r
+ for (; MacCount-- != 0; MacAddr += sizeof (PXE_MAC_ADDR)) {\r
+ if (MacAddr[0] != 0x01 || MacAddr[1] != 0x00 || MacAddr[2] != 0x5E || (MacAddr[3] & 0x80) != 0) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CPB;\r
+ return ;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // check selective mcast case enable case\r
+ //\r
+ if ((OpFlags & PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST) != 0) {\r
+ if (((OpFlags & PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST) != 0) ||\r
+ ((OpFlags & PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST) != 0) ) {\r
+ goto BadCdb;\r
+\r
+ }\r
+ //\r
+ // if no cpb, make sure we have an old list\r
+ //\r
+ if ((CdbPtr->CPBsize == 0) && (AdapterInfo->mcast_list.list_len == 0)) {\r
+ goto BadCdb;\r
+ }\r
+ }\r
+ //\r
+ // if you want to enable anything, you got to have unicast\r
+ // and you have what you already enabled!\r
+ //\r
+ NewFilter = (UINT16) (NewFilter | (PXE_OPFLAGS_RECEIVE_FILTER_UNICAST | AdapterInfo->Rx_Filter));\r
+\r
+ break;\r
+\r
+ case PXE_OPFLAGS_RECEIVE_FILTER_DISABLE:\r
+\r
+ //\r
+ // mcast list not expected, i.e. no cpb here!\r
+ //\r
+ if (CdbPtr->CPBsize != PXE_CPBSIZE_NOT_USED) {\r
+ goto BadCdb;\r
+ }\r
+\r
+ NewFilter = (UINT16) ((~(CdbPtr->OpFlags & 0x1F)) & AdapterInfo->Rx_Filter);\r
+\r
+ break;\r
+\r
+ default:\r
+ goto BadCdb;\r
+ }\r
+\r
+ if ((OpFlags & PXE_OPFLAGS_RECEIVE_FILTER_RESET_MCAST_LIST) != 0) {\r
+ AdapterInfo->mcast_list.list_len = 0;\r
+ NewFilter &= (~PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST);\r
+ }\r
+\r
+ E100bSetfilter (AdapterInfo, NewFilter, CdbPtr->CPBaddr, CdbPtr->CPBsize);\r
+\r
+JustRead:\r
+ //\r
+ // give the current mcast list\r
+ //\r
+ if ((CdbPtr->DBsize != 0) && (AdapterInfo->mcast_list.list_len != 0)) {\r
+ //\r
+ // copy the mc list to db\r
+ //\r
+\r
+ DbPtr = (PXE_DB_RECEIVE_FILTERS *) (UINTN) CdbPtr->DBaddr;\r
+ ptr1 = (UINT8 *) (&DbPtr->MCastList[0]);\r
+\r
+ //\r
+ // DbPtr->mc_count = AdapterInfo->mcast_list.list_len;\r
+ //\r
+ copy_len = (UINT16) (AdapterInfo->mcast_list.list_len * PXE_MAC_LENGTH);\r
+\r
+ if (copy_len > CdbPtr->DBsize) {\r
+ copy_len = CdbPtr->DBsize;\r
+\r
+ }\r
+\r
+ ptr2 = (UINT8 *) (&AdapterInfo->mcast_list.mc_list[0]);\r
+ for (Index = 0; Index < copy_len; Index++) {\r
+ ptr1[Index] = ptr2[Index];\r
+ }\r
+ }\r
+ //\r
+ // give the stat flags here\r
+ //\r
+ if (AdapterInfo->Receive_Started) {\r
+ CdbPtr->StatFlags = (PXE_STATFLAGS) (CdbPtr->StatFlags | AdapterInfo->Rx_Filter);\r
+\r
+ }\r
+\r
+ return ;\r
+\r
+BadCdb:\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to get the current station and broadcast MAC addresses, and to change the\r
+ current station MAC address.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_StnAddr (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ PXE_CPB_STATION_ADDRESS *CpbPtr;\r
+ PXE_DB_STATION_ADDRESS *DbPtr;\r
+ UINT16 Index;\r
+\r
+ if (CdbPtr->OpFlags == PXE_OPFLAGS_STATION_ADDRESS_RESET) {\r
+ //\r
+ // configure the permanent address.\r
+ // change the AdapterInfo->CurrentNodeAddress field.\r
+ //\r
+ if (CompareMem (\r
+ &AdapterInfo->CurrentNodeAddress[0],\r
+ &AdapterInfo->PermNodeAddress[0],\r
+ PXE_MAC_LENGTH\r
+ ) != 0) {\r
+ for (Index = 0; Index < PXE_MAC_LENGTH; Index++) {\r
+ AdapterInfo->CurrentNodeAddress[Index] = AdapterInfo->PermNodeAddress[Index];\r
+ }\r
+\r
+ E100bSetupIAAddr (AdapterInfo);\r
+ }\r
+ }\r
+\r
+ if (CdbPtr->CPBaddr != (UINT64) 0) {\r
+ CpbPtr = (PXE_CPB_STATION_ADDRESS *) (UINTN) (CdbPtr->CPBaddr);\r
+ //\r
+ // configure the new address\r
+ //\r
+ for (Index = 0; Index < PXE_MAC_LENGTH; Index++) {\r
+ AdapterInfo->CurrentNodeAddress[Index] = CpbPtr->StationAddr[Index];\r
+ }\r
+\r
+ E100bSetupIAAddr (AdapterInfo);\r
+ }\r
+\r
+ if (CdbPtr->DBaddr != (UINT64) 0) {\r
+ DbPtr = (PXE_DB_STATION_ADDRESS *) (UINTN) (CdbPtr->DBaddr);\r
+ //\r
+ // fill it with the new values\r
+ //\r
+ for (Index = 0; Index < PXE_MAC_LENGTH; Index++) {\r
+ DbPtr->StationAddr[Index] = AdapterInfo->CurrentNodeAddress[Index];\r
+ DbPtr->BroadcastAddr[Index] = AdapterInfo->BroadcastNodeAddress[Index];\r
+ DbPtr->PermanentAddr[Index] = AdapterInfo->PermNodeAddress[Index];\r
+ }\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to read and clear the NIC traffic statistics. This command is supported only\r
+ if the !PXE structure's Implementation flags say so.\r
+ Results will be parsed out in the following manner:\r
+ CdbPtr->DBaddr.Data[0] R Total Frames (Including frames with errors and dropped frames)\r
+ CdbPtr->DBaddr.Data[1] R Good Frames (All frames copied into receive buffer)\r
+ CdbPtr->DBaddr.Data[2] R Undersize Frames (Frames below minimum length for media <64 for ethernet)\r
+ CdbPtr->DBaddr.Data[4] R Dropped Frames (Frames that were dropped because receive buffers were full)\r
+ CdbPtr->DBaddr.Data[8] R CRC Error Frames (Frames with alignment or CRC errors)\r
+ CdbPtr->DBaddr.Data[A] T Total Frames (Including frames with errors and dropped frames)\r
+ CdbPtr->DBaddr.Data[B] T Good Frames (All frames copied into transmit buffer)\r
+ CdbPtr->DBaddr.Data[C] T Undersize Frames (Frames below minimum length for media <64 for ethernet)\r
+ CdbPtr->DBaddr.Data[E] T Dropped Frames (Frames that were dropped because of collisions)\r
+ CdbPtr->DBaddr.Data[14] T Total Collision Frames (Total collisions on this subnet)\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Statistics (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ if ((CdbPtr->OpFlags &~(PXE_OPFLAGS_STATISTICS_RESET)) != 0) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ if ((CdbPtr->OpFlags & PXE_OPFLAGS_STATISTICS_RESET) != 0) {\r
+ //\r
+ // Reset the statistics\r
+ //\r
+ CdbPtr->StatCode = (UINT16) E100bStatistics (AdapterInfo, 0, 0);\r
+ } else {\r
+ CdbPtr->StatCode = (UINT16) E100bStatistics (AdapterInfo, CdbPtr->DBaddr, CdbPtr->DBsize);\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to translate a multicast IP address to a multicast MAC address.\r
+ This results in a MAC address composed of 25 bits of fixed data with the upper 23 bits of the IP\r
+ address being appended to it. Results passed back in the equivalent of CdbPtr->DBaddr->MAC[0-5].\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_ip2mac (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ PXE_CPB_MCAST_IP_TO_MAC *CpbPtr;\r
+ PXE_DB_MCAST_IP_TO_MAC *DbPtr;\r
+ UINT8 *TmpPtr;\r
+\r
+ CpbPtr = (PXE_CPB_MCAST_IP_TO_MAC *) (UINTN) CdbPtr->CPBaddr;\r
+ DbPtr = (PXE_DB_MCAST_IP_TO_MAC *) (UINTN) CdbPtr->DBaddr;\r
+\r
+ if ((CdbPtr->OpFlags & PXE_OPFLAGS_MCAST_IPV6_TO_MAC) != 0) {\r
+ //\r
+ // for now this is not supported\r
+ //\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_UNSUPPORTED;\r
+ return ;\r
+ }\r
+\r
+ TmpPtr = (UINT8 *) (&CpbPtr->IP.IPv4);\r
+ //\r
+ // check if the ip given is a mcast IP\r
+ //\r
+ if ((TmpPtr[0] & 0xF0) != 0xE0) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CPB;\r
+ }\r
+ //\r
+ // take the last 23 bits in IP.\r
+ // be very careful. accessing word on a non-word boundary will hang motherboard codenamed Big Sur\r
+ // casting the mac array (in the middle) to a UINT32 pointer and accessing\r
+ // the UINT32 content hung the system...\r
+ //\r
+ DbPtr->MAC[0] = 0x01;\r
+ DbPtr->MAC[1] = 0x00;\r
+ DbPtr->MAC[2] = 0x5e;\r
+ DbPtr->MAC[3] = (UINT8) (TmpPtr[1] & 0x7f);\r
+ DbPtr->MAC[4] = (UINT8) TmpPtr[2];\r
+ DbPtr->MAC[5] = (UINT8) TmpPtr[3];\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to read and write non-volatile storage on the NIC (if supported). The NVRAM\r
+ could be EEPROM, FLASH, or battery backed RAM.\r
+ This is an optional function according to the UNDI specification (or will be......)\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_NVData (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ PXE_DB_NVDATA *DbPtr;\r
+ UINT16 Index;\r
+\r
+ if ((CdbPtr->OpFlags == PXE_OPFLAGS_NVDATA_READ) != 0) {\r
+\r
+ if ((CdbPtr->DBsize == PXE_DBSIZE_NOT_USED) != 0) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ DbPtr = (PXE_DB_NVDATA *) (UINTN) CdbPtr->DBaddr;\r
+\r
+ for (Index = 0; Index < MAX_PCI_CONFIG_LEN; Index++) {\r
+ DbPtr->Data.Dword[Index] = AdapterInfo->NVData[Index];\r
+\r
+ }\r
+\r
+ } else {\r
+ //\r
+ // no write for now\r
+ //\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_UNSUPPORTED;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine returns the current interrupt status and/or the transmitted buffer addresses.\r
+ If the current interrupt status is returned, pending interrupts will be acknowledged by this\r
+ command. Transmitted buffer addresses that are written to the DB are removed from the transmit\r
+ buffer queue.\r
+ Normally, this command would be polled with interrupts disabled.\r
+ The transmit buffers are returned in CdbPtr->DBaddr->TxBufer[0 - NumEntries].\r
+ The interrupt status is returned in CdbPtr->StatFlags.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Status (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ PXE_DB_GET_STATUS *DbPtr;\r
+ PXE_DB_GET_STATUS TmpGetStatus;\r
+ UINT16 Index;\r
+ UINT16 Status;\r
+ UINT16 NumEntries;\r
+ RxFD *RxPtr;\r
+\r
+ //\r
+ // Fill in temporary GetStatus storage.\r
+ //\r
+ RxPtr = &AdapterInfo->rx_ring[AdapterInfo->cur_rx_ind];\r
+\r
+ if ((RxPtr->cb_header.status & RX_COMPLETE) != 0) {\r
+ TmpGetStatus.RxFrameLen = RxPtr->ActualCount & 0x3fff;\r
+ } else {\r
+ TmpGetStatus.RxFrameLen = 0;\r
+ }\r
+\r
+ TmpGetStatus.reserved = 0;\r
+\r
+ //\r
+ // Fill in size of next available receive packet and\r
+ // reserved field in caller's DB storage.\r
+ //\r
+ DbPtr = (PXE_DB_GET_STATUS *) (UINTN) CdbPtr->DBaddr;\r
+\r
+ if (CdbPtr->DBsize > 0 && CdbPtr->DBsize < sizeof (UINT32) * 2) {\r
+ CopyMem (DbPtr, &TmpGetStatus, CdbPtr->DBsize);\r
+ } else {\r
+ CopyMem (DbPtr, &TmpGetStatus, sizeof (UINT32) * 2);\r
+ }\r
+\r
+ //\r
+ //\r
+ //\r
+ if ((CdbPtr->OpFlags & PXE_OPFLAGS_GET_TRANSMITTED_BUFFERS) != 0) {\r
+ //\r
+ // DBsize of zero is invalid if Tx buffers are requested.\r
+ //\r
+ if (CdbPtr->DBsize == 0) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // remember this b4 we overwrite\r
+ //\r
+ NumEntries = (UINT16) (CdbPtr->DBsize - sizeof (UINT64));\r
+\r
+ //\r
+ // We already filled in 2 UINT32s.\r
+ //\r
+ CdbPtr->DBsize = sizeof (UINT32) * 2;\r
+\r
+ //\r
+ // will claim any hanging free CBs\r
+ //\r
+ CheckCBList (AdapterInfo);\r
+\r
+ if (AdapterInfo->xmit_done_head == AdapterInfo->xmit_done_tail) {\r
+ CdbPtr->StatFlags |= PXE_STATFLAGS_GET_STATUS_TXBUF_QUEUE_EMPTY;\r
+ } else {\r
+ for (Index = 0; NumEntries >= sizeof (UINT64); Index++, NumEntries -= sizeof (UINT64)) {\r
+ if (AdapterInfo->xmit_done_head != AdapterInfo->xmit_done_tail) {\r
+ DbPtr->TxBuffer[Index] = AdapterInfo->xmit_done[AdapterInfo->xmit_done_head];\r
+ AdapterInfo->xmit_done_head = next (AdapterInfo->xmit_done_head);\r
+ CdbPtr->DBsize += sizeof (UINT64);\r
+ } else {\r
+ break;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (AdapterInfo->xmit_done_head != AdapterInfo->xmit_done_tail) {\r
+ CdbPtr->StatFlags |= PXE_STATFLAGS_DB_WRITE_TRUNCATED;\r
+\r
+ }\r
+ //\r
+ // check for a receive buffer and give it's size in db\r
+ //\r
+ }\r
+ //\r
+ //\r
+ //\r
+ if ((CdbPtr->OpFlags & PXE_OPFLAGS_GET_INTERRUPT_STATUS) != 0) {\r
+\r
+ Status = InWord (AdapterInfo, AdapterInfo->ioaddr + SCBStatus);\r
+ AdapterInfo->Int_Status = (UINT16) (AdapterInfo->Int_Status | Status);\r
+\r
+ //\r
+ // acknoledge the interrupts\r
+ //\r
+ OutWord (AdapterInfo, (UINT16) (Status & 0xfc00), (UINT32) (AdapterInfo->ioaddr + SCBStatus));\r
+\r
+ //\r
+ // report all the outstanding interrupts\r
+ //\r
+ Status = AdapterInfo->Int_Status;\r
+ if ((Status & SCB_STATUS_FR) != 0) {\r
+ CdbPtr->StatFlags |= PXE_STATFLAGS_GET_STATUS_RECEIVE;\r
+ }\r
+\r
+ if ((Status & SCB_STATUS_SWI) != 0) {\r
+ CdbPtr->StatFlags |= PXE_STATFLAGS_GET_STATUS_SOFTWARE;\r
+ }\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to fill media header(s) in transmit packet(s).\r
+ Copies the MAC address into the media header whether it is dealing\r
+ with fragmented or non-fragmented packets.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_FillHeader (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ PXE_CPB_FILL_HEADER *Cpb;\r
+ PXE_CPB_FILL_HEADER_FRAGMENTED *Cpbf;\r
+ EtherHeader *MacHeader;\r
+ UINTN Index;\r
+\r
+ if (CdbPtr->CPBsize == PXE_CPBSIZE_NOT_USED) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ if ((CdbPtr->OpFlags & PXE_OPFLAGS_FILL_HEADER_FRAGMENTED) != 0) {\r
+ Cpbf = (PXE_CPB_FILL_HEADER_FRAGMENTED *) (UINTN) CdbPtr->CPBaddr;\r
+\r
+ //\r
+ // assume 1st fragment is big enough for the mac header\r
+ //\r
+ if ((Cpbf->FragCnt == 0) || (Cpbf->FragDesc[0].FragLen < PXE_MAC_HEADER_LEN_ETHER)) {\r
+ //\r
+ // no buffers given\r
+ //\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ MacHeader = (EtherHeader *) (UINTN) Cpbf->FragDesc[0].FragAddr;\r
+ //\r
+ // we don't swap the protocol bytes\r
+ //\r
+ MacHeader->type = Cpbf->Protocol;\r
+\r
+ for (Index = 0; Index < PXE_HWADDR_LEN_ETHER; Index++) {\r
+ MacHeader->dest_addr[Index] = Cpbf->DestAddr[Index];\r
+ MacHeader->src_addr[Index] = Cpbf->SrcAddr[Index];\r
+ }\r
+ } else {\r
+ Cpb = (PXE_CPB_FILL_HEADER *) (UINTN) CdbPtr->CPBaddr;\r
+\r
+ MacHeader = (EtherHeader *) (UINTN) Cpb->MediaHeader;\r
+ //\r
+ // we don't swap the protocol bytes\r
+ //\r
+ MacHeader->type = Cpb->Protocol;\r
+\r
+ for (Index = 0; Index < PXE_HWADDR_LEN_ETHER; Index++) {\r
+ MacHeader->dest_addr[Index] = Cpb->DestAddr[Index];\r
+ MacHeader->src_addr[Index] = Cpb->SrcAddr[Index];\r
+ }\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine is used to place a packet into the transmit queue. The data buffers given to\r
+ this command are to be considered locked and the application or network driver loses\r
+ ownership of these buffers and must not free or relocate them until the ownership returns.\r
+ When the packets are transmitted, a transmit complete interrupt is generated (if interrupts\r
+ are disabled, the transmit interrupt status is still set and can be checked using the UNDI_Status\r
+ command.\r
+ Some implementations and adapters support transmitting multiple packets with one transmit\r
+ command. If this feature is supported, the transmit CPBs can be linked in one transmit\r
+ command.\r
+ All UNDIs support fragmented frames, now all network devices or protocols do. If a fragmented\r
+ frame CPB is given to UNDI and the network device does not support fragmented frames\r
+ (see !PXE.Implementation flag), the UNDI will have to copy the fragments into a local buffer\r
+ before transmitting.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Transmit (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+\r
+ if (CdbPtr->CPBsize == PXE_CPBSIZE_NOT_USED) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ CdbPtr->StatCode = (PXE_STATCODE) E100bTransmit (AdapterInfo, CdbPtr->CPBaddr, CdbPtr->OpFlags);\r
+\r
+ if (CdbPtr->StatCode != PXE_STATCODE_SUCCESS) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ When the network adapter has received a frame, this command is used to copy the frame\r
+ into the driver/application storage location. Once a frame has been copied, it is\r
+ removed from the receive queue.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+UNDI_Receive (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+\r
+ //\r
+ // check if RU has started...\r
+ //\r
+ if (!AdapterInfo->Receive_Started) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_NOT_INITIALIZED;\r
+ return ;\r
+ }\r
+\r
+\r
+ CdbPtr->StatCode = (UINT16) E100bReceive (AdapterInfo, CdbPtr->CPBaddr, CdbPtr->DBaddr);\r
+ if (CdbPtr->StatCode != PXE_STATCODE_SUCCESS) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+\r
+/**\r
+ This is the main SW UNDI API entry using the newer nii protocol.\r
+ The parameter passed in is a 64 bit flat model virtual\r
+ address of the cdb. We then jump into the common routine for both old and\r
+ new nii protocol entries.\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+// TODO: cdb - add argument and description to function comment\r
+VOID\r
+UNDI_APIEntry_new (\r
+ IN UINT64 cdb\r
+ )\r
+{\r
+ PXE_CDB *CdbPtr;\r
+ NIC_DATA_INSTANCE *AdapterInfo;\r
+\r
+ if (cdb == (UINT64) 0) {\r
+ return ;\r
+\r
+ }\r
+\r
+ CdbPtr = (PXE_CDB *) (UINTN) cdb;\r
+\r
+ if (CdbPtr->IFnum >= pxe_31->IFcnt) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+ }\r
+\r
+ AdapterInfo = &(UNDI32DeviceList[CdbPtr->IFnum]->NicInfo);\r
+ //\r
+ // entering from older entry point\r
+ //\r
+ AdapterInfo->VersionFlag = 0x31;\r
+ UNDI_APIEntry_Common (cdb);\r
+}\r
+\r
+\r
+/**\r
+ This is the common routine for both old and new entry point procedures.\r
+ The parameter passed in is a 64 bit flat model virtual\r
+ address of the cdb. We then jump into the service routine pointed to by the\r
+ Api_Table[OpCode].\r
+\r
+ @param CdbPtr Pointer to the command descriptor block.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+// TODO: cdb - add argument and description to function comment\r
+VOID\r
+UNDI_APIEntry_Common (\r
+ IN UINT64 cdb\r
+ )\r
+{\r
+ PXE_CDB *CdbPtr;\r
+ NIC_DATA_INSTANCE *AdapterInfo;\r
+ UNDI_CALL_TABLE *tab_ptr;\r
+\r
+ CdbPtr = (PXE_CDB *) (UINTN) cdb;\r
+\r
+ //\r
+ // check the OPCODE range\r
+ //\r
+ if ((CdbPtr->OpCode > PXE_OPCODE_LAST_VALID) ||\r
+ (CdbPtr->StatCode != PXE_STATCODE_INITIALIZE) ||\r
+ (CdbPtr->StatFlags != PXE_STATFLAGS_INITIALIZE) ||\r
+ (CdbPtr->IFnum >= pxe_31->IFcnt) ) {\r
+ goto badcdb;\r
+\r
+ }\r
+\r
+ if (CdbPtr->CPBsize == PXE_CPBSIZE_NOT_USED) {\r
+ if (CdbPtr->CPBaddr != PXE_CPBADDR_NOT_USED) {\r
+ goto badcdb;\r
+ }\r
+ } else if (CdbPtr->CPBaddr == PXE_CPBADDR_NOT_USED) {\r
+ goto badcdb;\r
+ }\r
+\r
+ if (CdbPtr->DBsize == PXE_DBSIZE_NOT_USED) {\r
+ if (CdbPtr->DBaddr != PXE_DBADDR_NOT_USED) {\r
+ goto badcdb;\r
+ }\r
+ } else if (CdbPtr->DBaddr == PXE_DBADDR_NOT_USED) {\r
+ goto badcdb;\r
+ }\r
+\r
+ //\r
+ // check if cpbsize and dbsize are as needed\r
+ // check if opflags are as expected\r
+ //\r
+ tab_ptr = &api_table[CdbPtr->OpCode];\r
+\r
+ if (tab_ptr->cpbsize != (UINT16) (DONT_CHECK) && tab_ptr->cpbsize != CdbPtr->CPBsize) {\r
+ goto badcdb;\r
+ }\r
+\r
+ if (tab_ptr->dbsize != (UINT16) (DONT_CHECK) && tab_ptr->dbsize != CdbPtr->DBsize) {\r
+ goto badcdb;\r
+ }\r
+\r
+ if (tab_ptr->opflags != (UINT16) (DONT_CHECK) && tab_ptr->opflags != CdbPtr->OpFlags) {\r
+ goto badcdb;\r
+\r
+ }\r
+\r
+ AdapterInfo = &(UNDI32DeviceList[CdbPtr->IFnum]->NicInfo);\r
+\r
+ //\r
+ // check if UNDI_State is valid for this call\r
+ //\r
+ if (tab_ptr->state != (UINT16) (-1)) {\r
+ //\r
+ // should atleast be started\r
+ //\r
+ if (AdapterInfo->State == PXE_STATFLAGS_GET_STATE_STOPPED) {\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_NOT_STARTED;\r
+ return ;\r
+ }\r
+ //\r
+ // check if it should be initialized\r
+ //\r
+ if (tab_ptr->state == 2) {\r
+ if (AdapterInfo->State != PXE_STATFLAGS_GET_STATE_INITIALIZED) {\r
+ CdbPtr->StatCode = PXE_STATCODE_NOT_INITIALIZED;\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ return ;\r
+ }\r
+ }\r
+ }\r
+ //\r
+ // set the return variable for success case here\r
+ //\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_COMPLETE;\r
+ CdbPtr->StatCode = PXE_STATCODE_SUCCESS;\r
+\r
+ tab_ptr->api_ptr (CdbPtr, AdapterInfo);\r
+ return ;\r
+ //\r
+ // %% AVL - check for command linking\r
+ //\r
+badcdb:\r
+ CdbPtr->StatFlags = PXE_STATFLAGS_COMMAND_FAILED;\r
+ CdbPtr->StatCode = PXE_STATCODE_INVALID_CDB;\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ When called with a null NicPtr, this routine decrements the number of NICs\r
+ this UNDI is supporting and removes the NIC_DATA_POINTER from the array.\r
+ Otherwise, it increments the number of NICs this UNDI is supported and\r
+ updates the pxe.Fudge to ensure a proper check sum results.\r
+\r
+ @param NicPtr Pointer to the NIC data structure.\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+PxeUpdate (\r
+ IN NIC_DATA_INSTANCE *NicPtr,\r
+ IN PXE_SW_UNDI *PxePtr\r
+ )\r
+{\r
+ if (NicPtr == NULL) {\r
+ if (PxePtr->IFcnt > 0) {\r
+ //\r
+ // number of NICs this undi supports\r
+ //\r
+ PxePtr->IFcnt--;\r
+ }\r
+\r
+ PxePtr->Fudge = (UINT8) (PxePtr->Fudge - CalculateSum8 ((VOID *) PxePtr, PxePtr->Len));\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // number of NICs this undi supports\r
+ //\r
+ PxePtr->IFcnt++;\r
+ PxePtr->Fudge = (UINT8) (PxePtr->Fudge - CalculateSum8 ((VOID *) PxePtr, PxePtr->Len));\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ Initialize the !PXE structure\r
+\r
+ @param PxePtr Pointer to SW_UNDI data structure.\r
+\r
+ @retval EFI_SUCCESS This driver is added to Controller.\r
+ @retval other This driver does not support this device.\r
+\r
+**/\r
+VOID\r
+PxeStructInit (\r
+ IN PXE_SW_UNDI *PxePtr\r
+ )\r
+{\r
+ //\r
+ // Initialize the !PXE structure\r
+ //\r
+ PxePtr->Signature = PXE_ROMID_SIGNATURE;\r
+ PxePtr->Len = sizeof (PXE_SW_UNDI);\r
+ //\r
+ // cksum\r
+ //\r
+ PxePtr->Fudge = 0;\r
+ //\r
+ // number of NICs this undi supports\r
+ //\r
+ PxePtr->IFcnt = 0;\r
+ PxePtr->Rev = PXE_ROMID_REV;\r
+ PxePtr->MajorVer = PXE_ROMID_MAJORVER;\r
+ PxePtr->MinorVer = PXE_ROMID_MINORVER;\r
+ PxePtr->reserved1 = 0;\r
+\r
+ PxePtr->Implementation = PXE_ROMID_IMP_SW_VIRT_ADDR |\r
+ PXE_ROMID_IMP_FRAG_SUPPORTED |\r
+ PXE_ROMID_IMP_CMD_LINK_SUPPORTED |\r
+ PXE_ROMID_IMP_NVDATA_READ_ONLY |\r
+ PXE_ROMID_IMP_STATION_ADDR_SETTABLE |\r
+ PXE_ROMID_IMP_PROMISCUOUS_MULTICAST_RX_SUPPORTED |\r
+ PXE_ROMID_IMP_PROMISCUOUS_RX_SUPPORTED |\r
+ PXE_ROMID_IMP_BROADCAST_RX_SUPPORTED |\r
+ PXE_ROMID_IMP_FILTERED_MULTICAST_RX_SUPPORTED |\r
+ PXE_ROMID_IMP_SOFTWARE_INT_SUPPORTED |\r
+ PXE_ROMID_IMP_PACKET_RX_INT_SUPPORTED;\r
+\r
+ PxePtr->EntryPoint = (UINT64) (UINTN) UNDI_APIEntry_new;\r
+ PxePtr->MinorVer = PXE_ROMID_MINORVER_31;\r
+\r
+ PxePtr->reserved2[0] = 0;\r
+ PxePtr->reserved2[1] = 0;\r
+ PxePtr->reserved2[2] = 0;\r
+ PxePtr->BusCnt = 1;\r
+ PxePtr->BusType[0] = PXE_BUSTYPE_PCI;\r
+\r
+ PxePtr->Fudge = (UINT8) (PxePtr->Fudge - CalculateSum8 ((VOID *) PxePtr, PxePtr->Len));\r
+}\r
+\r
--- /dev/null
+/** @file\r
+ Provides basic function upon network adapter card.\r
+\r
+Copyright (c) 2006, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "Undi32.h"\r
+\r
+UINT8 basic_config_cmd[22] = {\r
+ 22, 0x08,\r
+ 0, 0,\r
+ 0, (UINT8)0x80,\r
+ 0x32, 0x03,\r
+ 1, 0,\r
+ 0x2E, 0,\r
+ 0x60, 0,\r
+ (UINT8)0xf2, 0x48,\r
+ 0, 0x40,\r
+ (UINT8)0xf2, (UINT8)0x80, // 0x40=Force full-duplex\r
+ 0x3f, 0x05,\r
+};\r
+\r
+//\r
+// How to wait for the command unit to accept a command.\r
+// Typically this takes 0 ticks.\r
+//\r
+#define wait_for_cmd_done(cmd_ioaddr) \\r
+{ \\r
+ INT16 wait_count = 2000; \\r
+ while ((InByte (AdapterInfo, cmd_ioaddr) != 0) && --wait_count >= 0) \\r
+ DelayIt (AdapterInfo, 10); \\r
+ if (wait_count == 0) \\r
+ DelayIt (AdapterInfo, 50); \\r
+}\r
+\r
+\r
+/**\r
+ This function calls the MemIo callback to read a byte from the device's\r
+ address space\r
+ Since UNDI3.0 uses the TmpMemIo function (instead of the callback routine)\r
+ which also takes the UniqueId parameter (as in UNDI3.1 spec) we don't have\r
+ to make undi3.0 a special case\r
+\r
+ @param Port Which port to read from.\r
+\r
+ @retval Results The data read from the port.\r
+\r
+**/\r
+// TODO: AdapterInfo - add argument and description to function comment\r
+UINT8\r
+InByte (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT32 Port\r
+ )\r
+{\r
+ UINT8 Results;\r
+\r
+ (*AdapterInfo->Mem_Io) (\r
+ AdapterInfo->Unique_ID,\r
+ PXE_MEM_READ,\r
+ 1,\r
+ (UINT64)Port,\r
+ (UINT64) (UINTN) &Results\r
+ );\r
+ return Results;\r
+}\r
+\r
+\r
+/**\r
+ This function calls the MemIo callback to read a word from the device's\r
+ address space\r
+ Since UNDI3.0 uses the TmpMemIo function (instead of the callback routine)\r
+ which also takes the UniqueId parameter (as in UNDI3.1 spec) we don't have\r
+ to make undi3.0 a special case\r
+\r
+ @param Port Which port to read from.\r
+\r
+ @retval Results The data read from the port.\r
+\r
+**/\r
+// TODO: AdapterInfo - add argument and description to function comment\r
+UINT16\r
+InWord (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT32 Port\r
+ )\r
+{\r
+ UINT16 Results;\r
+\r
+ (*AdapterInfo->Mem_Io) (\r
+ AdapterInfo->Unique_ID,\r
+ PXE_MEM_READ,\r
+ 2,\r
+ (UINT64)Port,\r
+ (UINT64)(UINTN)&Results\r
+ );\r
+ return Results;\r
+}\r
+\r
+\r
+/**\r
+ This function calls the MemIo callback to read a dword from the device's\r
+ address space\r
+ Since UNDI3.0 uses the TmpMemIo function (instead of the callback routine)\r
+ which also takes the UniqueId parameter (as in UNDI3.1 spec) we don't have\r
+ to make undi3.0 a special case\r
+\r
+ @param Port Which port to read from.\r
+\r
+ @retval Results The data read from the port.\r
+\r
+**/\r
+// TODO: AdapterInfo - add argument and description to function comment\r
+UINT32\r
+InLong (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT32 Port\r
+ )\r
+{\r
+ UINT32 Results;\r
+\r
+ (*AdapterInfo->Mem_Io) (\r
+ AdapterInfo->Unique_ID,\r
+ PXE_MEM_READ,\r
+ 4,\r
+ (UINT64)Port,\r
+ (UINT64)(UINTN)&Results\r
+ );\r
+ return Results;\r
+}\r
+\r
+\r
+/**\r
+ This function calls the MemIo callback to write a byte from the device's\r
+ address space\r
+ Since UNDI3.0 uses the TmpMemIo function (instead of the callback routine)\r
+ which also takes the UniqueId parameter (as in UNDI3.1 spec) we don't have\r
+ to make undi3.0 a special case\r
+\r
+ @param Data Data to write to Port.\r
+ @param Port Which port to write to.\r
+\r
+ @return none\r
+\r
+**/\r
+// TODO: AdapterInfo - add argument and description to function comment\r
+VOID\r
+OutByte (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT8 Data,\r
+ IN UINT32 Port\r
+ )\r
+{\r
+ UINT8 Val;\r
+\r
+ Val = Data;\r
+ (*AdapterInfo->Mem_Io) (\r
+ AdapterInfo->Unique_ID,\r
+ PXE_MEM_WRITE,\r
+ 1,\r
+ (UINT64)Port,\r
+ (UINT64)(UINTN)(UINTN)&Val\r
+ );\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This function calls the MemIo callback to write a word from the device's\r
+ address space\r
+ Since UNDI3.0 uses the TmpMemIo function (instead of the callback routine)\r
+ which also takes the UniqueId parameter (as in UNDI3.1 spec) we don't have\r
+ to make undi3.0 a special case\r
+\r
+ @param Data Data to write to Port.\r
+ @param Port Which port to write to.\r
+\r
+ @return none\r
+\r
+**/\r
+// TODO: AdapterInfo - add argument and description to function comment\r
+VOID\r
+OutWord (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT16 Data,\r
+ IN UINT32 Port\r
+ )\r
+{\r
+ UINT16 Val;\r
+\r
+ Val = Data;\r
+ (*AdapterInfo->Mem_Io) (\r
+ AdapterInfo->Unique_ID,\r
+ PXE_MEM_WRITE,\r
+ 2,\r
+ (UINT64)Port,\r
+ (UINT64)(UINTN)&Val\r
+ );\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This function calls the MemIo callback to write a dword from the device's\r
+ address space\r
+ Since UNDI3.0 uses the TmpMemIo function (instead of the callback routine)\r
+ which also takes the UniqueId parameter (as in UNDI3.1 spec) we don't have\r
+ to make undi3.0 a special case\r
+\r
+ @param Data Data to write to Port.\r
+ @param Port Which port to write to.\r
+\r
+ @return none\r
+\r
+**/\r
+// TODO: AdapterInfo - add argument and description to function comment\r
+VOID\r
+OutLong (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT32 Data,\r
+ IN UINT32 Port\r
+ )\r
+{\r
+ UINT32 Val;\r
+\r
+ Val = Data;\r
+ (*AdapterInfo->Mem_Io) (\r
+ AdapterInfo->Unique_ID,\r
+ PXE_MEM_WRITE,\r
+ 4,\r
+ (UINT64)Port,\r
+ (UINT64)(UINTN)&Val\r
+ );\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+ @param MemAddr TODO: add argument description\r
+ @param Size TODO: add argument description\r
+ @param Direction TODO: add argument description\r
+ @param MappedAddr TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINTN\r
+MapIt (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT64 MemAddr,\r
+ IN UINT32 Size,\r
+ IN UINT32 Direction,\r
+ OUT UINT64 MappedAddr\r
+ )\r
+{\r
+ UINT64 *PhyAddr;\r
+\r
+ PhyAddr = (UINT64 *) (UINTN) MappedAddr;\r
+ //\r
+ // mapping is different for theold and new NII protocols\r
+ //\r
+ if (AdapterInfo->VersionFlag == 0x30) {\r
+ if (AdapterInfo->Virt2Phys_30 == (VOID *) NULL) {\r
+ *PhyAddr = (UINT64) AdapterInfo->MemoryPtr;\r
+ } else {\r
+ (*AdapterInfo->Virt2Phys_30) (MemAddr, (UINT64) (UINTN) PhyAddr);\r
+ }\r
+\r
+ if (*PhyAddr > FOUR_GIGABYTE) {\r
+ return PXE_STATCODE_INVALID_PARAMETER;\r
+ }\r
+ } else {\r
+ if (AdapterInfo->Map_Mem == (VOID *) NULL) {\r
+ //\r
+ // this UNDI cannot handle addresses beyond 4 GB without a map routine\r
+ //\r
+ if (MemAddr > FOUR_GIGABYTE) {\r
+ return PXE_STATCODE_INVALID_PARAMETER;\r
+ } else {\r
+ *PhyAddr = MemAddr;\r
+ }\r
+ } else {\r
+ (*AdapterInfo->Map_Mem) (\r
+ AdapterInfo->Unique_ID,\r
+ MemAddr,\r
+ Size,\r
+ Direction,\r
+ MappedAddr\r
+ );\r
+ }\r
+ }\r
+\r
+ return PXE_STATCODE_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+ @param MemAddr TODO: add argument description\r
+ @param Size TODO: add argument description\r
+ @param Direction TODO: add argument description\r
+ @param MappedAddr TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+VOID\r
+UnMapIt (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT64 MemAddr,\r
+ IN UINT32 Size,\r
+ IN UINT32 Direction,\r
+ IN UINT64 MappedAddr\r
+ )\r
+{\r
+ if (AdapterInfo->VersionFlag > 0x30) {\r
+ //\r
+ // no mapping service\r
+ //\r
+ if (AdapterInfo->UnMap_Mem != (VOID *) NULL) {\r
+ (*AdapterInfo->UnMap_Mem) (\r
+ AdapterInfo->Unique_ID,\r
+ MemAddr,\r
+ Size,\r
+ Direction,\r
+ MappedAddr\r
+ );\r
+\r
+ }\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+\r
+\r
+**/\r
+// TODO: MicroSeconds - add argument and description to function comment\r
+VOID\r
+DelayIt (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ UINT16 MicroSeconds\r
+ )\r
+{\r
+ if (AdapterInfo->VersionFlag == 0x30) {\r
+ (*AdapterInfo->Delay_30) (MicroSeconds);\r
+ } else {\r
+ (*AdapterInfo->Delay) (AdapterInfo->Unique_ID, MicroSeconds);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+\r
+\r
+**/\r
+// TODO: flag - add argument and description to function comment\r
+VOID\r
+BlockIt (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ UINT32 flag\r
+ )\r
+{\r
+ if (AdapterInfo->VersionFlag == 0x30) {\r
+ (*AdapterInfo->Block_30) (flag);\r
+ } else {\r
+ (*AdapterInfo->Block) (AdapterInfo->Unique_ID, flag);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT8\r
+Load_Base_Regs (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ //\r
+ // we will use the linear (flat) memory model and fill our base registers\r
+ // with 0's so that the entire physical address is our offset\r
+ //\r
+ //\r
+ // we reset the statistics totals here because this is where we are loading stats addr\r
+ //\r
+ AdapterInfo->RxTotals = 0;\r
+ AdapterInfo->TxTotals = 0;\r
+\r
+ //\r
+ // Load the statistics block address.\r
+ //\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+ OutLong (AdapterInfo, (UINT32) AdapterInfo->stat_phy_addr, AdapterInfo->ioaddr + SCBPointer);\r
+ OutByte (AdapterInfo, CU_STATSADDR, AdapterInfo->ioaddr + SCBCmd);\r
+ AdapterInfo->statistics->done_marker = 0;\r
+\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+ OutLong (AdapterInfo, 0, AdapterInfo->ioaddr + SCBPointer);\r
+ OutByte (AdapterInfo, RX_ADDR_LOAD, AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+ OutLong (AdapterInfo, 0, AdapterInfo->ioaddr + SCBPointer);\r
+ OutByte (AdapterInfo, CU_CMD_BASE, AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+ @param cmd_ptr TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT8\r
+IssueCB (\r
+ NIC_DATA_INSTANCE *AdapterInfo,\r
+ TxCB *cmd_ptr\r
+ )\r
+{\r
+ UINT16 status;\r
+\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ //\r
+ // read the CU status, if it is idle, write the address of cb_ptr\r
+ // in the scbpointer and issue a cu_start,\r
+ // if it is suspended, remove the suspend bit in the previous command\r
+ // block and issue a resume\r
+ //\r
+ // Ensure that the CU Active Status bit is not on from previous CBs.\r
+ //\r
+ status = InWord (AdapterInfo, AdapterInfo->ioaddr + SCBStatus);\r
+\r
+ //\r
+ // Skip acknowledging the interrupt if it is not already set\r
+ //\r
+\r
+ //\r
+ // ack only the cna the integer\r
+ //\r
+ if ((status & SCB_STATUS_CNA) != 0) {\r
+ OutWord (AdapterInfo, SCB_STATUS_CNA, AdapterInfo->ioaddr + SCBStatus);\r
+\r
+ }\r
+\r
+ if ((status & SCB_STATUS_CU_MASK) == SCB_STATUS_CU_IDLE) {\r
+ //\r
+ // give a cu_start\r
+ //\r
+ OutLong (AdapterInfo, cmd_ptr->PhysTCBAddress, AdapterInfo->ioaddr + SCBPointer);\r
+ OutByte (AdapterInfo, CU_START, AdapterInfo->ioaddr + SCBCmd);\r
+ } else {\r
+ //\r
+ // either active or suspended, give a resume\r
+ //\r
+\r
+ cmd_ptr->PrevTCBVirtualLinkPtr->cb_header.command &= ~(CmdSuspend | CmdIntr);\r
+ OutByte (AdapterInfo, CU_RESUME, AdapterInfo->ioaddr + SCBCmd);\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT8\r
+Configure (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ //\r
+ // all command blocks are of TxCB format\r
+ //\r
+ TxCB *cmd_ptr;\r
+ UINT8 *data_ptr;\r
+ volatile INT16 Index;\r
+ UINT8 my_filter;\r
+\r
+ cmd_ptr = GetFreeCB (AdapterInfo);\r
+ data_ptr = (UINT8 *) (&cmd_ptr->PhysTBDArrayAddres);\r
+\r
+ //\r
+ // start the config data right after the command header\r
+ //\r
+ for (Index = 0; Index < sizeof (basic_config_cmd); Index++) {\r
+ data_ptr[Index] = basic_config_cmd[Index];\r
+ }\r
+\r
+ my_filter = (UINT8) ((AdapterInfo->Rx_Filter & PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS) ? 1 : 0);\r
+ my_filter = (UINT8) (my_filter | ((AdapterInfo->Rx_Filter & PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST) ? 0 : 2));\r
+\r
+ data_ptr[15] = (UINT8) (data_ptr[15] | my_filter);\r
+ data_ptr[19] = (UINT8) (AdapterInfo->Duplex ? 0xC0 : 0x80);\r
+ data_ptr[21] = (UINT8) ((AdapterInfo->Rx_Filter & PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST) ? 0x0D : 0x05);\r
+\r
+ //\r
+ // check if we have to use the AUI port instead\r
+ //\r
+ if ((AdapterInfo->PhyRecord[0] & 0x8000) != 0) {\r
+ data_ptr[15] |= 0x80;\r
+ data_ptr[8] = 0;\r
+ }\r
+\r
+ BlockIt (AdapterInfo, TRUE);\r
+ cmd_ptr->cb_header.command = CmdSuspend | CmdConfigure;\r
+\r
+ IssueCB (AdapterInfo, cmd_ptr);\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ BlockIt (AdapterInfo, FALSE);\r
+\r
+ CommandWaitForCompletion (cmd_ptr, AdapterInfo);\r
+\r
+ //\r
+ // restore the cb values for tx\r
+ //\r
+ cmd_ptr->PhysTBDArrayAddres = cmd_ptr->PhysArrayAddr;\r
+ cmd_ptr->ByteCount = cmd_ptr->Threshold = cmd_ptr->TBDCount = 0;\r
+ //\r
+ // fields beyond the immediatedata are assumed to be safe\r
+ // add the CB to the free list again\r
+ //\r
+ SetFreeCB (AdapterInfo, cmd_ptr);\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT8\r
+E100bSetupIAAddr (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ //\r
+ // all command blocks are of TxCB format\r
+ //\r
+ TxCB *cmd_ptr;\r
+ UINT16 *data_ptr;\r
+ UINT16 *eaddrs;\r
+\r
+ eaddrs = (UINT16 *) AdapterInfo->CurrentNodeAddress;\r
+\r
+ cmd_ptr = GetFreeCB (AdapterInfo);\r
+ data_ptr = (UINT16 *) (&cmd_ptr->PhysTBDArrayAddres);\r
+\r
+ //\r
+ // AVOID a bug (?!) here by marking the command already completed.\r
+ //\r
+ cmd_ptr->cb_header.command = (CmdSuspend | CmdIASetup);\r
+ cmd_ptr->cb_header.status = 0;\r
+ data_ptr[0] = eaddrs[0];\r
+ data_ptr[1] = eaddrs[1];\r
+ data_ptr[2] = eaddrs[2];\r
+\r
+ BlockIt (AdapterInfo, TRUE);\r
+ IssueCB (AdapterInfo, cmd_ptr);\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+ BlockIt (AdapterInfo, FALSE);\r
+\r
+ CommandWaitForCompletion (cmd_ptr, AdapterInfo);\r
+\r
+ //\r
+ // restore the cb values for tx\r
+ //\r
+ cmd_ptr->PhysTBDArrayAddres = cmd_ptr->PhysArrayAddr;\r
+ cmd_ptr->ByteCount = cmd_ptr->Threshold = cmd_ptr->TBDCount = 0;\r
+ //\r
+ // fields beyond the immediatedata are assumed to be safe\r
+ // add the CB to the free list again\r
+ //\r
+ SetFreeCB (AdapterInfo, cmd_ptr);\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ Instructs the NIC to stop receiving packets.\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+\r
+\r
+**/\r
+VOID\r
+StopRU (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ if (AdapterInfo->Receive_Started) {\r
+\r
+ //\r
+ // Todo: verify that we must wait for previous command completion.\r
+ //\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ //\r
+ // Disable interrupts, and stop the chip's Rx process.\r
+ //\r
+ OutWord (AdapterInfo, INT_MASK, AdapterInfo->ioaddr + SCBCmd);\r
+ OutWord (AdapterInfo, INT_MASK | RX_ABORT, AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ AdapterInfo->Receive_Started = FALSE;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ Instructs the NIC to start receiving packets.\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+\r
+ @retval 0 Successful\r
+ @retval -1 Already Started\r
+\r
+**/\r
+INT8\r
+StartRU (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+\r
+ if (AdapterInfo->Receive_Started) {\r
+ //\r
+ // already started\r
+ //\r
+ return -1;\r
+ }\r
+\r
+ AdapterInfo->cur_rx_ind = 0;\r
+ AdapterInfo->Int_Status = 0;\r
+\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ OutLong (AdapterInfo, (UINT32) AdapterInfo->rx_phy_addr, AdapterInfo->ioaddr + SCBPointer);\r
+ OutByte (AdapterInfo, RX_START, AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ AdapterInfo->Receive_Started = TRUE;\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ Configures the chip. This routine expects the NIC_DATA_INSTANCE structure to be filled in.\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+\r
+ @retval 0 Successful\r
+ @retval PXE_STATCODE_NOT_ENOUGH_MEMORY Insufficient length of locked memory\r
+ @retval other Failure initializing chip\r
+\r
+**/\r
+UINTN\r
+E100bInit (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ PCI_CONFIG_HEADER *CfgHdr;\r
+ UINTN stat;\r
+ UINTN rx_size;\r
+ UINTN tx_size;\r
+\r
+ if (AdapterInfo->MemoryLength < MEMORY_NEEDED) {\r
+ return PXE_STATCODE_NOT_ENOUGH_MEMORY;\r
+ }\r
+\r
+ stat = MapIt (\r
+ AdapterInfo,\r
+ AdapterInfo->MemoryPtr,\r
+ AdapterInfo->MemoryLength,\r
+ TO_AND_FROM_DEVICE,\r
+ (UINT64)(UINTN) &AdapterInfo->Mapped_MemoryPtr\r
+ );\r
+\r
+ if (stat != 0) {\r
+ return stat;\r
+ }\r
+\r
+ CfgHdr = (PCI_CONFIG_HEADER *) &(AdapterInfo->Config[0]);\r
+\r
+ //\r
+ // fill in the ioaddr, int... from the config space\r
+ //\r
+ AdapterInfo->int_num = CfgHdr->int_line;\r
+\r
+ //\r
+ // we don't need to validate integer number, what if they don't want to assign one?\r
+ // if (AdapterInfo->int_num == 0 || AdapterInfo->int_num == 0xff)\r
+ // return PXE_STATCODE_DEVICE_FAILURE;\r
+ //\r
+ AdapterInfo->ioaddr = 0;\r
+ AdapterInfo->VendorID = CfgHdr->VendorID;\r
+ AdapterInfo->DeviceID = CfgHdr->DeviceID;\r
+ AdapterInfo->RevID = CfgHdr->RevID;\r
+ AdapterInfo->SubVendorID = CfgHdr->SubVendorID;\r
+ AdapterInfo->SubSystemID = CfgHdr->SubSystemID;\r
+ AdapterInfo->flash_addr = 0;\r
+\r
+ //\r
+ // Read the station address EEPROM before doing the reset.\r
+ // Perhaps this should even be done before accepting the device,\r
+ // then we wouldn't have a device name with which to report the error.\r
+ //\r
+ if (E100bReadEepromAndStationAddress (AdapterInfo) != 0) {\r
+ return PXE_STATCODE_DEVICE_FAILURE;\r
+\r
+ }\r
+ //\r
+ // ## calculate the buffer #s depending on memory given\r
+ // ## calculate the rx and tx ring pointers\r
+ //\r
+\r
+ AdapterInfo->TxBufCnt = TX_BUFFER_COUNT;\r
+ AdapterInfo->RxBufCnt = RX_BUFFER_COUNT;\r
+ rx_size = (AdapterInfo->RxBufCnt * sizeof (RxFD));\r
+ tx_size = (AdapterInfo->TxBufCnt * sizeof (TxCB));\r
+ AdapterInfo->rx_ring = (RxFD *) (UINTN) (AdapterInfo->MemoryPtr);\r
+ AdapterInfo->tx_ring = (TxCB *) (UINTN) (AdapterInfo->MemoryPtr + rx_size);\r
+ AdapterInfo->statistics = (struct speedo_stats *) (UINTN) (AdapterInfo->MemoryPtr + rx_size + tx_size);\r
+\r
+ AdapterInfo->rx_phy_addr = AdapterInfo->Mapped_MemoryPtr;\r
+ AdapterInfo->tx_phy_addr = AdapterInfo->Mapped_MemoryPtr + rx_size;\r
+ AdapterInfo->stat_phy_addr = AdapterInfo->tx_phy_addr + tx_size;\r
+\r
+ //\r
+ // auto detect.\r
+ //\r
+ AdapterInfo->PhyAddress = 0xFF;\r
+ AdapterInfo->Rx_Filter = PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST;\r
+ AdapterInfo->Receive_Started = FALSE;\r
+ AdapterInfo->mcast_list.list_len = 0;\r
+ return InitializeChip (AdapterInfo);\r
+}\r
+\r
+\r
+/**\r
+ Sets the interrupt state for the NIC.\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+\r
+ @retval 0 Successful\r
+\r
+**/\r
+UINT8\r
+E100bSetInterruptState (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ //\r
+ // don't set receive interrupt if receiver is disabled...\r
+ //\r
+ UINT16 cmd_word;\r
+\r
+ if ((AdapterInfo->int_mask & PXE_OPFLAGS_INTERRUPT_RECEIVE) != 0) {\r
+ cmd_word = InWord (AdapterInfo, AdapterInfo->ioaddr + SCBCmd);\r
+ cmd_word &= ~INT_MASK;\r
+ OutWord (AdapterInfo, cmd_word, AdapterInfo->ioaddr + SCBCmd);\r
+ } else {\r
+ //\r
+ // disable ints, should not be given for SW Int.\r
+ //\r
+ OutWord (AdapterInfo, INT_MASK, AdapterInfo->ioaddr + SCBCmd);\r
+ }\r
+\r
+ if ((AdapterInfo->int_mask & PXE_OPFLAGS_INTERRUPT_SOFTWARE) != 0) {\r
+ //\r
+ // reset the bit in our mask, it is only one time!!\r
+ //\r
+ AdapterInfo->int_mask &= ~(PXE_OPFLAGS_INTERRUPT_SOFTWARE);\r
+ cmd_word = InWord (AdapterInfo, AdapterInfo->ioaddr + SCBCmd);\r
+ cmd_word |= DRVR_INT;\r
+ OutWord (AdapterInfo, cmd_word, AdapterInfo->ioaddr + SCBCmd);\r
+ }\r
+\r
+ return 0;\r
+}\r
+//\r
+// we are not going to disable broadcast for the WOL's sake!\r
+//\r
+\r
+/**\r
+ Instructs the NIC to start receiving packets.\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on.. new_filter\r
+ - cpb -\r
+ cpbsize -\r
+\r
+ @retval 0 Successful\r
+ @retval -1 Already Started\r
+\r
+**/\r
+UINTN\r
+E100bSetfilter (\r
+ NIC_DATA_INSTANCE *AdapterInfo,\r
+ UINT16 new_filter,\r
+ UINT64 cpb,\r
+ UINT32 cpbsize\r
+ )\r
+{\r
+ PXE_CPB_RECEIVE_FILTERS *mc_list = (PXE_CPB_RECEIVE_FILTERS *) (UINTN)cpb;\r
+ UINT16 cfg_flt;\r
+ UINT16 old_filter;\r
+ UINT16 Index;\r
+ UINT16 Index2;\r
+ UINT16 mc_count;\r
+ TxCB *cmd_ptr;\r
+ struct MC_CB_STRUCT *data_ptr;\r
+ UINT16 mc_byte_cnt;\r
+\r
+ old_filter = AdapterInfo->Rx_Filter;\r
+\r
+ //\r
+ // only these bits need a change in the configuration\r
+ // actually change in bcast requires configure but we ignore that change\r
+ //\r
+ cfg_flt = PXE_OPFLAGS_RECEIVE_FILTER_PROMISCUOUS |\r
+ PXE_OPFLAGS_RECEIVE_FILTER_ALL_MULTICAST;\r
+\r
+ if ((old_filter & cfg_flt) != (new_filter & cfg_flt)) {\r
+ XmitWaitForCompletion (AdapterInfo);\r
+\r
+ if (AdapterInfo->Receive_Started) {\r
+ StopRU (AdapterInfo);\r
+ }\r
+\r
+ AdapterInfo->Rx_Filter = (UINT8) (new_filter | PXE_OPFLAGS_RECEIVE_FILTER_BROADCAST);\r
+ Configure (AdapterInfo);\r
+ }\r
+\r
+ //\r
+ // check if mcast setting changed\r
+ //\r
+ if ( ((new_filter & PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST) !=\r
+ (old_filter & PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST) ) ||\r
+ (mc_list != NULL) ) {\r
+\r
+\r
+ if (mc_list != NULL) {\r
+ mc_count = AdapterInfo->mcast_list.list_len = (UINT16) (cpbsize / PXE_MAC_LENGTH);\r
+\r
+ for (Index = 0; (Index < mc_count && Index < MAX_MCAST_ADDRESS_CNT); Index++) {\r
+ for (Index2 = 0; Index2 < PXE_MAC_LENGTH; Index2++) {\r
+ AdapterInfo->mcast_list.mc_list[Index][Index2] = mc_list->MCastList[Index][Index2];\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // are we setting the list or resetting??\r
+ //\r
+ if ((new_filter & PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST) != 0) {\r
+ //\r
+ // we are setting a new list!\r
+ //\r
+ mc_count = AdapterInfo->mcast_list.list_len;\r
+ //\r
+ // count should be the actual # of bytes in the list\r
+ // so multiply this with 6\r
+ //\r
+ mc_byte_cnt = (UINT16) ((mc_count << 2) + (mc_count << 1));\r
+ AdapterInfo->Rx_Filter |= PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST;\r
+ } else {\r
+ //\r
+ // disabling the list in the NIC.\r
+ //\r
+ mc_byte_cnt = mc_count = 0;\r
+ AdapterInfo->Rx_Filter &= (~PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST);\r
+ }\r
+\r
+ //\r
+ // before issuing any new command!\r
+ //\r
+ XmitWaitForCompletion (AdapterInfo);\r
+\r
+ if (AdapterInfo->Receive_Started) {\r
+ StopRU (AdapterInfo);\r
+\r
+ }\r
+\r
+ cmd_ptr = GetFreeCB (AdapterInfo);\r
+ if (cmd_ptr == NULL) {\r
+ return PXE_STATCODE_QUEUE_FULL;\r
+ }\r
+ //\r
+ // fill the command structure and issue\r
+ //\r
+ data_ptr = (struct MC_CB_STRUCT *) (&cmd_ptr->PhysTBDArrayAddres);\r
+ //\r
+ // first 2 bytes are the count;\r
+ //\r
+ data_ptr->count = mc_byte_cnt;\r
+ for (Index = 0; Index < mc_count; Index++) {\r
+ for (Index2 = 0; Index2 < PXE_HWADDR_LEN_ETHER; Index2++) {\r
+ data_ptr->m_list[Index][Index2] = AdapterInfo->mcast_list.mc_list[Index][Index2];\r
+ }\r
+ }\r
+\r
+ cmd_ptr->cb_header.command = CmdSuspend | CmdMulticastList;\r
+ cmd_ptr->cb_header.status = 0;\r
+\r
+ BlockIt (AdapterInfo, TRUE);\r
+ IssueCB (AdapterInfo, cmd_ptr);\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ BlockIt (AdapterInfo, FALSE);\r
+\r
+ CommandWaitForCompletion (cmd_ptr, AdapterInfo);\r
+\r
+ cmd_ptr->PhysTBDArrayAddres = cmd_ptr->PhysArrayAddr;\r
+ cmd_ptr->ByteCount = cmd_ptr->Threshold = cmd_ptr->TBDCount = 0;\r
+ //\r
+ // fields beyond the immediatedata are assumed to be safe\r
+ // add the CB to the free list again\r
+ //\r
+ SetFreeCB (AdapterInfo, cmd_ptr);\r
+ }\r
+\r
+ if (new_filter != 0) {\r
+ //\r
+ // enable unicast and start the RU\r
+ //\r
+ AdapterInfo->Rx_Filter = (UINT8) (AdapterInfo->Rx_Filter | (new_filter | PXE_OPFLAGS_RECEIVE_FILTER_UNICAST));\r
+ StartRU (AdapterInfo);\r
+ } else {\r
+ //\r
+ // may be disabling everything!\r
+ //\r
+ if (AdapterInfo->Receive_Started) {\r
+ StopRU (AdapterInfo);\r
+ }\r
+\r
+ AdapterInfo->Rx_Filter |= (~PXE_OPFLAGS_RECEIVE_FILTER_UNICAST);\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+ @param cpb TODO: add argument description\r
+ @param opflags TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINTN\r
+E100bTransmit (\r
+ NIC_DATA_INSTANCE *AdapterInfo,\r
+ UINT64 cpb,\r
+ UINT16 opflags\r
+ )\r
+{\r
+ PXE_CPB_TRANSMIT_FRAGMENTS *tx_ptr_f;\r
+ PXE_CPB_TRANSMIT *tx_ptr_1;\r
+ TxCB *tcb_ptr;\r
+ UINT64 Tmp_ptr;\r
+ UINTN stat;\r
+ INT32 Index;\r
+ UINT16 wait_sec;\r
+\r
+ tx_ptr_1 = (PXE_CPB_TRANSMIT *) (UINTN) cpb;\r
+ tx_ptr_f = (PXE_CPB_TRANSMIT_FRAGMENTS *) (UINTN) cpb;\r
+\r
+ //\r
+ // stop reentrancy here\r
+ //\r
+ if (AdapterInfo->in_transmit) {\r
+ return PXE_STATCODE_BUSY;\r
+\r
+ }\r
+\r
+ AdapterInfo->in_transmit = TRUE;\r
+\r
+ //\r
+ // Prevent interrupts from changing the Tx ring from underneath us.\r
+ //\r
+ // Calculate the Tx descriptor entry.\r
+ //\r
+ if ((tcb_ptr = GetFreeCB (AdapterInfo)) == NULL) {\r
+ AdapterInfo->in_transmit = FALSE;\r
+ return PXE_STATCODE_QUEUE_FULL;\r
+ }\r
+\r
+ AdapterInfo->TxTotals++;\r
+\r
+ tcb_ptr->cb_header.command = (CmdSuspend | CmdTx | CmdTxFlex);\r
+ tcb_ptr->cb_header.status = 0;\r
+\r
+ //\r
+ // no immediate data, set EOF in the ByteCount\r
+ //\r
+ tcb_ptr->ByteCount = 0x8000;\r
+\r
+ //\r
+ // The data region is always in one buffer descriptor, Tx FIFO\r
+ // threshold of 256.\r
+ // 82557 multiplies the threashold value by 8, so give 256/8\r
+ //\r
+ tcb_ptr->Threshold = 32;\r
+ if ((opflags & PXE_OPFLAGS_TRANSMIT_FRAGMENTED) != 0) {\r
+\r
+ if (tx_ptr_f->FragCnt > MAX_XMIT_FRAGMENTS) {\r
+ SetFreeCB (AdapterInfo, tcb_ptr);\r
+ AdapterInfo->in_transmit = FALSE;\r
+ return PXE_STATCODE_INVALID_PARAMETER;\r
+ }\r
+\r
+ tcb_ptr->TBDCount = (UINT8) tx_ptr_f->FragCnt;\r
+\r
+ for (Index = 0; Index < tx_ptr_f->FragCnt; Index++) {\r
+ stat = MapIt (\r
+ AdapterInfo,\r
+ tx_ptr_f->FragDesc[Index].FragAddr,\r
+ tx_ptr_f->FragDesc[Index].FragLen,\r
+ TO_DEVICE,\r
+ (UINT64)(UINTN) &Tmp_ptr\r
+ );\r
+ if (stat != 0) {\r
+ SetFreeCB (AdapterInfo, tcb_ptr);\r
+ AdapterInfo->in_transmit = FALSE;\r
+ return PXE_STATCODE_INVALID_PARAMETER;\r
+ }\r
+\r
+ tcb_ptr->TBDArray[Index].phys_buf_addr = (UINT32) Tmp_ptr;\r
+ tcb_ptr->TBDArray[Index].buf_len = tx_ptr_f->FragDesc[Index].FragLen;\r
+ }\r
+\r
+ tcb_ptr->free_data_ptr = tx_ptr_f->FragDesc[0].FragAddr;\r
+\r
+ } else {\r
+ //\r
+ // non fragmented case\r
+ //\r
+ tcb_ptr->TBDCount = 1;\r
+ stat = MapIt (\r
+ AdapterInfo,\r
+ tx_ptr_1->FrameAddr,\r
+ tx_ptr_1->DataLen + tx_ptr_1->MediaheaderLen,\r
+ TO_DEVICE,\r
+ (UINT64)(UINTN) &Tmp_ptr\r
+ );\r
+ if (stat != 0) {\r
+ SetFreeCB (AdapterInfo, tcb_ptr);\r
+ AdapterInfo->in_transmit = FALSE;\r
+ return PXE_STATCODE_INVALID_PARAMETER;\r
+ }\r
+\r
+ tcb_ptr->TBDArray[0].phys_buf_addr = (UINT32) (Tmp_ptr);\r
+ tcb_ptr->TBDArray[0].buf_len = tx_ptr_1->DataLen + tx_ptr_1->MediaheaderLen;\r
+ tcb_ptr->free_data_ptr = tx_ptr_1->FrameAddr;\r
+ }\r
+\r
+ //\r
+ // must wait for previous command completion only if it was a non-transmit\r
+ //\r
+ BlockIt (AdapterInfo, TRUE);\r
+ IssueCB (AdapterInfo, tcb_ptr);\r
+ BlockIt (AdapterInfo, FALSE);\r
+\r
+ //\r
+ // see if we need to wait for completion here\r
+ //\r
+ if ((opflags & PXE_OPFLAGS_TRANSMIT_BLOCK) != 0) {\r
+ //\r
+ // don't wait for more than 1 second!!!\r
+ //\r
+ wait_sec = 1000;\r
+ while (tcb_ptr->cb_header.status == 0) {\r
+ DelayIt (AdapterInfo, 10);\r
+ wait_sec--;\r
+ if (wait_sec == 0) {\r
+ break;\r
+ }\r
+ }\r
+ //\r
+ // we need to un-map any mapped buffers here\r
+ //\r
+ if ((opflags & PXE_OPFLAGS_TRANSMIT_FRAGMENTED) != 0) {\r
+\r
+ for (Index = 0; Index < tx_ptr_f->FragCnt; Index++) {\r
+ Tmp_ptr = tcb_ptr->TBDArray[Index].phys_buf_addr;\r
+ UnMapIt (\r
+ AdapterInfo,\r
+ tx_ptr_f->FragDesc[Index].FragAddr,\r
+ tx_ptr_f->FragDesc[Index].FragLen,\r
+ TO_DEVICE,\r
+ (UINT64) Tmp_ptr\r
+ );\r
+ }\r
+ } else {\r
+ Tmp_ptr = tcb_ptr->TBDArray[0].phys_buf_addr;\r
+ UnMapIt (\r
+ AdapterInfo,\r
+ tx_ptr_1->FrameAddr,\r
+ tx_ptr_1->DataLen + tx_ptr_1->MediaheaderLen,\r
+ TO_DEVICE,\r
+ (UINT64) Tmp_ptr\r
+ );\r
+ }\r
+\r
+ if (tcb_ptr->cb_header.status == 0) {\r
+ SetFreeCB (AdapterInfo, tcb_ptr);\r
+ AdapterInfo->in_transmit = FALSE;\r
+ return PXE_STATCODE_DEVICE_FAILURE;\r
+ }\r
+\r
+ SetFreeCB (AdapterInfo, tcb_ptr);\r
+ }\r
+ //\r
+ // CB will be set free later in get_status (or when we run out of xmit buffers\r
+ //\r
+ AdapterInfo->in_transmit = FALSE;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+ @param cpb TODO: add argument description\r
+ @param db TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINTN\r
+E100bReceive (\r
+ NIC_DATA_INSTANCE *AdapterInfo,\r
+ UINT64 cpb,\r
+ UINT64 db\r
+ )\r
+{\r
+ PXE_CPB_RECEIVE *rx_cpbptr;\r
+ PXE_DB_RECEIVE *rx_dbptr;\r
+ RxFD *rx_ptr;\r
+ INT32 status;\r
+ INT32 Index;\r
+ UINT16 pkt_len;\r
+ UINT16 ret_code;\r
+ PXE_FRAME_TYPE pkt_type;\r
+ UINT16 Tmp_len;\r
+ EtherHeader *hdr_ptr;\r
+ ret_code = PXE_STATCODE_NO_DATA;\r
+ pkt_type = PXE_FRAME_TYPE_NONE;\r
+ status = InWord (AdapterInfo, AdapterInfo->ioaddr + SCBStatus);\r
+ AdapterInfo->Int_Status = (UINT16) (AdapterInfo->Int_Status | status);\r
+ //\r
+ // acknoledge the interrupts\r
+ //\r
+ OutWord (AdapterInfo, (UINT16) (status & 0xfc00), (UINT32) (AdapterInfo->ioaddr + SCBStatus));\r
+\r
+ //\r
+ // include the prev ints as well\r
+ //\r
+ status = AdapterInfo->Int_Status;\r
+ rx_cpbptr = (PXE_CPB_RECEIVE *) (UINTN) cpb;\r
+ rx_dbptr = (PXE_DB_RECEIVE *) (UINTN) db;\r
+\r
+ rx_ptr = &AdapterInfo->rx_ring[AdapterInfo->cur_rx_ind];\r
+\r
+ //\r
+ // be in a loop just in case (we may drop a pkt)\r
+ //\r
+ while ((status = rx_ptr->cb_header.status) & RX_COMPLETE) {\r
+\r
+ AdapterInfo->RxTotals++;\r
+ //\r
+ // If we own the next entry, it's a new packet. Send it up.\r
+ //\r
+ if (rx_ptr->forwarded) {\r
+ goto FreeRFD;\r
+\r
+ }\r
+\r
+ //\r
+ // discard bad frames\r
+ //\r
+\r
+ //\r
+ // crc, align, dma overrun, too short, receive error (v22 no coll)\r
+ //\r
+ if ((status & 0x0D90) != 0) {\r
+ goto FreeRFD;\r
+\r
+ }\r
+\r
+ //\r
+ // make sure the status is OK\r
+ //\r
+ if ((status & 0x02000) == 0) {\r
+ goto FreeRFD;\r
+ }\r
+\r
+ pkt_len = (UINT16) (rx_ptr->ActualCount & 0x3fff);\r
+\r
+ if (pkt_len != 0) {\r
+\r
+ Tmp_len = pkt_len;\r
+ if (pkt_len > rx_cpbptr->BufferLen) {\r
+ Tmp_len = (UINT16) rx_cpbptr->BufferLen;\r
+ }\r
+\r
+ CopyMem ((INT8 *) (UINTN) rx_cpbptr->BufferAddr, (INT8 *) &rx_ptr->RFDBuffer, Tmp_len);\r
+\r
+ hdr_ptr = (EtherHeader *) &rx_ptr->RFDBuffer;\r
+ //\r
+ // fill the CDB and break the loop\r
+ //\r
+\r
+ //\r
+ // includes header\r
+ //\r
+ rx_dbptr->FrameLen = pkt_len;\r
+ rx_dbptr->MediaHeaderLen = PXE_MAC_HEADER_LEN_ETHER;\r
+\r
+ for (Index = 0; Index < PXE_HWADDR_LEN_ETHER; Index++) {\r
+ if (hdr_ptr->dest_addr[Index] != AdapterInfo->CurrentNodeAddress[Index]) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (Index >= PXE_HWADDR_LEN_ETHER) {\r
+ pkt_type = PXE_FRAME_TYPE_UNICAST;\r
+ } else {\r
+ for (Index = 0; Index < PXE_HWADDR_LEN_ETHER; Index++) {\r
+ if (hdr_ptr->dest_addr[Index] != AdapterInfo->BroadcastNodeAddress[Index]) {\r
+ break;\r
+ }\r
+ }\r
+\r
+ if (Index >= PXE_HWADDR_LEN_ETHER) {\r
+ pkt_type = PXE_FRAME_TYPE_BROADCAST;\r
+ } else {\r
+ if ((hdr_ptr->dest_addr[0] & 1) == 1) {\r
+ //\r
+ // mcast\r
+ //\r
+\r
+ pkt_type = PXE_FRAME_TYPE_FILTERED_MULTICAST;\r
+ } else {\r
+ pkt_type = PXE_FRAME_TYPE_PROMISCUOUS;\r
+ }\r
+ }\r
+ }\r
+\r
+ rx_dbptr->Type = pkt_type;\r
+ rx_dbptr->Protocol = hdr_ptr->type;\r
+\r
+ for (Index = 0; Index < PXE_HWADDR_LEN_ETHER; Index++) {\r
+ rx_dbptr->SrcAddr[Index] = hdr_ptr->src_addr[Index];\r
+ rx_dbptr->DestAddr[Index] = hdr_ptr->dest_addr[Index];\r
+ }\r
+\r
+ rx_ptr->forwarded = TRUE;\r
+ //\r
+ // success\r
+ //\r
+ ret_code = 0;\r
+ Recycle_RFD (AdapterInfo, AdapterInfo->cur_rx_ind);\r
+ AdapterInfo->cur_rx_ind++;\r
+ if (AdapterInfo->cur_rx_ind == AdapterInfo->RxBufCnt) {\r
+ AdapterInfo->cur_rx_ind = 0;\r
+ }\r
+ break;\r
+ }\r
+\r
+FreeRFD:\r
+ Recycle_RFD (AdapterInfo, AdapterInfo->cur_rx_ind);\r
+ AdapterInfo->cur_rx_ind++;\r
+ if (AdapterInfo->cur_rx_ind == AdapterInfo->RxBufCnt) {\r
+ AdapterInfo->cur_rx_ind = 0;\r
+ }\r
+\r
+ rx_ptr = &AdapterInfo->rx_ring[AdapterInfo->cur_rx_ind];\r
+ }\r
+\r
+ if (pkt_type == PXE_FRAME_TYPE_NONE) {\r
+ AdapterInfo->Int_Status &= (~SCB_STATUS_FR);\r
+ }\r
+\r
+ status = InWord (AdapterInfo, AdapterInfo->ioaddr + SCBStatus);\r
+ if ((status & SCB_RUS_NO_RESOURCES) != 0) {\r
+ //\r
+ // start the receive unit here!\r
+ // leave all the filled frames,\r
+ //\r
+ SetupReceiveQueues (AdapterInfo);\r
+ OutLong (AdapterInfo, (UINT32) AdapterInfo->rx_phy_addr, AdapterInfo->ioaddr + SCBPointer);\r
+ OutWord (AdapterInfo, RX_START, AdapterInfo->ioaddr + SCBCmd);\r
+ AdapterInfo->cur_rx_ind = 0;\r
+ }\r
+\r
+ return ret_code;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+INT16\r
+E100bReadEepromAndStationAddress (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ INT32 Index;\r
+ INT32 Index2;\r
+ UINT16 sum;\r
+ UINT16 eeprom_len;\r
+ UINT8 addr_len;\r
+ UINT16 *eedata;\r
+\r
+ eedata = (UINT16 *) (&AdapterInfo->NVData[0]);\r
+\r
+ sum = 0;\r
+ addr_len = E100bGetEepromAddrLen (AdapterInfo);\r
+\r
+ //\r
+ // in words\r
+ //\r
+ AdapterInfo->NVData_Len = eeprom_len = (UINT16) (1 << addr_len);\r
+ for (Index2 = 0, Index = 0; Index < eeprom_len; Index++) {\r
+ UINT16 value;\r
+ value = E100bReadEeprom (AdapterInfo, Index, addr_len);\r
+ eedata[Index] = value;\r
+ sum = (UINT16) (sum + value);\r
+ if (Index < 3) {\r
+ AdapterInfo->PermNodeAddress[Index2++] = (UINT8) value;\r
+ AdapterInfo->PermNodeAddress[Index2++] = (UINT8) (value >> 8);\r
+ }\r
+ }\r
+\r
+ if (sum != 0xBABA) {\r
+ return -1;\r
+ }\r
+\r
+ for (Index = 0; Index < PXE_HWADDR_LEN_ETHER; Index++) {\r
+ AdapterInfo->CurrentNodeAddress[Index] = AdapterInfo->PermNodeAddress[Index];\r
+ }\r
+\r
+ for (Index = 0; Index < PXE_HWADDR_LEN_ETHER; Index++) {\r
+ AdapterInfo->BroadcastNodeAddress[Index] = 0xff;\r
+ }\r
+\r
+ for (Index = PXE_HWADDR_LEN_ETHER; Index < PXE_MAC_LENGTH; Index++) {\r
+ AdapterInfo->CurrentNodeAddress[Index] = 0;\r
+ AdapterInfo->PermNodeAddress[Index] = 0;\r
+ AdapterInfo->BroadcastNodeAddress[Index] = 0;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+//\r
+// CBList is a circular linked list\r
+// 1) When all are free, Tail->next == Head and FreeCount == # allocated\r
+// 2) When none are free, Tail == Head and FreeCount == 0\r
+// 3) when one is free, Tail == Head and Freecount == 1\r
+// 4) First non-Free frame is always at Tail->next\r
+//\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT8\r
+SetupCBlink (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ TxCB *head_ptr;\r
+ TxCB *tail_ptr;\r
+ TxCB *cur_ptr;\r
+ INT32 Index;\r
+ UINTN array_off;\r
+\r
+ cur_ptr = &(AdapterInfo->tx_ring[0]);\r
+ array_off = (UINTN) (&cur_ptr->TBDArray) - (UINTN) cur_ptr;\r
+ for (Index = 0; Index < AdapterInfo->TxBufCnt; Index++) {\r
+ cur_ptr[Index].cb_header.status = 0;\r
+ cur_ptr[Index].cb_header.command = 0;\r
+\r
+ cur_ptr[Index].PhysTCBAddress =\r
+ (UINT32) AdapterInfo->tx_phy_addr + (Index * sizeof (TxCB));\r
+\r
+ cur_ptr[Index].PhysArrayAddr = (UINT32)(cur_ptr[Index].PhysTCBAddress + array_off);\r
+ cur_ptr[Index].PhysTBDArrayAddres = (UINT32)(cur_ptr[Index].PhysTCBAddress + array_off);\r
+\r
+ cur_ptr->free_data_ptr = (UINT64) 0;\r
+\r
+ if (Index < AdapterInfo->TxBufCnt - 1) {\r
+ cur_ptr[Index].cb_header.link = cur_ptr[Index].PhysTCBAddress + sizeof (TxCB);\r
+ cur_ptr[Index].NextTCBVirtualLinkPtr = &cur_ptr[Index + 1];\r
+ cur_ptr[Index + 1].PrevTCBVirtualLinkPtr = &cur_ptr[Index];\r
+ }\r
+ }\r
+\r
+ head_ptr = &cur_ptr[0];\r
+ tail_ptr = &cur_ptr[AdapterInfo->TxBufCnt - 1];\r
+ tail_ptr->cb_header.link = head_ptr->PhysTCBAddress;\r
+ tail_ptr->NextTCBVirtualLinkPtr = head_ptr;\r
+ head_ptr->PrevTCBVirtualLinkPtr = tail_ptr;\r
+\r
+ AdapterInfo->FreeCBCount = AdapterInfo->TxBufCnt;\r
+ AdapterInfo->FreeTxHeadPtr = head_ptr;\r
+ //\r
+ // set tail of the free list, next to this would be either in use\r
+ // or the head itself\r
+ //\r
+ AdapterInfo->FreeTxTailPtr = tail_ptr;\r
+\r
+ AdapterInfo->xmit_done_head = AdapterInfo->xmit_done_tail = 0;\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+TxCB *\r
+GetFreeCB (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ TxCB *free_cb_ptr;\r
+\r
+ //\r
+ // claim any hanging free CBs\r
+ //\r
+ if (AdapterInfo->FreeCBCount <= 1) {\r
+ CheckCBList (AdapterInfo);\r
+ }\r
+\r
+ //\r
+ // don't use up the last CB problem if the previous CB that the CU used\r
+ // becomes the last CB we submit because of the SUSPEND bit we set.\r
+ // the CU thinks it was never cleared.\r
+ //\r
+\r
+ if (AdapterInfo->FreeCBCount <= 1) {\r
+ return NULL;\r
+ }\r
+\r
+ BlockIt (AdapterInfo, TRUE);\r
+ free_cb_ptr = AdapterInfo->FreeTxHeadPtr;\r
+ AdapterInfo->FreeTxHeadPtr = free_cb_ptr->NextTCBVirtualLinkPtr;\r
+ --AdapterInfo->FreeCBCount;\r
+ BlockIt (AdapterInfo, FALSE);\r
+ return free_cb_ptr;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+ @param cb_ptr TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+VOID\r
+SetFreeCB (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN TxCB *cb_ptr\r
+ )\r
+{\r
+ //\r
+ // here we assume cb are returned in the order they are taken out\r
+ // and we link the newly freed cb at the tail of free cb list\r
+ //\r
+ cb_ptr->cb_header.status = 0;\r
+ cb_ptr->free_data_ptr = (UINT64) 0;\r
+\r
+ AdapterInfo->FreeTxTailPtr = cb_ptr;\r
+ ++AdapterInfo->FreeCBCount;\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param ind TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT16\r
+next (\r
+ IN UINT16 ind\r
+ )\r
+{\r
+ UINT16 Tmp;\r
+\r
+ Tmp = (UINT16) (ind + 1);\r
+ if (Tmp >= (TX_BUFFER_COUNT << 1)) {\r
+ Tmp = 0;\r
+ }\r
+\r
+ return Tmp;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT16\r
+CheckCBList (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ TxCB *Tmp_ptr;\r
+ UINT16 cnt;\r
+\r
+ cnt = 0;\r
+ while (1) {\r
+ Tmp_ptr = AdapterInfo->FreeTxTailPtr->NextTCBVirtualLinkPtr;\r
+ if ((Tmp_ptr->cb_header.status & CMD_STATUS_MASK) != 0) {\r
+ //\r
+ // check if Q is full\r
+ //\r
+ if (next (AdapterInfo->xmit_done_tail) != AdapterInfo->xmit_done_head) {\r
+ AdapterInfo->xmit_done[AdapterInfo->xmit_done_tail] = Tmp_ptr->free_data_ptr;\r
+\r
+ UnMapIt (\r
+ AdapterInfo,\r
+ Tmp_ptr->free_data_ptr,\r
+ Tmp_ptr->TBDArray[0].buf_len,\r
+ TO_DEVICE,\r
+ (UINT64) Tmp_ptr->TBDArray[0].phys_buf_addr\r
+ );\r
+\r
+ AdapterInfo->xmit_done_tail = next (AdapterInfo->xmit_done_tail);\r
+ }\r
+\r
+ SetFreeCB (AdapterInfo, Tmp_ptr);\r
+ } else {\r
+ break;\r
+ }\r
+ }\r
+\r
+ return cnt;\r
+}\r
+//\r
+// Description : Initialize the RFD list list by linking each element together\r
+// in a circular list. The simplified memory model is used.\r
+// All data is in the RFD. The RFDs are linked together and the\r
+// last one points back to the first one. When the current RFD\r
+// is processed (frame received), its EL bit is set and the EL\r
+// bit in the previous RXFD is cleared.\r
+// Allocation done during INIT, this is making linked list.\r
+//\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT8\r
+SetupReceiveQueues (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ RxFD *rx_ptr;\r
+ RxFD *tail_ptr;\r
+ UINT16 Index;\r
+\r
+ AdapterInfo->cur_rx_ind = 0;\r
+ rx_ptr = (&AdapterInfo->rx_ring[0]);\r
+\r
+ for (Index = 0; Index < AdapterInfo->RxBufCnt; Index++) {\r
+ rx_ptr[Index].cb_header.status = 0;\r
+ rx_ptr[Index].cb_header.command = 0;\r
+ rx_ptr[Index].RFDSize = RX_BUFFER_SIZE;\r
+ rx_ptr[Index].ActualCount = 0;\r
+ //\r
+ // RBDs not used, simple memory model\r
+ //\r
+ rx_ptr[Index].rx_buf_addr = (UINT32) (-1);\r
+\r
+ //\r
+ // RBDs not used, simple memory model\r
+ //\r
+ rx_ptr[Index].forwarded = FALSE;\r
+\r
+ //\r
+ // don't use Tmp_ptr if it is beyond the last one\r
+ //\r
+ if (Index < AdapterInfo->RxBufCnt - 1) {\r
+ rx_ptr[Index].cb_header.link = (UINT32) AdapterInfo->rx_phy_addr + ((Index + 1) * sizeof (RxFD));\r
+ }\r
+ }\r
+\r
+ tail_ptr = (&AdapterInfo->rx_ring[AdapterInfo->RxBufCnt - 1]);\r
+ tail_ptr->cb_header.link = (UINT32) AdapterInfo->rx_phy_addr;\r
+\r
+ //\r
+ // set the EL bit\r
+ //\r
+ tail_ptr->cb_header.command = 0xC000;\r
+ AdapterInfo->RFDTailPtr = tail_ptr;\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+ @param rx_index TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+VOID\r
+Recycle_RFD (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT16 rx_index\r
+ )\r
+{\r
+ RxFD *rx_ptr;\r
+ RxFD *tail_ptr;\r
+ //\r
+ // change the EL bit and change the AdapterInfo->RxTailPtr\r
+ // rx_ptr is assumed to be the head of the Q\r
+ // AdapterInfo->rx_forwarded[rx_index] = FALSE;\r
+ //\r
+ rx_ptr = &AdapterInfo->rx_ring[rx_index];\r
+ tail_ptr = AdapterInfo->RFDTailPtr;\r
+ //\r
+ // set el_bit and suspend bit\r
+ //\r
+ rx_ptr->cb_header.command = 0xc000;\r
+ rx_ptr->cb_header.status = 0;\r
+ rx_ptr->ActualCount = 0;\r
+ rx_ptr->forwarded = FALSE;\r
+ AdapterInfo->RFDTailPtr = rx_ptr;\r
+ //\r
+ // resetting the el_bit.\r
+ //\r
+ tail_ptr->cb_header.command = 0;\r
+ //\r
+ // check the receive unit, fix if there is any problem\r
+ //\r
+ return ;\r
+}\r
+//\r
+// Serial EEPROM section.\r
+//\r
+// EEPROM_Ctrl bits.\r
+//\r
+#define EE_SHIFT_CLK 0x01 /* EEPROM shift clock. */\r
+#define EE_CS 0x02 /* EEPROM chip select. */\r
+#define EE_DI 0x04 /* EEPROM chip data in. */\r
+#define EE_WRITE_0 0x01\r
+#define EE_WRITE_1 0x05\r
+#define EE_DO 0x08 /* EEPROM chip data out. */\r
+#define EE_ENB (0x4800 | EE_CS)\r
+\r
+//\r
+// Delay between EEPROM clock transitions.\r
+// This will actually work with no delay on 33Mhz PCI.\r
+//\r
+#define eeprom_delay(nanosec) DelayIt (AdapterInfo, nanosec);\r
+\r
+//\r
+// The EEPROM commands include the alway-set leading bit.\r
+//\r
+#define EE_WRITE_CMD 5 // 101b\r
+#define EE_READ_CMD 6 // 110b\r
+#define EE_ERASE_CMD (7 << 6)\r
+\r
+VOID\r
+shift_bits_out (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT16 val,\r
+ IN UINT8 num_bits\r
+ )\r
+/*++\r
+\r
+Routine Description:\r
+\r
+ TODO: Add function description\r
+\r
+Arguments:\r
+\r
+ AdapterInfo - TODO: add argument description\r
+ val - TODO: add argument description\r
+ num_bits - TODO: add argument description\r
+\r
+Returns:\r
+\r
+ TODO: add return values\r
+\r
+--*/\r
+{\r
+ INT32 Index;\r
+ UINT8 Tmp;\r
+ UINT32 EEAddr;\r
+\r
+ EEAddr = AdapterInfo->ioaddr + SCBeeprom;\r
+\r
+ for (Index = num_bits; Index >= 0; Index--) {\r
+ INT16 dataval;\r
+\r
+ //\r
+ // will be 0 or 4\r
+ //\r
+ dataval = (INT16) ((val & (1 << Index)) ? EE_DI : 0);\r
+\r
+ //\r
+ // mask off the data_in bit\r
+ //\r
+ Tmp = (UINT8) (InByte (AdapterInfo, EEAddr) &~EE_DI);\r
+ Tmp = (UINT8) (Tmp | dataval);\r
+ OutByte (AdapterInfo, Tmp, EEAddr);\r
+ eeprom_delay (100);\r
+ //\r
+ // raise the eeprom clock\r
+ //\r
+ OutByte (AdapterInfo, (UINT8) (Tmp | EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (150);\r
+ //\r
+ // lower the eeprom clock\r
+ //\r
+ OutByte (AdapterInfo, (UINT8) (Tmp &~EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (150);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT16\r
+shift_bits_in (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT8 Tmp;\r
+ INT32 Index;\r
+ UINT16 retval;\r
+ UINT32 EEAddr;\r
+\r
+ EEAddr = AdapterInfo->ioaddr + SCBeeprom;\r
+\r
+ retval = 0;\r
+ for (Index = 15; Index >= 0; Index--) {\r
+ //\r
+ // raise the clock\r
+ //\r
+\r
+ //\r
+ // mask off the data_in bit\r
+ //\r
+ Tmp = InByte (AdapterInfo, EEAddr);\r
+ OutByte (AdapterInfo, (UINT8) (Tmp | EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (100);\r
+ Tmp = InByte (AdapterInfo, EEAddr);\r
+ retval = (UINT16) ((retval << 1) | ((Tmp & EE_DO) ? 1 : 0));\r
+ //\r
+ // lower the clock\r
+ //\r
+ OutByte (AdapterInfo, (UINT8) (Tmp &~EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (100);\r
+ }\r
+\r
+ return retval;\r
+}\r
+\r
+\r
+/**\r
+ This routine sets the EEPROM lockout bit to gain exclusive access to the\r
+ eeprom. the access bit is the most significant bit in the General Control\r
+ Register 2 in the SCB space.\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+\r
+ @retval TRUE if it got the access\r
+ @retval FALSE if it fails to get the exclusive access\r
+\r
+**/\r
+BOOLEAN\r
+E100bSetEepromLockOut (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINTN wait;\r
+ UINT8 tmp;\r
+\r
+ if ((AdapterInfo->DeviceID == D102_DEVICE_ID) ||\r
+ (AdapterInfo->RevID >= D102_REVID)) {\r
+\r
+ wait = 500;\r
+\r
+ while (wait--) {\r
+\r
+ tmp = InByte (AdapterInfo, AdapterInfo->ioaddr + SCBGenCtrl2);\r
+ tmp |= GCR2_EEPROM_ACCESS_SEMAPHORE;\r
+ OutByte (AdapterInfo, tmp, AdapterInfo->ioaddr + SCBGenCtrl2);\r
+\r
+ DelayIt (AdapterInfo, 50);\r
+ tmp = InByte (AdapterInfo, AdapterInfo->ioaddr + SCBGenCtrl2);\r
+\r
+ if (tmp & GCR2_EEPROM_ACCESS_SEMAPHORE) {\r
+ return TRUE;\r
+ }\r
+ }\r
+\r
+ return FALSE;\r
+ }\r
+\r
+ return TRUE;\r
+}\r
+\r
+\r
+/**\r
+ This routine Resets the EEPROM lockout bit to giveup access to the\r
+ eeprom. the access bit is the most significant bit in the General Control\r
+ Register 2 in the SCB space.\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+E100bReSetEepromLockOut (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT8 tmp;\r
+\r
+ if ((AdapterInfo->DeviceID == D102_DEVICE_ID) ||\r
+ (AdapterInfo->RevID >= D102_REVID)) {\r
+\r
+ tmp = InByte (AdapterInfo, AdapterInfo->ioaddr + SCBGenCtrl2);\r
+ tmp &= ~(GCR2_EEPROM_ACCESS_SEMAPHORE);\r
+ OutByte (AdapterInfo, tmp, AdapterInfo->ioaddr + SCBGenCtrl2);\r
+\r
+ DelayIt (AdapterInfo, 50);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ Using the NIC data structure information, read the EEPROM to get a Word of data for the MAC address.\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+ @param Location Word offset into the MAC address to read.\r
+ @param AddrLen Number of bits of address length.\r
+\r
+ @retval RetVal The word read from the EEPROM.\r
+\r
+**/\r
+UINT16\r
+E100bReadEeprom (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN INT32 Location,\r
+ IN UINT8 AddrLen\r
+ )\r
+{\r
+ UINT16 RetVal;\r
+ UINT8 Tmp;\r
+\r
+ UINT32 EEAddr;\r
+ UINT16 ReadCmd;\r
+\r
+ EEAddr = AdapterInfo->ioaddr + SCBeeprom;\r
+ ReadCmd = (UINT16) (Location | (EE_READ_CMD << AddrLen));\r
+\r
+ RetVal = 0;\r
+\r
+ //\r
+ // get exclusive access to the eeprom first!\r
+ //\r
+ E100bSetEepromLockOut (AdapterInfo);\r
+\r
+ //\r
+ // eeprom control reg bits: x,x,x,x,DO,DI,CS,SK\r
+ // to write the opcode+data value out one bit at a time in DI starting at msb\r
+ // and then out a 1 to sk, wait, out 0 to SK and wait\r
+ // repeat this for all the bits to be written\r
+ //\r
+\r
+ //\r
+ // 11110010b\r
+ //\r
+ Tmp = (UINT8) (InByte (AdapterInfo, EEAddr) & 0xF2);\r
+ OutByte (AdapterInfo, (UINT8) (Tmp | EE_CS), EEAddr);\r
+\r
+ //\r
+ // 3 for the read opcode 110b\r
+ //\r
+ shift_bits_out (AdapterInfo, ReadCmd, (UINT8) (3 + AddrLen));\r
+\r
+ //\r
+ // read the eeprom word one bit at a time\r
+ //\r
+ RetVal = shift_bits_in (AdapterInfo);\r
+\r
+ //\r
+ // Terminate the EEPROM access and leave eeprom in a clean state.\r
+ //\r
+ Tmp = InByte (AdapterInfo, EEAddr);\r
+ Tmp &= ~(EE_CS | EE_DI);\r
+ OutByte (AdapterInfo, Tmp, EEAddr);\r
+\r
+ //\r
+ // raise the clock and lower the eeprom shift clock\r
+ //\r
+ OutByte (AdapterInfo, (UINT8) (Tmp | EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (100);\r
+\r
+ OutByte (AdapterInfo, (UINT8) (Tmp &~EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (100);\r
+\r
+ //\r
+ // giveup access to the eeprom\r
+ //\r
+ E100bReSetEepromLockOut (AdapterInfo);\r
+\r
+ return RetVal;\r
+}\r
+\r
+\r
+/**\r
+ Using the NIC data structure information, read the EEPROM to determine how many bits of address length\r
+ this EEPROM is in Words.\r
+\r
+ @param AdapterInfo Pointer to the NIC data structure\r
+ information which the UNDI driver is\r
+ layering on..\r
+\r
+ @retval RetVal The word read from the EEPROM.\r
+\r
+**/\r
+UINT8\r
+E100bGetEepromAddrLen (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT8 Tmp;\r
+ UINT8 AddrLen;\r
+ UINT32 EEAddr;\r
+ //\r
+ // assume 64word eeprom (so,6 bits of address_length)\r
+ //\r
+ UINT16 ReadCmd;\r
+\r
+ EEAddr = AdapterInfo->ioaddr + SCBeeprom;\r
+ ReadCmd = (EE_READ_CMD << 6);\r
+\r
+ //\r
+ // get exclusive access to the eeprom first!\r
+ //\r
+ E100bSetEepromLockOut (AdapterInfo);\r
+\r
+ //\r
+ // address we are trying to read is 0\r
+ // eeprom control reg bits: x,x,x,x,DO,,DI,,CS,SK\r
+ // to write the opcode+data value out one bit at a time in DI starting at msb\r
+ // and then out a 1 to sk, wait, out 0 to SK and wait\r
+ // repeat this for all the bits to be written\r
+ //\r
+ Tmp = (UINT8) (InByte (AdapterInfo, EEAddr) & 0xF2);\r
+\r
+ //\r
+ // enable eeprom access\r
+ //\r
+ OutByte (AdapterInfo, (UINT8) (Tmp | EE_CS), EEAddr);\r
+\r
+ //\r
+ // 3 for opcode, 6 for the default address len\r
+ //\r
+ shift_bits_out (AdapterInfo, ReadCmd, (UINT8) (3 + 6));\r
+\r
+ //\r
+ // (in case of a 64 word eeprom).\r
+ // read the "dummy zero" from EE_DO to say that the address we wrote\r
+ // (six 0s) is accepted, write more zeros (until 8) to get a "dummy zero"\r
+ //\r
+\r
+ //\r
+ // assume the smallest\r
+ //\r
+ AddrLen = 6;\r
+ Tmp = InByte (AdapterInfo, EEAddr);\r
+ while ((AddrLen < 8) && ((Tmp & EE_DO) != 0)) {\r
+ OutByte (AdapterInfo, (UINT8) (Tmp &~EE_DI), EEAddr);\r
+ eeprom_delay (100);\r
+\r
+ //\r
+ // raise the eeprom clock\r
+ //\r
+ OutByte (AdapterInfo, (UINT8) (Tmp | EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (150);\r
+\r
+ //\r
+ // lower the eeprom clock\r
+ //\r
+ OutByte (AdapterInfo, (UINT8) (Tmp &~EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (150);\r
+ Tmp = InByte (AdapterInfo, EEAddr);\r
+ AddrLen++;\r
+ }\r
+\r
+ //\r
+ // read the eeprom word, even though we don't need this\r
+ //\r
+ shift_bits_in (AdapterInfo);\r
+\r
+ //\r
+ // Terminate the EEPROM access.\r
+ //\r
+ Tmp = InByte (AdapterInfo, EEAddr);\r
+ Tmp &= ~(EE_CS | EE_DI);\r
+ OutByte (AdapterInfo, Tmp, EEAddr);\r
+\r
+ //\r
+ // raise the clock and lower the eeprom shift clock\r
+ //\r
+ OutByte (AdapterInfo, (UINT8) (Tmp | EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (100);\r
+\r
+ OutByte (AdapterInfo, (UINT8) (Tmp &~EE_SHIFT_CLK), EEAddr);\r
+ eeprom_delay (100);\r
+\r
+ //\r
+ // giveup access to the eeprom!\r
+ //\r
+ E100bReSetEepromLockOut (AdapterInfo);\r
+\r
+ return AddrLen;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+ @param DBaddr TODO: add argument description\r
+ @param DBsize TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINTN\r
+E100bStatistics (\r
+ NIC_DATA_INSTANCE *AdapterInfo,\r
+ UINT64 DBaddr,\r
+ UINT16 DBsize\r
+ )\r
+{\r
+ PXE_DB_STATISTICS db;\r
+ //\r
+ // wait upto one second (each wait is 100 micro s)\r
+ //\r
+ UINT32 Wait;\r
+ Wait = 10000;\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ //\r
+ // Clear statistics done marker.\r
+ //\r
+ AdapterInfo->statistics->done_marker = 0;\r
+\r
+ //\r
+ // Issue statistics dump (or dump w/ reset) command.\r
+ //\r
+ OutByte (\r
+ AdapterInfo,\r
+ (UINT8) (DBsize ? CU_SHOWSTATS : CU_DUMPSTATS),\r
+ (UINT32) (AdapterInfo->ioaddr + SCBCmd)\r
+ );\r
+\r
+ //\r
+ // Wait for command to complete.\r
+ //\r
+ // zero the db here just to chew up a little more time.\r
+ //\r
+\r
+ ZeroMem ((VOID *) &db, sizeof db);\r
+\r
+ while (Wait != 0) {\r
+ //\r
+ // Wait a bit before checking.\r
+ //\r
+\r
+ DelayIt (AdapterInfo, 100);\r
+\r
+ //\r
+ // Look for done marker at end of statistics.\r
+ //\r
+\r
+ switch (AdapterInfo->statistics->done_marker) {\r
+ case 0xA005:\r
+ case 0xA007:\r
+ break;\r
+\r
+ default:\r
+ Wait--;\r
+ continue;\r
+ }\r
+\r
+ //\r
+ // if we did not "continue" from the above switch, we are done,\r
+ //\r
+ break;\r
+ }\r
+\r
+ //\r
+ // If this is a reset, we are out of here!\r
+ //\r
+ if (DBsize == 0) {\r
+ return PXE_STATCODE_SUCCESS;\r
+ }\r
+\r
+ //\r
+ // Convert NIC statistics counter format to EFI/UNDI\r
+ // specification statistics counter format.\r
+ //\r
+\r
+ //\r
+ // 54 3210 fedc ba98 7654 3210\r
+ // db.Supported = 01 0000 0100 1101 0001 0111;\r
+ //\r
+ db.Supported = 0x104D17;\r
+\r
+ //\r
+ // Statistics from the NIC\r
+ //\r
+\r
+ db.Data[0x01] = AdapterInfo->statistics->rx_good_frames;\r
+\r
+ db.Data[0x02] = AdapterInfo->statistics->rx_runt_errs;\r
+\r
+ db.Data[0x08] = AdapterInfo->statistics->rx_crc_errs +\r
+ AdapterInfo->statistics->rx_align_errs;\r
+\r
+ db.Data[0x04] = db.Data[0x02] +\r
+ db.Data[0x08] +\r
+ AdapterInfo->statistics->rx_resource_errs +\r
+ AdapterInfo->statistics->rx_overrun_errs;\r
+\r
+ db.Data[0x00] = db.Data[0x01] + db.Data[0x04];\r
+\r
+ db.Data[0x0B] = AdapterInfo->statistics->tx_good_frames;\r
+\r
+ db.Data[0x0E] = AdapterInfo->statistics->tx_coll16_errs +\r
+ AdapterInfo->statistics->tx_late_colls +\r
+ AdapterInfo->statistics->tx_underruns +\r
+ AdapterInfo->statistics->tx_one_colls +\r
+ AdapterInfo->statistics->tx_multi_colls;\r
+\r
+ db.Data[0x14] = AdapterInfo->statistics->tx_total_colls;\r
+\r
+ db.Data[0x0A] = db.Data[0x0B] +\r
+ db.Data[0x0E] +\r
+ AdapterInfo->statistics->tx_lost_carrier;\r
+\r
+ if (DBsize > sizeof db) {\r
+ DBsize = sizeof db;\r
+ }\r
+\r
+ CopyMem ((VOID *) (UINTN) DBaddr, (VOID *) &db, (UINTN) DBsize);\r
+\r
+ return PXE_STATCODE_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+ @param OpFlags TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINTN\r
+E100bReset (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN INT32 OpFlags\r
+ )\r
+{\r
+\r
+ UINT16 save_filter;\r
+ //\r
+ // disable the interrupts\r
+ //\r
+ OutWord (AdapterInfo, INT_MASK, AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ //\r
+ // wait for the tx queue to complete\r
+ //\r
+ CheckCBList (AdapterInfo);\r
+\r
+ XmitWaitForCompletion (AdapterInfo);\r
+\r
+ if (AdapterInfo->Receive_Started) {\r
+ StopRU (AdapterInfo);\r
+ }\r
+\r
+ InitializeChip (AdapterInfo);\r
+\r
+ //\r
+ // check the opflags and restart receive filters\r
+ //\r
+ if ((OpFlags & PXE_OPFLAGS_RESET_DISABLE_FILTERS) == 0) {\r
+\r
+ save_filter = AdapterInfo->Rx_Filter;\r
+ //\r
+ // if we give the filter same as Rx_Filter,\r
+ // this routine will not set mcast list (it thinks there is no change)\r
+ // to force it, we will reset that flag in the Rx_Filter\r
+ //\r
+ AdapterInfo->Rx_Filter &= (~PXE_OPFLAGS_RECEIVE_FILTER_FILTERED_MULTICAST);\r
+ E100bSetfilter (AdapterInfo, save_filter, (UINT64) 0, (UINT32) 0);\r
+ }\r
+\r
+ if ((OpFlags & PXE_OPFLAGS_RESET_DISABLE_INTERRUPTS) != 0) {\r
+ //\r
+ // disable the interrupts\r
+ //\r
+ AdapterInfo->int_mask = 0;\r
+ }\r
+ //\r
+ // else leave the interrupt in the pre-set state!!!\r
+ //\r
+ E100bSetInterruptState (AdapterInfo);\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINTN\r
+E100bShutdown (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ //\r
+ // disable the interrupts\r
+ //\r
+ OutWord (AdapterInfo, INT_MASK, AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ //\r
+ // stop the receive unit\r
+ //\r
+ if (AdapterInfo->Receive_Started) {\r
+ StopRU (AdapterInfo);\r
+ }\r
+\r
+ //\r
+ // wait for the tx queue to complete\r
+ //\r
+ CheckCBList (AdapterInfo);\r
+ if (AdapterInfo->FreeCBCount != AdapterInfo->TxBufCnt) {\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+ }\r
+\r
+ //\r
+ // we do not want to reset the phy, it takes a long time to renegotiate the\r
+ // link after that (3-4 seconds)\r
+ //\r
+ InitializeChip (AdapterInfo);\r
+ SelectiveReset (AdapterInfo);\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ This routine will write a value to the specified MII register\r
+ of an external MDI compliant device (e.g. PHY 100). The command will\r
+ execute in polled mode.\r
+\r
+ @param AdapterInfo pointer to the structure that contains\r
+ the NIC's context.\r
+ @param RegAddress The MII register that we are writing to\r
+ @param PhyAddress The MDI address of the Phy component.\r
+ @param DataValue The value that we are writing to the MII\r
+ register.\r
+\r
+ @return nothing\r
+\r
+**/\r
+VOID\r
+MdiWrite (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT8 RegAddress,\r
+ IN UINT8 PhyAddress,\r
+ IN UINT16 DataValue\r
+ )\r
+{\r
+ UINT32 WriteCommand;\r
+\r
+ WriteCommand = ((UINT32) DataValue) |\r
+ ((UINT32)(RegAddress << 16)) |\r
+ ((UINT32)(PhyAddress << 21)) |\r
+ ((UINT32)(MDI_WRITE << 26));\r
+\r
+ //\r
+ // Issue the write command to the MDI control register.\r
+ //\r
+ OutLong (AdapterInfo, WriteCommand, AdapterInfo->ioaddr + SCBCtrlMDI);\r
+\r
+ //\r
+ // wait 20usec before checking status\r
+ //\r
+ DelayIt (AdapterInfo, 20);\r
+\r
+ //\r
+ // poll for the mdi write to complete\r
+ while ((InLong (AdapterInfo, AdapterInfo->ioaddr + SCBCtrlMDI) &\r
+ MDI_PHY_READY) == 0){\r
+ DelayIt (AdapterInfo, 20);\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ This routine will read a value from the specified MII register\r
+ of an external MDI compliant device (e.g. PHY 100), and return\r
+ it to the calling routine. The command will execute in polled mode.\r
+\r
+ @param AdapterInfo pointer to the structure that contains\r
+ the NIC's context.\r
+ @param RegAddress The MII register that we are reading from\r
+ @param PhyAddress The MDI address of the Phy component.\r
+ @param DataValue pointer to the value that we read from\r
+ the MII register.\r
+\r
+\r
+**/\r
+VOID\r
+MdiRead (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT8 RegAddress,\r
+ IN UINT8 PhyAddress,\r
+ IN OUT UINT16 *DataValue\r
+ )\r
+{\r
+ UINT32 ReadCommand;\r
+\r
+ ReadCommand = ((UINT32) (RegAddress << 16)) |\r
+ ((UINT32) (PhyAddress << 21)) |\r
+ ((UINT32) (MDI_READ << 26));\r
+\r
+ //\r
+ // Issue the read command to the MDI control register.\r
+ //\r
+ OutLong (AdapterInfo, ReadCommand, AdapterInfo->ioaddr + SCBCtrlMDI);\r
+\r
+ //\r
+ // wait 20usec before checking status\r
+ //\r
+ DelayIt (AdapterInfo, 20);\r
+\r
+ //\r
+ // poll for the mdi read to complete\r
+ //\r
+ while ((InLong (AdapterInfo, AdapterInfo->ioaddr + SCBCtrlMDI) &\r
+ MDI_PHY_READY) == 0) {\r
+ DelayIt (AdapterInfo, 20);\r
+\r
+ }\r
+\r
+ *DataValue = InWord (AdapterInfo, AdapterInfo->ioaddr + SCBCtrlMDI);\r
+}\r
+\r
+\r
+/**\r
+ This routine will reset the PHY that the adapter is currently\r
+ configured to use.\r
+\r
+ @param AdapterInfo pointer to the structure that contains\r
+ the NIC's context.\r
+\r
+\r
+**/\r
+VOID\r
+PhyReset (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT16 MdiControlReg;\r
+\r
+ MdiControlReg = (MDI_CR_AUTO_SELECT |\r
+ MDI_CR_RESTART_AUTO_NEG |\r
+ MDI_CR_RESET);\r
+\r
+ //\r
+ // Write the MDI control register with our new Phy configuration\r
+ //\r
+ MdiWrite (\r
+ AdapterInfo,\r
+ MDI_CONTROL_REG,\r
+ AdapterInfo->PhyAddress,\r
+ MdiControlReg\r
+ );\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ This routine will detect what phy we are using, set the line\r
+ speed, FDX or HDX, and configure the phy if necessary.\r
+ The following combinations are supported:\r
+ - TX or T4 PHY alone at PHY address 1\r
+ - T4 or TX PHY at address 1 and MII PHY at address 0\r
+ - 82503 alone (10Base-T mode, no full duplex support)\r
+ - 82503 and MII PHY (TX or T4) at address 0\r
+ The sequence / priority of detection is as follows:\r
+ - PHY 1 with cable termination\r
+ - PHY 0 with cable termination\r
+ - PHY 1 (if found) without cable termination\r
+ - 503 interface\r
+ Additionally auto-negotiation capable (NWAY) and parallel\r
+ detection PHYs are supported. The flow-chart is described in\r
+ the 82557 software writer's manual.\r
+ NOTE: 1. All PHY MDI registers are read in polled mode.\r
+ 2. The routines assume that the 82557 has been RESET and we have\r
+ obtained the virtual memory address of the CSR.\r
+ 3. PhyDetect will not RESET the PHY.\r
+ 4. If FORCEFDX is set, SPEED should also be set. The driver will\r
+ check the values for inconsistency with the detected PHY\r
+ technology.\r
+ 5. PHY 1 (the PHY on the adapter) may have an address in the range\r
+ 1 through 31 inclusive. The driver will accept addresses in\r
+ this range.\r
+ 6. Driver ignores FORCEFDX and SPEED overrides if a 503 interface\r
+ is detected.\r
+\r
+ @param AdapterInfo pointer to the structure that contains\r
+ the NIC's context.\r
+\r
+ @retval TRUE If a Phy was detected, and configured\r
+ correctly.\r
+ @retval FALSE If a valid phy could not be detected and\r
+ configured.\r
+\r
+**/\r
+BOOLEAN\r
+PhyDetect (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT16 *eedata;\r
+ UINT16 MdiControlReg;\r
+ UINT16 MdiStatusReg;\r
+ BOOLEAN FoundPhy1;\r
+ UINT8 ReNegotiateTime;\r
+\r
+ eedata = (UINT16 *) (&AdapterInfo->NVData[0]);\r
+\r
+ FoundPhy1 = FALSE;\r
+ ReNegotiateTime = 35;\r
+ //\r
+ // EEPROM word [6] contains the Primary PHY record in which the least 3 bits\r
+ // indicate the PHY address\r
+ // and word [7] contains the secondary PHY record\r
+ //\r
+ AdapterInfo->PhyRecord[0] = eedata[6];\r
+ AdapterInfo->PhyRecord[1] = eedata[7];\r
+ AdapterInfo->PhyAddress = (UINT8) (AdapterInfo->PhyRecord[0] & 7);\r
+\r
+ //\r
+ // Check for a phy address over-ride of 32 which indicates force use of 82503\r
+ // not detecting the link in this case\r
+ //\r
+ if (AdapterInfo->PhyAddress == 32) {\r
+ //\r
+ // 503 interface over-ride\r
+ // Record the current speed and duplex. We will be in half duplex\r
+ // mode unless the user used the force full duplex over-ride.\r
+ //\r
+ AdapterInfo->LinkSpeed = 10;\r
+ return (TRUE);\r
+ }\r
+\r
+ //\r
+ // If the Phy Address is between 1-31 then we must first look for phy 1,\r
+ // at that address.\r
+ //\r
+ if ((AdapterInfo->PhyAddress > 0) && (AdapterInfo->PhyAddress < 32)) {\r
+\r
+ //\r
+ // Read the MDI control and status registers at phy 1\r
+ // and check if we found a valid phy\r
+ //\r
+ MdiRead (\r
+ AdapterInfo,\r
+ MDI_CONTROL_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiControlReg\r
+ );\r
+\r
+ MdiRead (\r
+ AdapterInfo,\r
+ MDI_STATUS_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiStatusReg\r
+ );\r
+\r
+ if (!((MdiControlReg == 0xffff) ||\r
+ ((MdiStatusReg == 0) && (MdiControlReg == 0)))) {\r
+\r
+ //\r
+ // we have a valid phy1\r
+ // Read the status register again because of sticky bits\r
+ //\r
+ FoundPhy1 = TRUE;\r
+ MdiRead (\r
+ AdapterInfo,\r
+ MDI_STATUS_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiStatusReg\r
+ );\r
+\r
+ //\r
+ // If there is a valid link then use this Phy.\r
+ //\r
+ if (MdiStatusReg & MDI_SR_LINK_STATUS) {\r
+ return (SetupPhy(AdapterInfo));\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // Next try to detect a PHY at address 0x00 because there was no Phy 1,\r
+ // or Phy 1 didn't have link, or we had a phy 0 over-ride\r
+ //\r
+\r
+ //\r
+ // Read the MDI control and status registers at phy 0\r
+ //\r
+ MdiRead (AdapterInfo, MDI_CONTROL_REG, 0, &MdiControlReg);\r
+ MdiRead (AdapterInfo, MDI_STATUS_REG, 0, &MdiStatusReg);\r
+\r
+ //\r
+ // check if we found a valid phy 0\r
+ //\r
+ if (((MdiControlReg == 0xffff) ||\r
+ ((MdiStatusReg == 0) && (MdiControlReg == 0)))) {\r
+\r
+ //\r
+ // we don't have a valid phy at address 0\r
+ // if phy address was forced to 0, then error out because we\r
+ // didn't find a phy at that address\r
+ //\r
+ if (AdapterInfo->PhyAddress == 0x0000) {\r
+ return (FALSE);\r
+ } else {\r
+ //\r
+ // at this point phy1 does not have link and there is no phy 0 at all\r
+ // if we are forced to detect the cable, error out here!\r
+ //\r
+ if (AdapterInfo->CableDetect != 0) {\r
+ return FALSE;\r
+\r
+ }\r
+\r
+ if (FoundPhy1) {\r
+ //\r
+ // no phy 0, but there is a phy 1 (no link I guess), so use phy 1\r
+ //\r
+ return SetupPhy (AdapterInfo);\r
+ } else {\r
+ //\r
+ // didn't find phy 0 or phy 1, so assume a 503 interface\r
+ //\r
+ AdapterInfo->PhyAddress = 32;\r
+\r
+ //\r
+ // Record the current speed and duplex. We'll be in half duplex\r
+ // mode unless the user used the force full duplex over-ride.\r
+ //\r
+ AdapterInfo->LinkSpeed = 10;\r
+ return (TRUE);\r
+ }\r
+ }\r
+ } else {\r
+ //\r
+ // We have a valid phy at address 0. If phy 0 has a link then we use\r
+ // phy 0. If Phy 0 doesn't have a link then we use Phy 1 (no link)\r
+ // if phy 1 is present, or phy 0 if phy 1 is not present\r
+ // If phy 1 was present, then we must isolate phy 1 before we enable\r
+ // phy 0 to see if Phy 0 has a link.\r
+ //\r
+ if (FoundPhy1) {\r
+ //\r
+ // isolate phy 1\r
+ //\r
+ MdiWrite (\r
+ AdapterInfo,\r
+ MDI_CONTROL_REG,\r
+ AdapterInfo->PhyAddress,\r
+ MDI_CR_ISOLATE\r
+ );\r
+\r
+ //\r
+ // wait 100 microseconds for the phy to isolate.\r
+ //\r
+ DelayIt (AdapterInfo, 100);\r
+ }\r
+\r
+ //\r
+ // Since this Phy is at address 0, we must enable it. So clear\r
+ // the isolate bit, and set the auto-speed select bit\r
+ //\r
+ MdiWrite (\r
+ AdapterInfo,\r
+ MDI_CONTROL_REG,\r
+ 0,\r
+ MDI_CR_AUTO_SELECT\r
+ );\r
+\r
+ //\r
+ // wait 100 microseconds for the phy to be enabled.\r
+ //\r
+ DelayIt (AdapterInfo, 100);\r
+\r
+ //\r
+ // restart the auto-negotion process\r
+ //\r
+ MdiWrite (\r
+ AdapterInfo,\r
+ MDI_CONTROL_REG,\r
+ 0,\r
+ MDI_CR_RESTART_AUTO_NEG | MDI_CR_AUTO_SELECT\r
+ );\r
+\r
+ //\r
+ // wait no more than 3.5 seconds for auto-negotiation to complete\r
+ //\r
+ while (ReNegotiateTime) {\r
+ //\r
+ // Read the status register twice because of sticky bits\r
+ //\r
+ MdiRead (AdapterInfo, MDI_STATUS_REG, 0, &MdiStatusReg);\r
+ MdiRead (AdapterInfo, MDI_STATUS_REG, 0, &MdiStatusReg);\r
+\r
+ if (MdiStatusReg & MDI_SR_AUTO_NEG_COMPLETE) {\r
+ break;\r
+ }\r
+\r
+ DelayIt (AdapterInfo, 100);\r
+ ReNegotiateTime--;\r
+ }\r
+\r
+ //\r
+ // Read the status register again because of sticky bits\r
+ //\r
+ MdiRead (AdapterInfo, MDI_STATUS_REG, 0, &MdiStatusReg);\r
+\r
+ //\r
+ // If the link was not set\r
+ //\r
+ if ((MdiStatusReg & MDI_SR_LINK_STATUS) == 0) {\r
+ //\r
+ // PHY1 does not have a link and phy 0 does not have a link\r
+ // do not proceed if we need to detect the link!\r
+ //\r
+ if (AdapterInfo->CableDetect != 0) {\r
+ return FALSE;\r
+ }\r
+\r
+ //\r
+ // the link wasn't set, so use phy 1 if phy 1 was present\r
+ //\r
+ if (FoundPhy1) {\r
+ //\r
+ // isolate phy 0\r
+ //\r
+ MdiWrite (AdapterInfo, MDI_CONTROL_REG, 0, MDI_CR_ISOLATE);\r
+\r
+ //\r
+ // wait 100 microseconds for the phy to isolate.\r
+ //\r
+ DelayIt (AdapterInfo, 100);\r
+\r
+ //\r
+ // Now re-enable PHY 1\r
+ //\r
+ MdiWrite (\r
+ AdapterInfo,\r
+ MDI_CONTROL_REG,\r
+ AdapterInfo->PhyAddress,\r
+ MDI_CR_AUTO_SELECT\r
+ );\r
+\r
+ //\r
+ // wait 100 microseconds for the phy to be enabled\r
+ //\r
+ DelayIt (AdapterInfo, 100);\r
+\r
+ //\r
+ // restart the auto-negotion process\r
+ //\r
+ MdiWrite (\r
+ AdapterInfo,\r
+ MDI_CONTROL_REG,\r
+ AdapterInfo->PhyAddress,\r
+ MDI_CR_RESTART_AUTO_NEG | MDI_CR_AUTO_SELECT\r
+ );\r
+\r
+ //\r
+ // Don't wait for it to complete (we didn't have link earlier)\r
+ //\r
+ return (SetupPhy (AdapterInfo));\r
+ }\r
+ }\r
+\r
+ //\r
+ // Definitely using Phy 0\r
+ //\r
+ AdapterInfo->PhyAddress = 0;\r
+ return (SetupPhy(AdapterInfo));\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ This routine will setup phy 1 or phy 0 so that it is configured\r
+ to match a speed and duplex over-ride option. If speed or\r
+ duplex mode is not explicitly specified in the registry, the\r
+ driver will skip the speed and duplex over-ride code, and\r
+ assume the adapter is automatically setting the line speed, and\r
+ the duplex mode. At the end of this routine, any truly Phy\r
+ specific code will be executed (each Phy has its own quirks,\r
+ and some require that certain special bits are set).\r
+ NOTE: The driver assumes that SPEED and FORCEFDX are specified at the\r
+ same time. If FORCEDPX is set without speed being set, the driver\r
+ will encouter a fatal error and log a message into the event viewer.\r
+\r
+ @param AdapterInfo pointer to the structure that contains\r
+ the NIC's context.\r
+\r
+ @retval TRUE If the phy could be configured correctly\r
+ @retval FALSE If the phy couldn't be configured\r
+ correctly, because an unsupported\r
+ over-ride option was used\r
+\r
+**/\r
+BOOLEAN\r
+SetupPhy (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT16 MdiControlReg;\r
+ UINT16 MdiStatusReg;\r
+ UINT16 MdiIdLowReg;\r
+ UINT16 MdiIdHighReg;\r
+ UINT16 MdiMiscReg;\r
+ UINT32 PhyId;\r
+ BOOLEAN ForcePhySetting;\r
+\r
+ ForcePhySetting = FALSE;\r
+\r
+ //\r
+ // If we are NOT forcing a setting for line speed or full duplex, then\r
+ // we won't force a link setting, and we'll jump down to the phy\r
+ // specific code.\r
+ //\r
+ if (((AdapterInfo->LinkSpeedReq) || (AdapterInfo->DuplexReq))) {\r
+ //\r
+ // Find out what kind of technology this Phy is capable of.\r
+ //\r
+ MdiRead (\r
+ AdapterInfo,\r
+ MDI_STATUS_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiStatusReg\r
+ );\r
+\r
+ //\r
+ // Read the MDI control register at our phy\r
+ //\r
+ MdiRead (\r
+ AdapterInfo,\r
+ MDI_CONTROL_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiControlReg\r
+ );\r
+\r
+ //\r
+ // Now check the validity of our forced option. If the force option is\r
+ // valid, then force the setting. If the force option is not valid,\r
+ // we'll set a flag indicating that we should error out.\r
+ //\r
+\r
+ //\r
+ // If speed is forced to 10mb\r
+ //\r
+ if (AdapterInfo->LinkSpeedReq == 10) {\r
+ //\r
+ // If half duplex is forced\r
+ //\r
+ if ((AdapterInfo->DuplexReq & PXE_FORCE_HALF_DUPLEX) != 0) {\r
+ if (MdiStatusReg & MDI_SR_10T_HALF_DPX) {\r
+\r
+ MdiControlReg &= ~(MDI_CR_10_100 | MDI_CR_AUTO_SELECT | MDI_CR_FULL_HALF);\r
+ ForcePhySetting = TRUE;\r
+ }\r
+ } else if ((AdapterInfo->DuplexReq & PXE_FORCE_FULL_DUPLEX) != 0) {\r
+\r
+ //\r
+ // If full duplex is forced\r
+ //\r
+ if (MdiStatusReg & MDI_SR_10T_FULL_DPX) {\r
+\r
+ MdiControlReg &= ~(MDI_CR_10_100 | MDI_CR_AUTO_SELECT);\r
+ MdiControlReg |= MDI_CR_FULL_HALF;\r
+ ForcePhySetting = TRUE;\r
+ }\r
+ } else {\r
+ //\r
+ // If auto duplex (we actually set phy to 1/2)\r
+ //\r
+ if (MdiStatusReg & (MDI_SR_10T_FULL_DPX | MDI_SR_10T_HALF_DPX)) {\r
+\r
+ MdiControlReg &= ~(MDI_CR_10_100 | MDI_CR_AUTO_SELECT | MDI_CR_FULL_HALF);\r
+ ForcePhySetting = TRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ //\r
+ // If speed is forced to 100mb\r
+ //\r
+ else if (AdapterInfo->LinkSpeedReq == 100) {\r
+ //\r
+ // If half duplex is forced\r
+ //\r
+ if ((AdapterInfo->DuplexReq & PXE_FORCE_HALF_DUPLEX) != 0) {\r
+ if (MdiStatusReg & (MDI_SR_TX_HALF_DPX | MDI_SR_T4_CAPABLE)) {\r
+\r
+ MdiControlReg &= ~(MDI_CR_AUTO_SELECT | MDI_CR_FULL_HALF);\r
+ MdiControlReg |= MDI_CR_10_100;\r
+ ForcePhySetting = TRUE;\r
+ }\r
+ } else if ((AdapterInfo->DuplexReq & PXE_FORCE_FULL_DUPLEX) != 0) {\r
+ //\r
+ // If full duplex is forced\r
+ //\r
+ if (MdiStatusReg & MDI_SR_TX_FULL_DPX) {\r
+ MdiControlReg &= ~MDI_CR_AUTO_SELECT;\r
+ MdiControlReg |= (MDI_CR_10_100 | MDI_CR_FULL_HALF);\r
+ ForcePhySetting = TRUE;\r
+ }\r
+ } else {\r
+ //\r
+ // If auto duplex (we set phy to 1/2)\r
+ //\r
+ if (MdiStatusReg & (MDI_SR_TX_HALF_DPX | MDI_SR_T4_CAPABLE)) {\r
+\r
+ MdiControlReg &= ~(MDI_CR_AUTO_SELECT | MDI_CR_FULL_HALF);\r
+ MdiControlReg |= MDI_CR_10_100;\r
+ ForcePhySetting = TRUE;\r
+ }\r
+ }\r
+ }\r
+\r
+ if (!ForcePhySetting) {\r
+ return (FALSE);\r
+ }\r
+\r
+ //\r
+ // Write the MDI control register with our new Phy configuration\r
+ //\r
+ MdiWrite (\r
+ AdapterInfo,\r
+ MDI_CONTROL_REG,\r
+ AdapterInfo->PhyAddress,\r
+ MdiControlReg\r
+ );\r
+\r
+ //\r
+ // wait 100 milliseconds for auto-negotiation to complete\r
+ //\r
+ DelayIt (AdapterInfo, 100);\r
+ }\r
+\r
+ //\r
+ // Find out specifically what Phy this is. We do this because for certain\r
+ // phys there are specific bits that must be set so that the phy and the\r
+ // 82557 work together properly.\r
+ //\r
+\r
+ MdiRead (\r
+ AdapterInfo,\r
+ PHY_ID_REG_1,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiIdLowReg\r
+ );\r
+ MdiRead (\r
+ AdapterInfo,\r
+ PHY_ID_REG_2,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiIdHighReg\r
+ );\r
+\r
+ PhyId = ((UINT32) MdiIdLowReg | ((UINT32) MdiIdHighReg << 16));\r
+\r
+ //\r
+ // And out the revsion field of the Phy ID so that we'll be able to detect\r
+ // future revs of the same Phy.\r
+ //\r
+ PhyId &= PHY_MODEL_REV_ID_MASK;\r
+\r
+ //\r
+ // Handle the National TX\r
+ //\r
+ if (PhyId == PHY_NSC_TX) {\r
+\r
+ MdiRead (\r
+ AdapterInfo,\r
+ NSC_CONG_CONTROL_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiMiscReg\r
+ );\r
+\r
+ MdiMiscReg |= (NSC_TX_CONG_TXREADY | NSC_TX_CONG_F_CONNECT);\r
+\r
+ MdiWrite (\r
+ AdapterInfo,\r
+ NSC_CONG_CONTROL_REG,\r
+ AdapterInfo->PhyAddress,\r
+ MdiMiscReg\r
+ );\r
+ }\r
+\r
+ FindPhySpeedAndDpx (AdapterInfo, PhyId);\r
+\r
+ //\r
+ // We put a hardware fix on to our adapters to work-around the PHY_100 errata\r
+ // described below. The following code is only compiled in, if we wanted\r
+ // to attempt a software workaround to the PHY_100 A/B step problem.\r
+ //\r
+\r
+ return (TRUE);\r
+}\r
+\r
+\r
+/**\r
+ This routine will figure out what line speed and duplex mode\r
+ the PHY is currently using.\r
+\r
+ @param AdapterInfo pointer to the structure that contains\r
+ the NIC's context.\r
+ @param PhyId The ID of the PHY in question.\r
+\r
+ @return NOTHING\r
+\r
+**/\r
+VOID\r
+FindPhySpeedAndDpx (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT32 PhyId\r
+ )\r
+{\r
+ UINT16 MdiStatusReg;\r
+ UINT16 MdiMiscReg;\r
+ UINT16 MdiOwnAdReg;\r
+ UINT16 MdiLinkPartnerAdReg;\r
+\r
+ //\r
+ // If there was a speed and/or duplex override, then set our current\r
+ // value accordingly\r
+ //\r
+ AdapterInfo->LinkSpeed = AdapterInfo->LinkSpeedReq;\r
+ AdapterInfo->Duplex = (UINT8) ((AdapterInfo->DuplexReq & PXE_FORCE_FULL_DUPLEX) ?\r
+ FULL_DUPLEX : HALF_DUPLEX);\r
+\r
+ //\r
+ // If speed and duplex were forced, then we know our current settings, so\r
+ // we'll just return. Otherwise, we'll need to figure out what NWAY set\r
+ // us to.\r
+ //\r
+ if (AdapterInfo->LinkSpeed && AdapterInfo->Duplex) {\r
+ return ;\r
+\r
+ }\r
+ //\r
+ // If we didn't have a valid link, then we'll assume that our current\r
+ // speed is 10mb half-duplex.\r
+ //\r
+\r
+ //\r
+ // Read the status register twice because of sticky bits\r
+ //\r
+ MdiRead (\r
+ AdapterInfo,\r
+ MDI_STATUS_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiStatusReg\r
+ );\r
+ MdiRead (\r
+ AdapterInfo,\r
+ MDI_STATUS_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiStatusReg\r
+ );\r
+\r
+ //\r
+ // If there wasn't a valid link then use default speed & duplex\r
+ //\r
+ if (!(MdiStatusReg & MDI_SR_LINK_STATUS)) {\r
+\r
+ AdapterInfo->LinkSpeed = 10;\r
+ AdapterInfo->Duplex = HALF_DUPLEX;\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // If this is an Intel PHY (a T4 PHY_100 or a TX PHY_TX), then read bits\r
+ // 1 and 0 of extended register 0, to get the current speed and duplex\r
+ // settings.\r
+ //\r
+ if ((PhyId == PHY_100_A) || (PhyId == PHY_100_C) || (PhyId == PHY_TX_ID)) {\r
+ //\r
+ // Read extended register 0\r
+ //\r
+ MdiRead (\r
+ AdapterInfo,\r
+ EXTENDED_REG_0,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiMiscReg\r
+ );\r
+\r
+ //\r
+ // Get current speed setting\r
+ //\r
+ if (MdiMiscReg & PHY_100_ER0_SPEED_INDIC) {\r
+ AdapterInfo->LinkSpeed = 100;\r
+ } else {\r
+ AdapterInfo->LinkSpeed = 10;\r
+ }\r
+\r
+ //\r
+ // Get current duplex setting -- if bit is set then FDX is enabled\r
+ //\r
+ if (MdiMiscReg & PHY_100_ER0_FDX_INDIC) {\r
+ AdapterInfo->Duplex = FULL_DUPLEX;\r
+ } else {\r
+ AdapterInfo->Duplex = HALF_DUPLEX;\r
+ }\r
+\r
+ return ;\r
+ }\r
+ //\r
+ // Read our link partner's advertisement register\r
+ //\r
+ MdiRead (\r
+ AdapterInfo,\r
+ AUTO_NEG_LINK_PARTNER_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiLinkPartnerAdReg\r
+ );\r
+\r
+ //\r
+ // See if Auto-Negotiation was complete (bit 5, reg 1)\r
+ //\r
+ MdiRead (\r
+ AdapterInfo,\r
+ MDI_STATUS_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiStatusReg\r
+ );\r
+\r
+ //\r
+ // If a True NWAY connection was made, then we can detect speed/duplex by\r
+ // ANDing our adapter's advertised abilities with our link partner's\r
+ // advertised ablilities, and then assuming that the highest common\r
+ // denominator was chosed by NWAY.\r
+ //\r
+ if ((MdiLinkPartnerAdReg & NWAY_LP_ABILITY) &&\r
+ (MdiStatusReg & MDI_SR_AUTO_NEG_COMPLETE)) {\r
+\r
+ //\r
+ // Read our advertisement register\r
+ //\r
+ MdiRead (\r
+ AdapterInfo,\r
+ AUTO_NEG_ADVERTISE_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiOwnAdReg\r
+ );\r
+\r
+ //\r
+ // AND the two advertisement registers together, and get rid of any\r
+ // extraneous bits.\r
+ //\r
+ MdiOwnAdReg = (UINT16) (MdiOwnAdReg & (MdiLinkPartnerAdReg & NWAY_LP_ABILITY));\r
+\r
+ //\r
+ // Get speed setting\r
+ //\r
+ if (MdiOwnAdReg & (NWAY_AD_TX_HALF_DPX | NWAY_AD_TX_FULL_DPX | NWAY_AD_T4_CAPABLE)) {\r
+ AdapterInfo->LinkSpeed = 100;\r
+ } else {\r
+ AdapterInfo->LinkSpeed = 10;\r
+ }\r
+\r
+ //\r
+ // Get duplex setting -- use priority resolution algorithm\r
+ //\r
+ if (MdiOwnAdReg & (NWAY_AD_T4_CAPABLE)) {\r
+ AdapterInfo->Duplex = HALF_DUPLEX;\r
+ return ;\r
+ } else if (MdiOwnAdReg & (NWAY_AD_TX_FULL_DPX)) {\r
+ AdapterInfo->Duplex = FULL_DUPLEX;\r
+ return ;\r
+ } else if (MdiOwnAdReg & (NWAY_AD_TX_HALF_DPX)) {\r
+ AdapterInfo->Duplex = HALF_DUPLEX;\r
+ return ;\r
+ } else if (MdiOwnAdReg & (NWAY_AD_10T_FULL_DPX)) {\r
+ AdapterInfo->Duplex = FULL_DUPLEX;\r
+ return ;\r
+ } else {\r
+ AdapterInfo->Duplex = HALF_DUPLEX;\r
+ return ;\r
+ }\r
+ }\r
+\r
+ //\r
+ // If we are connected to a dumb (non-NWAY) repeater or hub, and the line\r
+ // speed was determined automatically by parallel detection, then we have\r
+ // no way of knowing exactly what speed the PHY is set to unless that PHY\r
+ // has a propietary register which indicates speed in this situation. The\r
+ // NSC TX PHY does have such a register. Also, since NWAY didn't establish\r
+ // the connection, the duplex setting should HALF duplex.\r
+ //\r
+ AdapterInfo->Duplex = HALF_DUPLEX;\r
+\r
+ if (PhyId == PHY_NSC_TX) {\r
+ //\r
+ // Read register 25 to get the SPEED_10 bit\r
+ //\r
+ MdiRead (\r
+ AdapterInfo,\r
+ NSC_SPEED_IND_REG,\r
+ AdapterInfo->PhyAddress,\r
+ &MdiMiscReg\r
+ );\r
+\r
+ //\r
+ // If bit 6 was set then we're at 10mb\r
+ //\r
+ if (MdiMiscReg & NSC_TX_SPD_INDC_SPEED) {\r
+ AdapterInfo->LinkSpeed = 10;\r
+ } else {\r
+ AdapterInfo->LinkSpeed = 100;\r
+ }\r
+ }\r
+\r
+ //\r
+ // If we don't know what line speed we are set at, then we'll default to\r
+ // 10mbs\r
+ //\r
+ else {\r
+ AdapterInfo->LinkSpeed = 10;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+VOID\r
+XmitWaitForCompletion (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ TxCB *TxPtr;\r
+\r
+ if (AdapterInfo->FreeCBCount == AdapterInfo->TxBufCnt) {\r
+ return ;\r
+ }\r
+\r
+ //\r
+ // used xmit cb list starts right after the free tail (ends before the\r
+ // free head ptr)\r
+ //\r
+ TxPtr = AdapterInfo->FreeTxTailPtr->NextTCBVirtualLinkPtr;\r
+ while (TxPtr != AdapterInfo->FreeTxHeadPtr) {\r
+ CommandWaitForCompletion (TxPtr, AdapterInfo);\r
+ SetFreeCB (AdapterInfo, TxPtr);\r
+ TxPtr = TxPtr->NextTCBVirtualLinkPtr;\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param cmd_ptr TODO: add argument description\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+INT8\r
+CommandWaitForCompletion (\r
+ TxCB *cmd_ptr,\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ INT16 wait;\r
+ wait = 5000;\r
+ while ((cmd_ptr->cb_header.status == 0) && (--wait > 0)) {\r
+ DelayIt (AdapterInfo, 10);\r
+ }\r
+\r
+ if (cmd_ptr->cb_header.status == 0) {\r
+ return -1;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+INT8\r
+SoftwareReset (\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT8 tco_stat;\r
+ UINT16 wait;\r
+\r
+ tco_stat = 0;\r
+\r
+ //\r
+ // Reset the chip: stop Tx and Rx processes and clear counters.\r
+ // This takes less than 10usec and will easily finish before the next\r
+ // action.\r
+ //\r
+\r
+ OutLong (AdapterInfo, PORT_RESET, AdapterInfo->ioaddr + SCBPort);\r
+ //\r
+ // wait for 5 milli seconds here!\r
+ //\r
+ DelayIt (AdapterInfo, 5000);\r
+ //\r
+ // TCO Errata work around for 559s only\r
+ // -----------------------------------------------------------------------------------\r
+ // TCO Workaround Code\r
+ // haifa workaround\r
+ // -----------------------------------------------------------------------------------\r
+ // 1. Issue SW-RST ^^^ (already done above)\r
+ // 2. Issue a redundant Set CU Base CMD immediately\r
+ // Do not set the General Pointer before the Set CU Base cycle\r
+ // Do not check the SCB CMD before the Set CU Base cycle\r
+ // 3. Wait for the SCB-CMD to be cleared\r
+ // this indicates the transition to post-driver\r
+ // 4. Poll the TCO-Req bit in the PMDR to be cleared\r
+ // this indicates the tco activity has stopped for real\r
+ // 5. Proceed with the nominal Driver Init:\r
+ // Actual Set CU & RU Base ...\r
+ //\r
+ // Check for ICH2 device ID. If this is an ICH2,\r
+ // do the TCO workaround code.\r
+ //\r
+ if (AdapterInfo->VendorID == D102_DEVICE_ID ||\r
+ AdapterInfo->VendorID == ICH3_DEVICE_ID_1 ||\r
+ AdapterInfo->VendorID == ICH3_DEVICE_ID_2 ||\r
+ AdapterInfo->VendorID == ICH3_DEVICE_ID_3 ||\r
+ AdapterInfo->VendorID == ICH3_DEVICE_ID_4 ||\r
+ AdapterInfo->VendorID == ICH3_DEVICE_ID_5 ||\r
+ AdapterInfo->VendorID == ICH3_DEVICE_ID_6 ||\r
+ AdapterInfo->VendorID == ICH3_DEVICE_ID_7 ||\r
+ AdapterInfo->VendorID == ICH3_DEVICE_ID_8 ||\r
+ AdapterInfo->RevID >= 8) { // do the TCO fix\r
+ //\r
+ // donot load the scb pointer but just give load_cu cmd.\r
+ //\r
+ OutByte (AdapterInfo, CU_CMD_BASE, AdapterInfo->ioaddr + SCBCmd);\r
+ //\r
+ // wait for command to be accepted.\r
+ //\r
+ wait_for_cmd_done (AdapterInfo->ioaddr + SCBCmd);\r
+ //\r
+ // read PMDR register and check bit 1 in it to see if TCO is active\r
+ //\r
+\r
+ //\r
+ // wait for 5 milli seconds\r
+ //\r
+ wait = 5000;\r
+ while (wait) {\r
+ tco_stat = InByte (AdapterInfo, AdapterInfo->ioaddr + 0x1b);\r
+ if ((tco_stat & 2) == 0) {\r
+ //\r
+ // is the activity bit clear??\r
+ //\r
+ break;\r
+ }\r
+\r
+ wait--;\r
+ DelayIt (AdapterInfo, 1);\r
+ }\r
+\r
+ if ((tco_stat & 2) != 0) {\r
+ //\r
+ // not zero??\r
+ //\r
+ return -1;\r
+ }\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT8\r
+SelectiveReset (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT16 wait;\r
+ UINT32 stat;\r
+\r
+ wait = 10;\r
+ stat = 0;\r
+ OutLong (AdapterInfo, POR_SELECTIVE_RESET, AdapterInfo->ioaddr + SCBPort);\r
+ //\r
+ // wait for this to complete\r
+ //\r
+\r
+ //\r
+ // wait for 2 milli seconds here!\r
+ //\r
+ DelayIt (AdapterInfo, 2000);\r
+ while (wait > 0) {\r
+ wait--;\r
+ stat = InLong (AdapterInfo, AdapterInfo->ioaddr + SCBPort);\r
+ if (stat == 0) {\r
+ break;\r
+ }\r
+\r
+ //\r
+ // wait for 1 milli second\r
+ //\r
+ DelayIt (AdapterInfo, 1000);\r
+ }\r
+\r
+ if (stat != 0) {\r
+ return PXE_STATCODE_DEVICE_FAILURE;\r
+ }\r
+\r
+ return 0;\r
+}\r
+\r
+\r
+/**\r
+ TODO: Add function description\r
+\r
+ @param AdapterInfo TODO: add argument description\r
+\r
+ @return TODO: add return values\r
+\r
+**/\r
+UINT16\r
+InitializeChip (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ UINT16 ret_val;\r
+ if (SoftwareReset (AdapterInfo) != 0) {\r
+ return PXE_STATCODE_DEVICE_FAILURE;\r
+ }\r
+\r
+ //\r
+ // disable interrupts\r
+ //\r
+ OutWord (AdapterInfo, INT_MASK, AdapterInfo->ioaddr + SCBCmd);\r
+\r
+ //\r
+ // Load the base registers with 0s (we will give the complete address as\r
+ // offset later when we issue any command\r
+ //\r
+ if ((ret_val = Load_Base_Regs (AdapterInfo)) != 0) {\r
+ return ret_val;\r
+ }\r
+\r
+ if ((ret_val = SetupCBlink (AdapterInfo)) != 0) {\r
+ return ret_val;\r
+ }\r
+\r
+ if ((ret_val = SetupReceiveQueues (AdapterInfo)) != 0) {\r
+ return ret_val;\r
+ }\r
+\r
+ //\r
+ // detect the PHY only if we need to detect the cable as requested by the\r
+ // initialize parameters\r
+ //\r
+ AdapterInfo->PhyAddress = 0xFF;\r
+\r
+ if (AdapterInfo->CableDetect != 0) {\r
+ if (!PhyDetect (AdapterInfo)) {\r
+ return PXE_STATCODE_DEVICE_FAILURE;\r
+ }\r
+ }\r
+\r
+ if ((ret_val = E100bSetupIAAddr (AdapterInfo)) != 0) {\r
+ return ret_val;\r
+ }\r
+\r
+ if ((ret_val = Configure (AdapterInfo)) != 0) {\r
+ return ret_val;\r
+ }\r
+\r
+ return 0;\r
+}\r
--- /dev/null
+/** @file\r
+ Definitions for network adapter card.\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _E100B_H_\r
+#define _E100B_H_\r
+\r
+// pci config offsets:\r
+\r
+#define RX_BUFFER_COUNT 32\r
+#define TX_BUFFER_COUNT 32\r
+\r
+#define PCI_VENDOR_ID_INTEL 0x8086\r
+#define PCI_DEVICE_ID_INTEL_82557 0x1229\r
+#define D100_VENDOR_ID 0x8086\r
+#define D100_DEVICE_ID 0x1229\r
+#define D102_DEVICE_ID 0x2449\r
+\r
+#define ICH3_DEVICE_ID_1 0x1031\r
+#define ICH3_DEVICE_ID_2 0x1032\r
+#define ICH3_DEVICE_ID_3 0x1033\r
+#define ICH3_DEVICE_ID_4 0x1034\r
+#define ICH3_DEVICE_ID_5 0x1035\r
+#define ICH3_DEVICE_ID_6 0x1036\r
+#define ICH3_DEVICE_ID_7 0x1037\r
+#define ICH3_DEVICE_ID_8 0x1038\r
+\r
+#define SPEEDO_DEVICE_ID 0x1227\r
+#define SPLASH1_DEVICE_ID 0x1226\r
+\r
+\r
+// bit fields for the command\r
+#define PCI_COMMAND_MASTER 0x04 // bit 2\r
+#define PCI_COMMAND_IO 0x01 // bit 0\r
+#define PCI_COMMAND 0x04\r
+#define PCI_LATENCY_TIMER 0x0D\r
+\r
+#define ETHER_MAC_ADDR_LEN 6\r
+#ifdef AVL_XXX\r
+#define ETHER_HEADER_LEN 14\r
+// media interface type\r
+// #define INTERFACE_TYPE "\r
+\r
+// Hardware type values\r
+#define HW_ETHER_TYPE 1\r
+#define HW_EXPERIMENTAL_ETHER_TYPE 2\r
+#define HW_IEEE_TYPE 6\r
+#define HW_ARCNET_TYPE 7\r
+\r
+#endif // AVL_XXX\r
+\r
+#define MAX_ETHERNET_PKT_SIZE 1514 // including eth header\r
+#define RX_BUFFER_SIZE 1536 // including crc and padding\r
+#define TX_BUFFER_SIZE 64\r
+#define ETH_MTU 1500 // does not include ethernet header length\r
+\r
+#define SPEEDO3_TOTAL_SIZE 0x20\r
+\r
+#pragma pack(1)\r
+\r
+typedef struct eth {\r
+ UINT8 dest_addr[PXE_HWADDR_LEN_ETHER];\r
+ UINT8 src_addr[PXE_HWADDR_LEN_ETHER];\r
+ UINT16 type;\r
+} EtherHeader;\r
+\r
+#pragma pack(1)\r
+typedef struct CONFIG_HEADER {\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 Command;\r
+ UINT16 Status;\r
+ UINT16 RevID;\r
+ UINT16 ClassID;\r
+ UINT8 CacheLineSize;\r
+ UINT8 LatencyTimer;\r
+ UINT8 HeaderType; // must be zero to impose this structure...\r
+ UINT8 BIST; // built-in self test\r
+ UINT32 BaseAddressReg_0; // memory mapped address\r
+ UINT32 BaseAddressReg_1; //io mapped address, Base IO address\r
+ UINT32 BaseAddressReg_2; // option rom address\r
+ UINT32 BaseAddressReg_3;\r
+ UINT32 BaseAddressReg_4;\r
+ UINT32 BaseAddressReg_5;\r
+ UINT32 CardBusCISPtr;\r
+ UINT16 SubVendorID;\r
+ UINT16 SubSystemID;\r
+ UINT32 ExpansionROMBaseAddr;\r
+ UINT8 CapabilitiesPtr;\r
+ UINT8 reserved1;\r
+ UINT16 Reserved2;\r
+ UINT32 Reserved3;\r
+ UINT8 int_line;\r
+ UINT8 int_pin;\r
+ UINT8 Min_gnt;\r
+ UINT8 Max_lat;\r
+} PCI_CONFIG_HEADER;\r
+#pragma pack()\r
+\r
+//-------------------------------------------------------------------------\r
+// Offsets to the various registers.\r
+// All accesses need not be longword aligned.\r
+//-------------------------------------------------------------------------\r
+enum speedo_offsets {\r
+ SCBStatus = 0, SCBCmd = 2, // Rx/Command Unit command and status.\r
+ SCBPointer = 4, // General purpose pointer.\r
+ SCBPort = 8, // Misc. commands and operands.\r
+ SCBflash = 12, SCBeeprom = 14, // EEPROM and flash memory control.\r
+ SCBCtrlMDI = 16, // MDI interface control.\r
+ SCBEarlyRx = 20, // Early receive byte count.\r
+ SCBEarlyRxInt = 24, SCBFlowCtrlReg = 25, SCBPmdr = 27,\r
+ // offsets for general control registers (GCRs)\r
+ SCBGenCtrl = 28, SCBGenStatus = 29, SCBGenCtrl2 = 30, SCBRsvd = 31\r
+};\r
+\r
+#define GCR2_EEPROM_ACCESS_SEMAPHORE 0x80 // bit offset into the gcr2\r
+\r
+//-------------------------------------------------------------------------\r
+// Action commands - Commands that can be put in a command list entry.\r
+//-------------------------------------------------------------------------\r
+enum commands {\r
+ CmdNOp = 0, CmdIASetup = 1, CmdConfigure = 2, CmdMulticastList = 3,\r
+ CmdTx = 4, CmdTDR = 5, CmdDump = 6, CmdDiagnose = 7,\r
+ CmdSuspend = 0x4000, /* Suspend after completion. */\r
+ CmdIntr = 0x2000, /* Interrupt after completion. */\r
+ CmdTxFlex = 0x0008 /* Use "Flexible mode" for CmdTx command. */\r
+};\r
+\r
+//-------------------------------------------------------------------------\r
+// port commands\r
+//-------------------------------------------------------------------------\r
+#define PORT_RESET 0\r
+#define PORT_SELF_TEST 1\r
+#define POR_SELECTIVE_RESET 2\r
+#define PORT_DUMP_POINTER 2\r
+\r
+//-------------------------------------------------------------------------\r
+// SCB Command Word bit definitions\r
+//-------------------------------------------------------------------------\r
+//- CUC fields\r
+#define CU_START 0x0010\r
+#define CU_RESUME 0x0020\r
+#define CU_STATSADDR 0x0040\r
+#define CU_SHOWSTATS 0x0050 /* Dump statistics counters. */\r
+#define CU_CMD_BASE 0x0060 /* Base address to add to add CU commands. */\r
+#define CU_DUMPSTATS 0x0070 /* Dump then reset stats counters. */\r
+\r
+//- RUC fields\r
+#define RX_START 0x0001\r
+#define RX_RESUME 0x0002\r
+#define RX_ABORT 0x0004\r
+#define RX_ADDR_LOAD 0x0006 /* load ru_base_reg */\r
+#define RX_RESUMENR 0x0007\r
+\r
+// Interrupt fields (assuming byte addressing)\r
+#define INT_MASK 0x0100\r
+#define DRVR_INT 0x0200 /* Driver generated interrupt. */\r
+\r
+//- CB Status Word\r
+#define CMD_STATUS_COMPLETE 0x8000\r
+#define RX_STATUS_COMPLETE 0x8000\r
+#define CMD_STATUS_MASK 0xF000\r
+\r
+//-------------------------------------------------------------------------\r
+//- SCB Status bits:\r
+// Interrupts are ACKed by writing to the upper 6 interrupt bits\r
+//-------------------------------------------------------------------------\r
+#define SCB_STATUS_MASK 0xFC00 // bits 2-7 - STATUS/ACK Mask\r
+#define SCB_STATUS_CX_TNO 0x8000 // BIT_15 - CX or TNO Interrupt\r
+#define SCB_STATUS_FR 0x4000 // BIT_14 - FR Interrupt\r
+#define SCB_STATUS_CNA 0x2000 // BIT_13 - CNA Interrupt\r
+#define SCB_STATUS_RNR 0x1000 // BIT_12 - RNR Interrupt\r
+#define SCB_STATUS_MDI 0x0800 // BIT_11 - MDI R/W Done Interrupt\r
+#define SCB_STATUS_SWI 0x0400 // BIT_10 - SWI Interrupt\r
+\r
+// CU STATUS: bits 6 & 7\r
+#define SCB_STATUS_CU_MASK 0x00C0 // bits 6 & 7\r
+#define SCB_STATUS_CU_IDLE 0x0000 // 00\r
+#define SCB_STATUS_CU_SUSPEND 0x0040 // 01\r
+#define SCB_STATUS_CU_ACTIVE 0x0080 // 10\r
+\r
+// RU STATUS: bits 2-5\r
+#define SCB_RUS_IDLE 0x0000\r
+#define SCB_RUS_SUSPENDED 0x0004 // bit 2\r
+#define SCB_RUS_NO_RESOURCES 0x0008 // bit 3\r
+#define SCB_RUS_READY 0x0010 // bit 4\r
+\r
+//-------------------------------------------------------------------------\r
+// Bit Mask definitions\r
+//-------------------------------------------------------------------------\r
+#define BIT_0 0x0001\r
+#define BIT_1 0x0002\r
+#define BIT_2 0x0004\r
+#define BIT_3 0x0008\r
+#define BIT_4 0x0010\r
+#define BIT_5 0x0020\r
+#define BIT_6 0x0040\r
+#define BIT_7 0x0080\r
+#define BIT_8 0x0100\r
+#define BIT_9 0x0200\r
+#define BIT_10 0x0400\r
+#define BIT_11 0x0800\r
+#define BIT_12 0x1000\r
+#define BIT_13 0x2000\r
+#define BIT_14 0x4000\r
+#define BIT_15 0x8000\r
+#define BIT_24 0x01000000\r
+#define BIT_28 0x10000000\r
+\r
+\r
+//-------------------------------------------------------------------------\r
+// MDI Control register bit definitions\r
+//-------------------------------------------------------------------------\r
+#define MDI_DATA_MASK BIT_0_15 // MDI Data port\r
+#define MDI_REG_ADDR BIT_16_20 // which MDI register to read/write\r
+#define MDI_PHY_ADDR BIT_21_25 // which PHY to read/write\r
+#define MDI_PHY_OPCODE BIT_26_27 // which PHY to read/write\r
+#define MDI_PHY_READY BIT_28 // PHY is ready for another MDI cycle\r
+#define MDI_PHY_INT_ENABLE BIT_29 // Assert INT at MDI cycle completion\r
+\r
+#define BIT_0_2 0x0007\r
+#define BIT_0_3 0x000F\r
+#define BIT_0_4 0x001F\r
+#define BIT_0_5 0x003F\r
+#define BIT_0_6 0x007F\r
+#define BIT_0_7 0x00FF\r
+#define BIT_0_8 0x01FF\r
+#define BIT_0_13 0x3FFF\r
+#define BIT_0_15 0xFFFF\r
+#define BIT_1_2 0x0006\r
+#define BIT_1_3 0x000E\r
+#define BIT_2_5 0x003C\r
+#define BIT_3_4 0x0018\r
+#define BIT_4_5 0x0030\r
+#define BIT_4_6 0x0070\r
+#define BIT_4_7 0x00F0\r
+#define BIT_5_7 0x00E0\r
+#define BIT_5_9 0x03E0\r
+#define BIT_5_12 0x1FE0\r
+#define BIT_5_15 0xFFE0\r
+#define BIT_6_7 0x00c0\r
+#define BIT_7_11 0x0F80\r
+#define BIT_8_10 0x0700\r
+#define BIT_9_13 0x3E00\r
+#define BIT_12_15 0xF000\r
+\r
+#define BIT_16_20 0x001F0000\r
+#define BIT_21_25 0x03E00000\r
+#define BIT_26_27 0x0C000000\r
+\r
+//-------------------------------------------------------------------------\r
+// MDI Control register opcode definitions\r
+//-------------------------------------------------------------------------\r
+#define MDI_WRITE 1 // Phy Write\r
+#define MDI_READ 2 // Phy read\r
+\r
+//-------------------------------------------------------------------------\r
+// PHY 100 MDI Register/Bit Definitions\r
+//-------------------------------------------------------------------------\r
+// MDI register set\r
+#define MDI_CONTROL_REG 0x00 // MDI control register\r
+#define MDI_STATUS_REG 0x01 // MDI Status regiser\r
+#define PHY_ID_REG_1 0x02 // Phy indentification reg (word 1)\r
+#define PHY_ID_REG_2 0x03 // Phy indentification reg (word 2)\r
+#define AUTO_NEG_ADVERTISE_REG 0x04 // Auto-negotiation advertisement\r
+#define AUTO_NEG_LINK_PARTNER_REG 0x05 // Auto-negotiation link partner ability\r
+#define AUTO_NEG_EXPANSION_REG 0x06 // Auto-negotiation expansion\r
+#define AUTO_NEG_NEXT_PAGE_REG 0x07 // Auto-negotiation next page transmit\r
+#define EXTENDED_REG_0 0x10 // Extended reg 0 (Phy 100 modes)\r
+#define EXTENDED_REG_1 0x14 // Extended reg 1 (Phy 100 error indications)\r
+#define NSC_CONG_CONTROL_REG 0x17 // National (TX) congestion control\r
+#define NSC_SPEED_IND_REG 0x19 // National (TX) speed indication\r
+\r
+// MDI Control register bit definitions\r
+#define MDI_CR_COLL_TEST_ENABLE BIT_7 // Collision test enable\r
+#define MDI_CR_FULL_HALF BIT_8 // FDX =1, half duplex =0\r
+#define MDI_CR_RESTART_AUTO_NEG BIT_9 // Restart auto negotiation\r
+#define MDI_CR_ISOLATE BIT_10 // Isolate PHY from MII\r
+#define MDI_CR_POWER_DOWN BIT_11 // Power down\r
+#define MDI_CR_AUTO_SELECT BIT_12 // Auto speed select enable\r
+#define MDI_CR_10_100 BIT_13 // 0 = 10Mbs, 1 = 100Mbs\r
+#define MDI_CR_LOOPBACK BIT_14 // 0 = normal, 1 = loopback\r
+#define MDI_CR_RESET BIT_15 // 0 = normal, 1 = PHY reset\r
+\r
+// MDI Status register bit definitions\r
+#define MDI_SR_EXT_REG_CAPABLE BIT_0 // Extended register capabilities\r
+#define MDI_SR_JABBER_DETECT BIT_1 // Jabber detected\r
+#define MDI_SR_LINK_STATUS BIT_2 // Link Status -- 1 = link\r
+#define MDI_SR_AUTO_SELECT_CAPABLE BIT_3 // Auto speed select capable\r
+#define MDI_SR_REMOTE_FAULT_DETECT BIT_4 // Remote fault detect\r
+#define MDI_SR_AUTO_NEG_COMPLETE BIT_5 // Auto negotiation complete\r
+#define MDI_SR_10T_HALF_DPX BIT_11 // 10BaseT Half Duplex capable\r
+#define MDI_SR_10T_FULL_DPX BIT_12 // 10BaseT full duplex capable\r
+#define MDI_SR_TX_HALF_DPX BIT_13 // TX Half Duplex capable\r
+#define MDI_SR_TX_FULL_DPX BIT_14 // TX full duplex capable\r
+#define MDI_SR_T4_CAPABLE BIT_15 // T4 capable\r
+\r
+// Auto-Negotiation advertisement register bit definitions\r
+#define NWAY_AD_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r
+#define NWAY_AD_ABILITY BIT_5_12 // technologies that are supported\r
+#define NWAY_AD_10T_HALF_DPX BIT_5 // 10BaseT Half Duplex capable\r
+#define NWAY_AD_10T_FULL_DPX BIT_6 // 10BaseT full duplex capable\r
+#define NWAY_AD_TX_HALF_DPX BIT_7 // TX Half Duplex capable\r
+#define NWAY_AD_TX_FULL_DPX BIT_8 // TX full duplex capable\r
+#define NWAY_AD_T4_CAPABLE BIT_9 // T4 capable\r
+#define NWAY_AD_REMOTE_FAULT BIT_13 // indicates local remote fault\r
+#define NWAY_AD_RESERVED BIT_14 // reserved\r
+#define NWAY_AD_NEXT_PAGE BIT_15 // Next page (not supported)\r
+\r
+// Auto-Negotiation link partner ability register bit definitions\r
+#define NWAY_LP_SELCTOR_FIELD BIT_0_4 // identifies supported protocol\r
+#define NWAY_LP_ABILITY BIT_5_9 // technologies that are supported\r
+#define NWAY_LP_REMOTE_FAULT BIT_13 // indicates partner remote fault\r
+#define NWAY_LP_ACKNOWLEDGE BIT_14 // acknowledge\r
+#define NWAY_LP_NEXT_PAGE BIT_15 // Next page (not supported)\r
+\r
+// Auto-Negotiation expansion register bit definitions\r
+#define NWAY_EX_LP_NWAY BIT_0 // link partner is NWAY\r
+#define NWAY_EX_PAGE_RECEIVED BIT_1 // link code word received\r
+#define NWAY_EX_NEXT_PAGE_ABLE BIT_2 // local is next page able\r
+#define NWAY_EX_LP_NEXT_PAGE_ABLE BIT_3 // partner is next page able\r
+#define NWAY_EX_PARALLEL_DET_FLT BIT_4 // parallel detection fault\r
+#define NWAY_EX_RESERVED BIT_5_15 // reserved\r
+\r
+\r
+// PHY 100 Extended Register 0 bit definitions\r
+#define PHY_100_ER0_FDX_INDIC BIT_0 // 1 = FDX, 0 = half duplex\r
+#define PHY_100_ER0_SPEED_INDIC BIT_1 // 1 = 100mbs, 0= 10mbs\r
+#define PHY_100_ER0_WAKE_UP BIT_2 // Wake up DAC\r
+#define PHY_100_ER0_RESERVED BIT_3_4 // Reserved\r
+#define PHY_100_ER0_REV_CNTRL BIT_5_7 // Revsion control (A step = 000)\r
+#define PHY_100_ER0_FORCE_FAIL BIT_8 // Force Fail is enabled\r
+#define PHY_100_ER0_TEST BIT_9_13 // Revsion control (A step = 000)\r
+#define PHY_100_ER0_LINKDIS BIT_14 // Link integrity test is disabled\r
+#define PHY_100_ER0_JABDIS BIT_15 // Jabber function is disabled\r
+\r
+\r
+// PHY 100 Extended Register 1 bit definitions\r
+#define PHY_100_ER1_RESERVED BIT_0_8 // Reserved\r
+#define PHY_100_ER1_CH2_DET_ERR BIT_9 // Channel 2 EOF detection error\r
+#define PHY_100_ER1_MANCH_CODE_ERR BIT_10 // Manchester code error\r
+#define PHY_100_ER1_EOP_ERR BIT_11 // EOP error\r
+#define PHY_100_ER1_BAD_CODE_ERR BIT_12 // bad code error\r
+#define PHY_100_ER1_INV_CODE_ERR BIT_13 // invalid code error\r
+#define PHY_100_ER1_DC_BAL_ERR BIT_14 // DC balance error\r
+#define PHY_100_ER1_PAIR_SKEW_ERR BIT_15 // Pair skew error\r
+\r
+// National Semiconductor TX phy congestion control register bit definitions\r
+#define NSC_TX_CONG_TXREADY BIT_10 // Makes TxReady an input\r
+#define NSC_TX_CONG_ENABLE BIT_8 // Enables congestion control\r
+#define NSC_TX_CONG_F_CONNECT BIT_5 // Enables congestion control\r
+\r
+// National Semiconductor TX phy speed indication register bit definitions\r
+#define NSC_TX_SPD_INDC_SPEED BIT_6 // 0 = 100mb, 1=10mb\r
+\r
+//-------------------------------------------------------------------------\r
+// Phy related constants\r
+//-------------------------------------------------------------------------\r
+#define PHY_503 0\r
+#define PHY_100_A 0x000003E0\r
+#define PHY_100_C 0x035002A8\r
+#define PHY_TX_ID 0x015002A8\r
+#define PHY_NSC_TX 0x5c002000\r
+#define PHY_OTHER 0xFFFF\r
+\r
+#define PHY_MODEL_REV_ID_MASK 0xFFF0FFFF\r
+#define PARALLEL_DETECT 0\r
+#define N_WAY 1\r
+\r
+#define RENEGOTIATE_TIME 35 // (3.5 Seconds)\r
+\r
+#define CONNECTOR_AUTO 0\r
+#define CONNECTOR_TPE 1\r
+#define CONNECTOR_MII 2\r
+\r
+//-------------------------------------------------------------------------\r
+\r
+/* The Speedo3 Rx and Tx frame/buffer descriptors. */\r
+#pragma pack(1)\r
+struct CB_Header { /* A generic descriptor. */\r
+ UINT16 status; /* Offset 0. */\r
+ UINT16 command; /* Offset 2. */\r
+ UINT32 link; /* struct descriptor * */\r
+};\r
+\r
+/* transmit command block structure */\r
+#pragma pack(1)\r
+typedef struct s_TxCB {\r
+ struct CB_Header cb_header;\r
+ UINT32 PhysTBDArrayAddres; /* address of an array that contains\r
+ physical TBD pointers */\r
+ UINT16 ByteCount; /* immediate data count = 0 always */\r
+ UINT8 Threshold;\r
+ UINT8 TBDCount;\r
+ UINT8 ImmediateData[TX_BUFFER_SIZE];\r
+ /* following fields are not seen by the 82557 */\r
+ struct TBD {\r
+ UINT32 phys_buf_addr;\r
+ UINT32 buf_len;\r
+ } TBDArray[MAX_XMIT_FRAGMENTS];\r
+ UINT32 PhysArrayAddr; /* in case the one in the header is lost */\r
+ UINT32 PhysTCBAddress; /* for this TCB */\r
+ struct s_TxCB *NextTCBVirtualLinkPtr;\r
+ struct s_TxCB *PrevTCBVirtualLinkPtr;\r
+ UINT64 free_data_ptr; // to be given to the upper layer when this xmit completes1\r
+}TxCB;\r
+\r
+/* The Speedo3 Rx and Tx buffer descriptors. */\r
+#pragma pack(1)\r
+typedef struct s_RxFD { /* Receive frame descriptor. */\r
+ struct CB_Header cb_header;\r
+ UINT32 rx_buf_addr; /* VOID * */\r
+ UINT16 ActualCount;\r
+ UINT16 RFDSize;\r
+ UINT8 RFDBuffer[RX_BUFFER_SIZE];\r
+ UINT8 forwarded;\r
+ UINT8 junk[3];\r
+}RxFD;\r
+\r
+/* Elements of the RxFD.status word. */\r
+#define RX_COMPLETE 0x8000\r
+#define RX_FRAME_OK 0x2000\r
+\r
+/* Elements of the dump_statistics block. This block must be lword aligned. */\r
+#pragma pack(1)\r
+struct speedo_stats {\r
+ UINT32 tx_good_frames;\r
+ UINT32 tx_coll16_errs;\r
+ UINT32 tx_late_colls;\r
+ UINT32 tx_underruns;\r
+ UINT32 tx_lost_carrier;\r
+ UINT32 tx_deferred;\r
+ UINT32 tx_one_colls;\r
+ UINT32 tx_multi_colls;\r
+ UINT32 tx_total_colls;\r
+ UINT32 rx_good_frames;\r
+ UINT32 rx_crc_errs;\r
+ UINT32 rx_align_errs;\r
+ UINT32 rx_resource_errs;\r
+ UINT32 rx_overrun_errs;\r
+ UINT32 rx_colls_errs;\r
+ UINT32 rx_runt_errs;\r
+ UINT32 done_marker;\r
+};\r
+#pragma pack()\r
+\r
+\r
+struct Krn_Mem{\r
+ RxFD rx_ring[RX_BUFFER_COUNT];\r
+ TxCB tx_ring[TX_BUFFER_COUNT];\r
+ struct speedo_stats statistics;\r
+};\r
+#define MEMORY_NEEDED sizeof(struct Krn_Mem)\r
+\r
+/* The parameters for a CmdConfigure operation.\r
+ There are so many options that it would be difficult to document each bit.\r
+ We mostly use the default or recommended settings.\r
+*/\r
+\r
+/*\r
+ *--------------------------------------------------------------------------\r
+ * Configuration CB Parameter Bit Definitions\r
+ *--------------------------------------------------------------------------\r
+ */\r
+// - Byte 0 (Default Value = 16h)\r
+#define CFIG_BYTE_COUNT 0x16 // 22 Configuration Bytes\r
+\r
+//- Byte 1 (Default Value = 88h)\r
+#define CFIG_TXRX_FIFO_LIMIT 0x88\r
+\r
+//- Byte 2 (Default Value = 0)\r
+#define CFIG_ADAPTIVE_IFS 0\r
+\r
+//- Byte 3 (Default Value = 0, ALWAYS. This byte is RESERVED)\r
+#define CFIG_RESERVED 0\r
+\r
+//- Byte 4 (Default Value = 0. Default implies that Rx DMA cannot be\r
+//- preempted).\r
+#define CFIG_RXDMA_BYTE_COUNT 0\r
+\r
+//- Byte 5 (Default Value = 80h. Default implies that Tx DMA cannot be\r
+//- preempted. However, setting these counters is enabled.)\r
+#define CFIG_DMBC_ENABLE 0x80\r
+\r
+//- Byte 6 (Default Value = 33h. Late SCB enabled, No TNO interrupts,\r
+//- CNA interrupts and do not save bad frames.)\r
+#define CFIG_LATE_SCB 1 // BIT 0\r
+#define CFIG_TNO_INTERRUPT 0x4 // BIT 2\r
+#define CFIG_CI_INTERRUPT 0x8 // BIT 3\r
+#define CFIG_SAVE_BAD_FRAMES 0x80 // BIT_7\r
+\r
+//- Byte 7 (Default Value = 7h. Discard short frames automatically and\r
+//- attempt upto 3 retries on transmit.)\r
+#define CFIG_DISCARD_SHORTRX 0x00001\r
+#define CFIG_URUN_RETRY BIT_1 OR BIT_2\r
+\r
+//- Byte 8 (Default Value = 1. Enable MII mode.)\r
+#define CFIG_503_MII BIT_0\r
+\r
+//- Byte 9 (Default Value = 0, ALWAYS)\r
+\r
+//- Byte 10 (Default Value = 2Eh)\r
+#define CFIG_NSAI BIT_3\r
+#define CFIG_PREAMBLE_LENGTH BIT_5 ;- Bit 5-4 = 1-0\r
+#define CFIG_NO_LOOPBACK 0\r
+#define CFIG_INTERNAL_LOOPBACK BIT_6\r
+#define CFIG_EXT_LOOPBACK BIT_7\r
+#define CFIG_EXT_PIN_LOOPBACK BIT_6 OR BIT_7\r
+\r
+//- Byte 11 (Default Value = 0)\r
+#define CFIG_LINEAR_PRIORITY 0\r
+\r
+//- Byte 12 (Default Value = 60h)\r
+#define CFIG_LPRIORITY_MODE 0\r
+#define CFIG_IFS 6 ;- 6 * 16 = 96\r
+\r
+//- Byte 13 (Default Value = 0, ALWAYS)\r
+\r
+//- Byte 14 (Default Value = 0F2h, ALWAYS)\r
+\r
+//- Byte 15 (Default Value = E8h)\r
+#define CFIG_PROMISCUOUS_MODE BIT_0\r
+#define CFIG_BROADCAST_DISABLE BIT_1\r
+#define CFIG_CRS_CDT BIT_7\r
+\r
+//- Byte 16 (Default Value = 0, ALWAYS)\r
+\r
+//- Byte 17 (Default Value = 40h, ALWAYS)\r
+\r
+//- Byte 18 (Default Value = F2h)\r
+#define CFIG_STRIPPING BIT_0\r
+#define CFIG_PADDING BIT_1\r
+#define CFIG_RX_CRC_TRANSFER BIT_2\r
+\r
+//- Byte 19 (Default Value = 80h)\r
+#define CFIG_FORCE_FDX BIT_6\r
+#define CFIG_FDX_PIN_ENABLE BIT_7\r
+\r
+//- Byte 20 (Default Value = 3Fh)\r
+#define CFIG_MULTI_IA BIT_6\r
+\r
+//- Byte 21 (Default Value = 05)\r
+#define CFIG_MC_ALL BIT_3\r
+\r
+/*-----------------------------------------------------------------------*/\r
+#define D102_REVID 0x0b\r
+\r
+#define HALF_DUPLEX 1\r
+#define FULL_DUPLEX 2\r
+\r
+typedef struct s_data_instance {\r
+\r
+ UINT16 State; // stopped, started or initialized\r
+ UINT16 Bus;\r
+ UINT8 Device;\r
+ UINT8 Function;\r
+ UINT16 VendorID;\r
+ UINT16 DeviceID;\r
+ UINT16 RevID;\r
+ UINT16 SubVendorID;\r
+ UINT16 SubSystemID;\r
+\r
+ UINT8 PermNodeAddress[PXE_MAC_LENGTH];\r
+ UINT8 CurrentNodeAddress[PXE_MAC_LENGTH];\r
+ UINT8 BroadcastNodeAddress[PXE_MAC_LENGTH];\r
+ UINT32 Config[MAX_PCI_CONFIG_LEN];\r
+ UINT32 NVData[MAX_EEPROM_LEN];\r
+\r
+ UINT32 ioaddr;\r
+ UINT32 flash_addr;\r
+\r
+ UINT16 LinkSpeed; // actual link speed setting\r
+ UINT16 LinkSpeedReq; // requested (forced) link speed\r
+ UINT8 DuplexReq; // requested duplex\r
+ UINT8 Duplex; // Duplex set\r
+ UINT8 CableDetect; // 1 to detect and 0 not to detect the cable\r
+ UINT8 LoopBack;\r
+\r
+ UINT16 TxBufCnt;\r
+ UINT16 TxBufSize;\r
+ UINT16 RxBufCnt;\r
+ UINT16 RxBufSize;\r
+ UINT32 RxTotals;\r
+ UINT32 TxTotals;\r
+\r
+ UINT16 int_mask;\r
+ UINT16 Int_Status;\r
+ UINT16 PhyRecord[2]; // primary and secondary PHY record registers from eeprom\r
+ UINT8 PhyAddress;\r
+ UINT8 int_num;\r
+ UINT16 NVData_Len;\r
+ UINT32 MemoryLength;\r
+\r
+ RxFD *rx_ring; // array of rx buffers\r
+ TxCB *tx_ring; // array of tx buffers\r
+ struct speedo_stats *statistics;\r
+ TxCB *FreeTxHeadPtr;\r
+ TxCB *FreeTxTailPtr;\r
+ RxFD *RFDTailPtr;\r
+\r
+ UINT64 rx_phy_addr; // physical addresses\r
+ UINT64 tx_phy_addr;\r
+ UINT64 stat_phy_addr;\r
+ UINT64 MemoryPtr;\r
+ UINT64 Mapped_MemoryPtr;\r
+\r
+ UINT64 xmit_done[TX_BUFFER_COUNT << 1]; // circular buffer\r
+ UINT16 xmit_done_head; // index into the xmit_done array\r
+ UINT16 xmit_done_tail; // where are we filling now (index into xmit_done)\r
+ UINT16 cur_rx_ind; // current RX Q head index\r
+ UINT16 FreeCBCount;\r
+\r
+ BOOLEAN in_interrupt;\r
+ BOOLEAN in_transmit;\r
+ BOOLEAN Receive_Started;\r
+ UINT8 Rx_Filter;\r
+ UINT8 VersionFlag; // UNDI30 or UNDI31??\r
+ UINT8 rsvd[3];\r
+\r
+ struct mc{\r
+ UINT16 reserved [3]; // padding for this structure to make it 8 byte aligned\r
+ UINT16 list_len;\r
+ UINT8 mc_list[MAX_MCAST_ADDRESS_CNT][PXE_MAC_LENGTH]; // 8*32 is the size\r
+ } mcast_list;\r
+\r
+ UINT64 Unique_ID;\r
+\r
+ EFI_PCI_IO_PROTOCOL *Io_Function;\r
+ //\r
+ // Original PCI attributes\r
+ //\r
+ UINT64 OriginalPciAttributes;\r
+\r
+ VOID (*Delay_30)(UINTN); // call back routine\r
+ VOID (*Virt2Phys_30)(UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r
+ VOID (*Block_30)(UINT32 enable); // call back routine\r
+ VOID (*Mem_Io_30)(UINT8 read_write, UINT8 len, UINT64 port, UINT64 buf_addr);\r
+ VOID (*Delay)(UINT64, UINTN); // call back routine\r
+ VOID (*Virt2Phys)(UINT64 unq_id, UINT64 virtual_addr, UINT64 physical_ptr); // call back routine\r
+ VOID (*Block)(UINT64 unq_id, UINT32 enable); // call back routine\r
+ VOID (*Mem_Io)(UINT64 unq_id, UINT8 read_write, UINT8 len, UINT64 port,\r
+ UINT64 buf_addr);\r
+ VOID (*Map_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
+ UINT32 Direction, UINT64 mapped_addr);\r
+ VOID (*UnMap_Mem)(UINT64 unq_id, UINT64 virtual_addr, UINT32 size,\r
+ UINT32 Direction, UINT64 mapped_addr);\r
+ VOID (*Sync_Mem)(UINT64 unq_id, UINT64 virtual_addr,\r
+ UINT32 size, UINT32 Direction, UINT64 mapped_addr);\r
+} NIC_DATA_INSTANCE;\r
+\r
+#pragma pack(1)\r
+struct MC_CB_STRUCT{\r
+ UINT16 count;\r
+ UINT8 m_list[MAX_MCAST_ADDRESS_CNT][ETHER_MAC_ADDR_LEN];\r
+};\r
+#pragma pack()\r
+\r
+#define FOUR_GIGABYTE (UINT64)0x100000000ULL\r
+\r
+#endif\r
+\r
--- /dev/null
+/** @file\r
+ Initialization functions for EFI UNDI32 driver.\r
+\r
+Copyright (c) 2006 - 2008, Intel Corporation\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "Undi32.h"\r
+//\r
+// Global Variables\r
+//\r
+\r
+PXE_SW_UNDI *pxe_31 = NULL; // 3.1 entry\r
+UNDI32_DEV *UNDI32DeviceList[MAX_NIC_INTERFACES];\r
+NII_TABLE *UndiDataPointer = NULL;\r
+\r
+//\r
+// UNDI Class Driver Global Variables\r
+//\r
+EFI_DRIVER_BINDING_PROTOCOL gUndiDriverBinding = {\r
+ UndiDriverSupported,\r
+ UndiDriverStart,\r
+ UndiDriverStop,\r
+ 0xa,\r
+ NULL,\r
+ NULL\r
+};\r
+\r
+\r
+/**\r
+ When address mapping changes to virtual this should make the appropriate\r
+ address conversions.\r
+\r
+ (Standard Event handler)\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+UndiNotifyVirtual (\r
+ EFI_EVENT Event,\r
+ VOID *Context\r
+ )\r
+{\r
+ UINT16 Index;\r
+ VOID *Pxe31Pointer;\r
+\r
+ if (pxe_31 != NULL) {\r
+ Pxe31Pointer = (VOID *) pxe_31;\r
+\r
+ EfiConvertPointer (\r
+ EFI_OPTIONAL_PTR,\r
+ (VOID **) &Pxe31Pointer\r
+ );\r
+\r
+ //\r
+ // UNDI32DeviceList is an array of pointers\r
+ //\r
+ for (Index = 0; Index < pxe_31->IFcnt; Index++) {\r
+ UNDI32DeviceList[Index]->NIIProtocol_31.Id = (UINT64) (UINTN) Pxe31Pointer;\r
+ EfiConvertPointer (\r
+ EFI_OPTIONAL_PTR,\r
+ (VOID **) &(UNDI32DeviceList[Index])\r
+ );\r
+ }\r
+\r
+ EfiConvertPointer (\r
+ EFI_OPTIONAL_PTR,\r
+ (VOID **) &(pxe_31->EntryPoint)\r
+ );\r
+ pxe_31 = Pxe31Pointer;\r
+ }\r
+\r
+ for (Index = 0; Index <= PXE_OPCODE_LAST_VALID; Index++) {\r
+ EfiConvertPointer (\r
+ EFI_OPTIONAL_PTR,\r
+ (VOID **) &api_table[Index].api_ptr\r
+ );\r
+ }\r
+}\r
+\r
+\r
+/**\r
+ When EFI is shuting down the boot services, we need to install a\r
+ configuration table for UNDI to work at runtime!\r
+\r
+ (Standard Event handler)\r
+\r
+ @return None\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+UndiNotifyExitBs (\r
+ EFI_EVENT Event,\r
+ VOID *Context\r
+ )\r
+{\r
+ InstallConfigTable ();\r
+}\r
+\r
+\r
+/**\r
+ Test to see if this driver supports ControllerHandle. Any ControllerHandle\r
+ than contains a DevicePath, PciIo protocol, Class code of 2, Vendor ID of 0x8086,\r
+ and DeviceId of (D100_DEVICE_ID || D102_DEVICE_ID || ICH3_DEVICE_ID_1 ||\r
+ ICH3_DEVICE_ID_2 || ICH3_DEVICE_ID_3 || ICH3_DEVICE_ID_4 || ICH3_DEVICE_ID_5 ||\r
+ ICH3_DEVICE_ID_6 || ICH3_DEVICE_ID_7 || ICH3_DEVICE_ID_8) can be supported.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Controller Handle of device to test.\r
+ @param RemainingDevicePath Not used.\r
+\r
+ @retval EFI_SUCCESS This driver supports this device.\r
+ @retval other This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+UndiDriverSupported (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+ PCI_TYPE00 Pci;\r
+\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ NULL,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_TEST_PROTOCOL\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **) &PciIo,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_BY_DRIVER\r
+ );\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = PciIo->Pci.Read (\r
+ PciIo,\r
+ EfiPciIoWidthUint8,\r
+ 0,\r
+ sizeof (PCI_CONFIG_HEADER),\r
+ &Pci\r
+ );\r
+\r
+ if (!EFI_ERROR (Status)) {\r
+ Status = EFI_UNSUPPORTED;\r
+\r
+ if (Pci.Hdr.ClassCode[2] == 0x02 && Pci.Hdr.VendorId == PCI_VENDOR_ID_INTEL) {\r
+ switch (Pci.Hdr.DeviceId) {\r
+ case D100_DEVICE_ID:\r
+ case D102_DEVICE_ID:\r
+ case ICH3_DEVICE_ID_1:\r
+ case ICH3_DEVICE_ID_2:\r
+ case ICH3_DEVICE_ID_3:\r
+ case ICH3_DEVICE_ID_4:\r
+ case ICH3_DEVICE_ID_5:\r
+ case ICH3_DEVICE_ID_6:\r
+ case ICH3_DEVICE_ID_7:\r
+ case ICH3_DEVICE_ID_8:\r
+ case 0x1039:\r
+ case 0x103A:\r
+ case 0x103B:\r
+ case 0x103C:\r
+ case 0x103D:\r
+ case 0x103E:\r
+ case 0x1050:\r
+ case 0x1051:\r
+ case 0x1052:\r
+ case 0x1053:\r
+ case 0x1054:\r
+ case 0x1055:\r
+ case 0x1056:\r
+ case 0x1057:\r
+ case 0x1059:\r
+ case 0x1064:\r
+ Status = EFI_SUCCESS;\r
+ }\r
+ }\r
+ }\r
+\r
+ gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+ Start this driver on Controller by opening PciIo and DevicePath protocol.\r
+ Initialize PXE structures, create a copy of the Controller Device Path with the\r
+ NIC's MAC address appended to it, install the NetworkInterfaceIdentifier protocol\r
+ on the newly created Device Path.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Controller Handle of device to work with.\r
+ @param RemainingDevicePath Not used, always produce all possible children.\r
+\r
+ @retval EFI_SUCCESS This driver is added to Controller.\r
+ @retval other This driver does not support this device.\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+UndiDriverStart (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_DEVICE_PATH_PROTOCOL *UndiDevicePath;\r
+ PCI_CONFIG_HEADER *CfgHdr;\r
+ UNDI32_DEV *UNDI32Device;\r
+ UINT16 NewCommand;\r
+ UINT8 *TmpPxePointer;\r
+ EFI_PCI_IO_PROTOCOL *PciIoFncs;\r
+ UINTN Len;\r
+ UINT64 Supports;\r
+ BOOLEAN PciAttributesSaved;\r
+\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **) &PciIoFncs,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_BY_DRIVER\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ return Status;\r
+ }\r
+\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ (VOID **) &UndiDevicePath,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_BY_DRIVER\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+\r
+ return Status;\r
+ }\r
+\r
+ PciAttributesSaved = FALSE;\r
+\r
+ Status = gBS->AllocatePool (\r
+ EfiRuntimeServicesData,\r
+ sizeof (UNDI32_DEV),\r
+ (VOID **) &UNDI32Device\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto UndiError;\r
+ }\r
+\r
+ ZeroMem ((CHAR8 *) UNDI32Device, sizeof (UNDI32_DEV));\r
+\r
+ //\r
+ // Get original PCI attributes\r
+ //\r
+ Status = PciIoFncs->Attributes (\r
+ PciIoFncs,\r
+ EfiPciIoAttributeOperationGet,\r
+ 0,\r
+ &UNDI32Device->NicInfo.OriginalPciAttributes\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto UndiErrorDeleteDevice;\r
+ }\r
+ PciAttributesSaved = TRUE;\r
+\r
+ //\r
+ // allocate and initialize both (old and new) the !pxe structures here,\r
+ // there should only be one copy of each of these structure for any number\r
+ // of NICs this undi supports. Also, these structures need to be on a\r
+ // paragraph boundary as per the spec. so, while allocating space for these,\r
+ // make sure that there is space for 2 !pxe structures (old and new) and a\r
+ // 32 bytes padding for alignment adjustment (in case)\r
+ //\r
+ TmpPxePointer = NULL;\r
+ if (pxe_31 == NULL) {\r
+ Status = gBS->AllocatePool (\r
+ EfiRuntimeServicesData,\r
+ (sizeof (PXE_SW_UNDI) + sizeof (PXE_SW_UNDI) + 32),\r
+ (VOID **) &TmpPxePointer\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto UndiErrorDeleteDevice;\r
+ }\r
+\r
+ ZeroMem (\r
+ TmpPxePointer,\r
+ sizeof (PXE_SW_UNDI) + sizeof (PXE_SW_UNDI) + 32\r
+ );\r
+ //\r
+ // check for paragraph alignment here, assuming that the pointer is\r
+ // already 8 byte aligned.\r
+ //\r
+ if (((UINTN) TmpPxePointer & 0x0F) != 0) {\r
+ pxe_31 = (PXE_SW_UNDI *) ((UINTN) (TmpPxePointer + 8));\r
+ } else {\r
+ pxe_31 = (PXE_SW_UNDI *) TmpPxePointer;\r
+ }\r
+\r
+ PxeStructInit (pxe_31);\r
+ }\r
+\r
+ UNDI32Device->NIIProtocol_31.Id = (UINT64) (UINTN) (pxe_31);\r
+\r
+ Status = PciIoFncs->Attributes (\r
+ PciIoFncs,\r
+ EfiPciIoAttributeOperationSupported,\r
+ 0,\r
+ &Supports\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+ Supports &= EFI_PCI_DEVICE_ENABLE;\r
+ Status = PciIoFncs->Attributes (\r
+ PciIoFncs,\r
+ EfiPciIoAttributeOperationEnable,\r
+ Supports,\r
+ NULL\r
+ );\r
+ }\r
+ //\r
+ // Read all the registers from device's PCI Configuration space\r
+ //\r
+ Status = PciIoFncs->Pci.Read (\r
+ PciIoFncs,\r
+ EfiPciIoWidthUint32,\r
+ 0,\r
+ MAX_PCI_CONFIG_LEN,\r
+ &UNDI32Device->NicInfo.Config\r
+ );\r
+\r
+ CfgHdr = (PCI_CONFIG_HEADER *) &(UNDI32Device->NicInfo.Config[0]);\r
+\r
+ //\r
+ // make sure that this device is a PCI bus master\r
+ //\r
+\r
+ NewCommand = (UINT16) (CfgHdr->Command | PCI_COMMAND_MASTER | PCI_COMMAND_IO);\r
+ if (CfgHdr->Command != NewCommand) {\r
+ PciIoFncs->Pci.Write (\r
+ PciIoFncs,\r
+ EfiPciIoWidthUint16,\r
+ PCI_COMMAND,\r
+ 1,\r
+ &NewCommand\r
+ );\r
+ CfgHdr->Command = NewCommand;\r
+ }\r
+\r
+ //\r
+ // make sure that the latency timer is at least 32\r
+ //\r
+ if (CfgHdr->LatencyTimer < 32) {\r
+ CfgHdr->LatencyTimer = 32;\r
+ PciIoFncs->Pci.Write (\r
+ PciIoFncs,\r
+ EfiPciIoWidthUint8,\r
+ PCI_LATENCY_TIMER,\r
+ 1,\r
+ &CfgHdr->LatencyTimer\r
+ );\r
+ }\r
+ //\r
+ // the IfNum index for the current interface will be the total number\r
+ // of interfaces initialized so far\r
+ //\r
+ UNDI32Device->NIIProtocol_31.IfNum = pxe_31->IFcnt;\r
+\r
+ PxeUpdate (&UNDI32Device->NicInfo, pxe_31);\r
+\r
+ UNDI32Device->NicInfo.Io_Function = PciIoFncs;\r
+ UNDI32DeviceList[UNDI32Device->NIIProtocol_31.IfNum] = UNDI32Device;\r
+ UNDI32Device->Undi32BaseDevPath = UndiDevicePath;\r
+\r
+ Status = AppendMac2DevPath (\r
+ &UNDI32Device->Undi32DevPath,\r
+ UNDI32Device->Undi32BaseDevPath,\r
+ &UNDI32Device->NicInfo\r
+ );\r
+\r
+ if (Status != 0) {\r
+ goto UndiErrorDeletePxe;\r
+ }\r
+\r
+ UNDI32Device->Signature = UNDI_DEV_SIGNATURE;\r
+\r
+ UNDI32Device->NIIProtocol_31.Revision = EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION_31;\r
+ UNDI32Device->NIIProtocol_31.Type = EfiNetworkInterfaceUndi;\r
+ UNDI32Device->NIIProtocol_31.MajorVer = PXE_ROMID_MAJORVER;\r
+ UNDI32Device->NIIProtocol_31.MinorVer = PXE_ROMID_MINORVER_31;\r
+ UNDI32Device->NIIProtocol_31.ImageSize = 0;\r
+ UNDI32Device->NIIProtocol_31.ImageAddr = 0;\r
+ UNDI32Device->NIIProtocol_31.Ipv6Supported = FALSE;\r
+\r
+ UNDI32Device->NIIProtocol_31.StringId[0] = 'U';\r
+ UNDI32Device->NIIProtocol_31.StringId[1] = 'N';\r
+ UNDI32Device->NIIProtocol_31.StringId[2] = 'D';\r
+ UNDI32Device->NIIProtocol_31.StringId[3] = 'I';\r
+\r
+ UNDI32Device->DeviceHandle = NULL;\r
+\r
+ //\r
+ // install both the 3.0 and 3.1 NII protocols.\r
+ //\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &UNDI32Device->DeviceHandle,\r
+ &gEfiNetworkInterfaceIdentifierProtocolGuid_31,\r
+ &UNDI32Device->NIIProtocol_31,\r
+ &gEfiDevicePathProtocolGuid,\r
+ UNDI32Device->Undi32DevPath,\r
+ NULL\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto UndiErrorDeleteDevicePath;\r
+ }\r
+\r
+ //\r
+ // if the table exists, free it and alloc again, or alloc it directly\r
+ //\r
+ if (UndiDataPointer != NULL) {\r
+ Status = gBS->FreePool(UndiDataPointer);\r
+ }\r
+ if (EFI_ERROR (Status)) {\r
+ goto UndiErrorDeleteDevicePath;\r
+ }\r
+\r
+ Len = (pxe_31->IFcnt * sizeof (NII_ENTRY)) + sizeof (UndiDataPointer);\r
+ Status = gBS->AllocatePool (EfiRuntimeServicesData, Len, (VOID **) &UndiDataPointer);\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ goto UndiErrorAllocDataPointer;\r
+ }\r
+\r
+ //\r
+ // Open For Child Device\r
+ //\r
+ Status = gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **) &PciIoFncs,\r
+ This->DriverBindingHandle,\r
+ UNDI32Device->DeviceHandle,\r
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER\r
+ );\r
+\r
+ return EFI_SUCCESS;\r
+UndiErrorAllocDataPointer:\r
+ gBS->UninstallMultipleProtocolInterfaces (\r
+ &UNDI32Device->DeviceHandle,\r
+ &gEfiNetworkInterfaceIdentifierProtocolGuid_31,\r
+ &UNDI32Device->NIIProtocol_31,\r
+ &gEfiDevicePathProtocolGuid,\r
+ UNDI32Device->Undi32DevPath,\r
+ NULL\r
+ );\r
+\r
+UndiErrorDeleteDevicePath:\r
+ UNDI32DeviceList[UNDI32Device->NIIProtocol_31.IfNum] = NULL;\r
+ gBS->FreePool (UNDI32Device->Undi32DevPath);\r
+\r
+UndiErrorDeletePxe:\r
+ PxeUpdate (NULL, pxe_31);\r
+ if (TmpPxePointer != NULL) {\r
+ gBS->FreePool (TmpPxePointer);\r
+\r
+ }\r
+\r
+UndiErrorDeleteDevice:\r
+ if (PciAttributesSaved) {\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
+ PciIoFncs->Attributes (\r
+ PciIoFncs,\r
+ EfiPciIoAttributeOperationSet,\r
+ UNDI32Device->NicInfo.OriginalPciAttributes,\r
+ NULL\r
+ );\r
+ }\r
+\r
+ gBS->FreePool (UNDI32Device);\r
+\r
+UndiError:\r
+ gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+\r
+ gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+\r
+ return Status;\r
+}\r
+\r
+\r
+/**\r
+ Stop this driver on Controller by removing NetworkInterfaceIdentifier protocol and\r
+ closing the DevicePath and PciIo protocols on Controller.\r
+\r
+ @param This Protocol instance pointer.\r
+ @param Controller Handle of device to stop driver on.\r
+ @param NumberOfChildren How many children need to be stopped.\r
+ @param ChildHandleBuffer Not used.\r
+\r
+ @retval EFI_SUCCESS This driver is removed Controller.\r
+ @retval other This driver was not removed from this device.\r
+\r
+**/\r
+// TODO: EFI_DEVICE_ERROR - add return value to function comment\r
+EFI_STATUS\r
+EFIAPI\r
+UndiDriverStop (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN UINTN NumberOfChildren,\r
+ IN EFI_HANDLE *ChildHandleBuffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ BOOLEAN AllChildrenStopped;\r
+ UINTN Index;\r
+ UNDI32_DEV *UNDI32Device;\r
+ EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL *NIIProtocol;\r
+ EFI_PCI_IO_PROTOCOL *PciIo;\r
+\r
+ //\r
+ // Complete all outstanding transactions to Controller.\r
+ // Don't allow any new transaction to Controller to be started.\r
+ //\r
+ if (NumberOfChildren == 0) {\r
+\r
+ //\r
+ // Close the bus driver\r
+ //\r
+ Status = gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiDevicePathProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+\r
+ Status = gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ Controller\r
+ );\r
+\r
+ return Status;\r
+ }\r
+\r
+ AllChildrenStopped = TRUE;\r
+\r
+ for (Index = 0; Index < NumberOfChildren; Index++) {\r
+\r
+ Status = gBS->OpenProtocol (\r
+ ChildHandleBuffer[Index],\r
+ &gEfiNetworkInterfaceIdentifierProtocolGuid_31,\r
+ (VOID **) &NIIProtocol,\r
+ This->DriverBindingHandle,\r
+ Controller,\r
+ EFI_OPEN_PROTOCOL_GET_PROTOCOL\r
+ );\r
+ if (!EFI_ERROR (Status)) {\r
+\r
+ UNDI32Device = UNDI_DEV_FROM_THIS (NIIProtocol);\r
+\r
+ //\r
+ // Restore original PCI attributes\r
+ //\r
+ Status = UNDI32Device->NicInfo.Io_Function->Attributes (\r
+ UNDI32Device->NicInfo.Io_Function,\r
+ EfiPciIoAttributeOperationSet,\r
+ UNDI32Device->NicInfo.OriginalPciAttributes,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->CloseProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ This->DriverBindingHandle,\r
+ ChildHandleBuffer[Index]\r
+ );\r
+\r
+ Status = gBS->UninstallMultipleProtocolInterfaces (\r
+ ChildHandleBuffer[Index],\r
+ &gEfiDevicePathProtocolGuid,\r
+ UNDI32Device->Undi32DevPath,\r
+ &gEfiNetworkInterfaceIdentifierProtocolGuid_31,\r
+ &UNDI32Device->NIIProtocol_31,\r
+ NULL\r
+ );\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ gBS->OpenProtocol (\r
+ Controller,\r
+ &gEfiPciIoProtocolGuid,\r
+ (VOID **) &PciIo,\r
+ This->DriverBindingHandle,\r
+ ChildHandleBuffer[Index],\r
+ EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER\r
+ );\r
+ } else {\r
+ gBS->FreePool (UNDI32Device->Undi32DevPath);\r
+ gBS->FreePool (UNDI32Device);\r
+ }\r
+ }\r
+\r
+ if (EFI_ERROR (Status)) {\r
+ AllChildrenStopped = FALSE;\r
+ }\r
+ }\r
+\r
+ if (!AllChildrenStopped) {\r
+ return EFI_DEVICE_ERROR;\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+\r
+}\r
+\r
+\r
+/**\r
+ Use the EFI boot services to produce a pause. This is also the routine which\r
+ gets replaced during RunTime by the O/S in the NIC_DATA_INSTANCE so it can\r
+ do it's own pause.\r
+\r
+ @param UnqId Runtime O/S routine might use this, this temp\r
+ routine does not use it\r
+ @param MicroSeconds Determines the length of pause.\r
+\r
+ @return none\r
+\r
+**/\r
+VOID\r
+TmpDelay (\r
+ IN UINT64 UnqId,\r
+ IN UINTN MicroSeconds\r
+ )\r
+{\r
+ gBS->Stall ((UINT32) MicroSeconds);\r
+}\r
+\r
+\r
+/**\r
+ Use the PCI IO abstraction to issue memory or I/O reads and writes. This is also the routine which\r
+ gets replaced during RunTime by the O/S in the NIC_DATA_INSTANCE so it can do it's own I/O abstractions.\r
+\r
+ @param UnqId Runtime O/S routine may use this field, this temp\r
+ routine does not.\r
+ @param ReadWrite Determine if it is an I/O or Memory Read/Write\r
+ Operation.\r
+ @param Len Determines the width of the data operation.\r
+ @param Port What port to Read/Write from.\r
+ @param BuffAddr Address to read to or write from.\r
+\r
+ @return none\r
+\r
+**/\r
+VOID\r
+TmpMemIo (\r
+ IN UINT64 UnqId,\r
+ IN UINT8 ReadWrite,\r
+ IN UINT8 Len,\r
+ IN UINT64 Port,\r
+ IN UINT64 BuffAddr\r
+ )\r
+{\r
+ EFI_PCI_IO_PROTOCOL_WIDTH Width;\r
+ NIC_DATA_INSTANCE *AdapterInfo;\r
+\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) 0;\r
+ AdapterInfo = (NIC_DATA_INSTANCE *) (UINTN) UnqId;\r
+ switch (Len) {\r
+ case 2:\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) 1;\r
+ break;\r
+\r
+ case 4:\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) 2;\r
+ break;\r
+\r
+ case 8:\r
+ Width = (EFI_PCI_IO_PROTOCOL_WIDTH) 3;\r
+ break;\r
+ }\r
+\r
+ switch (ReadWrite) {\r
+ case PXE_IO_READ:\r
+ AdapterInfo->Io_Function->Io.Read (\r
+ AdapterInfo->Io_Function,\r
+ Width,\r
+ 1,\r
+ Port,\r
+ 1,\r
+ (VOID *) (UINTN) (BuffAddr)\r
+ );\r
+ break;\r
+\r
+ case PXE_IO_WRITE:\r
+ AdapterInfo->Io_Function->Io.Write (\r
+ AdapterInfo->Io_Function,\r
+ Width,\r
+ 1,\r
+ Port,\r
+ 1,\r
+ (VOID *) (UINTN) (BuffAddr)\r
+ );\r
+ break;\r
+\r
+ case PXE_MEM_READ:\r
+ AdapterInfo->Io_Function->Mem.Read (\r
+ AdapterInfo->Io_Function,\r
+ Width,\r
+ 0,\r
+ Port,\r
+ 1,\r
+ (VOID *) (UINTN) (BuffAddr)\r
+ );\r
+ break;\r
+\r
+ case PXE_MEM_WRITE:\r
+ AdapterInfo->Io_Function->Mem.Write (\r
+ AdapterInfo->Io_Function,\r
+ Width,\r
+ 0,\r
+ Port,\r
+ 1,\r
+ (VOID *) (UINTN) (BuffAddr)\r
+ );\r
+ break;\r
+ }\r
+\r
+ return ;\r
+}\r
+\r
+\r
+/**\r
+ Using the NIC data structure information, read the EEPROM to get the MAC address and then allocate space\r
+ for a new devicepath (**DevPtr) which will contain the original device path the NIC was found on (*BaseDevPtr)\r
+ and an added MAC node.\r
+\r
+ @param DevPtr Pointer which will point to the newly created device\r
+ path with the MAC node attached.\r
+ @param BaseDevPtr Pointer to the device path which the UNDI device\r
+ driver is latching on to.\r
+ @param AdapterInfo Pointer to the NIC data structure information which\r
+ the UNDI driver is layering on..\r
+\r
+ @retval EFI_SUCCESS A MAC address was successfully appended to the Base\r
+ Device Path.\r
+ @retval other Not enough resources available to create new Device\r
+ Path node.\r
+\r
+**/\r
+EFI_STATUS\r
+AppendMac2DevPath (\r
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevPtr,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *BaseDevPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ )\r
+{\r
+ EFI_MAC_ADDRESS MACAddress;\r
+ PCI_CONFIG_HEADER *CfgHdr;\r
+ INT32 Val;\r
+ INT32 Index;\r
+ INT32 Index2;\r
+ UINT8 AddrLen;\r
+ MAC_ADDR_DEVICE_PATH MacAddrNode;\r
+ EFI_DEVICE_PATH_PROTOCOL *EndNode;\r
+ UINT8 *DevicePtr;\r
+ UINT16 TotalPathLen;\r
+ UINT16 BasePathLen;\r
+ EFI_STATUS Status;\r
+\r
+ //\r
+ // set the environment ready (similar to UNDI_Start call) so that we can\r
+ // execute the other UNDI_ calls to get the mac address\r
+ // we are using undi 3.1 style\r
+ //\r
+ AdapterInfo->Delay = TmpDelay;\r
+ AdapterInfo->Virt2Phys = (VOID *) 0;\r
+ AdapterInfo->Block = (VOID *) 0;\r
+ AdapterInfo->Map_Mem = (VOID *) 0;\r
+ AdapterInfo->UnMap_Mem = (VOID *) 0;\r
+ AdapterInfo->Sync_Mem = (VOID *) 0;\r
+ AdapterInfo->Mem_Io = TmpMemIo;\r
+ //\r
+ // these tmp call-backs follow 3.1 undi style\r
+ // i.e. they have the unique_id parameter.\r
+ //\r
+ AdapterInfo->VersionFlag = 0x31;\r
+ AdapterInfo->Unique_ID = (UINT64) (UINTN) AdapterInfo;\r
+\r
+ //\r
+ // undi init portion\r
+ //\r
+ CfgHdr = (PCI_CONFIG_HEADER *) &(AdapterInfo->Config[0]);\r
+ AdapterInfo->ioaddr = 0;\r
+ AdapterInfo->RevID = CfgHdr->RevID;\r
+\r
+ AddrLen = E100bGetEepromAddrLen (AdapterInfo);\r
+\r
+ for (Index = 0, Index2 = 0; Index < 3; Index++) {\r
+ Val = E100bReadEeprom (AdapterInfo, Index, AddrLen);\r
+ MACAddress.Addr[Index2++] = (UINT8) Val;\r
+ MACAddress.Addr[Index2++] = (UINT8) (Val >> 8);\r
+ }\r
+\r
+ SetMem (MACAddress.Addr + Index2, sizeof (EFI_MAC_ADDRESS) - Index2, 0);\r
+ //for (; Index2 < sizeof (EFI_MAC_ADDRESS); Index2++) {\r
+ // MACAddress.Addr[Index2] = 0;\r
+ //}\r
+ //\r
+ // stop undi\r
+ //\r
+ AdapterInfo->Delay = (VOID *) 0;\r
+ AdapterInfo->Mem_Io = (VOID *) 0;\r
+\r
+ //\r
+ // fill the mac address node first\r
+ //\r
+ ZeroMem ((CHAR8 *) &MacAddrNode, sizeof MacAddrNode);\r
+ CopyMem (\r
+ (CHAR8 *) &MacAddrNode.MacAddress,\r
+ (CHAR8 *) &MACAddress,\r
+ sizeof (EFI_MAC_ADDRESS)\r
+ );\r
+\r
+ MacAddrNode.Header.Type = MESSAGING_DEVICE_PATH;\r
+ MacAddrNode.Header.SubType = MSG_MAC_ADDR_DP;\r
+ MacAddrNode.Header.Length[0] = sizeof (MacAddrNode);\r
+ MacAddrNode.Header.Length[1] = 0;\r
+\r
+ //\r
+ // find the size of the base dev path.\r
+ //\r
+ EndNode = BaseDevPtr;\r
+\r
+ while (!IsDevicePathEnd (EndNode)) {\r
+ EndNode = NextDevicePathNode (EndNode);\r
+ }\r
+\r
+ BasePathLen = (UINT16) ((UINTN) (EndNode) - (UINTN) (BaseDevPtr));\r
+\r
+ //\r
+ // create space for full dev path\r
+ //\r
+ TotalPathLen = (UINT16) (BasePathLen + sizeof (MacAddrNode) + sizeof (EFI_DEVICE_PATH_PROTOCOL));\r
+\r
+ Status = gBS->AllocatePool (\r
+ EfiRuntimeServicesData,\r
+ TotalPathLen,\r
+ (VOID **) &DevicePtr\r
+ );\r
+\r
+ if (Status != EFI_SUCCESS) {\r
+ return Status;\r
+ }\r
+ //\r
+ // copy the base path, mac addr and end_dev_path nodes\r
+ //\r
+ *DevPtr = (EFI_DEVICE_PATH_PROTOCOL *) DevicePtr;\r
+ CopyMem (DevicePtr, (CHAR8 *) BaseDevPtr, BasePathLen);\r
+ DevicePtr += BasePathLen;\r
+ CopyMem (DevicePtr, (CHAR8 *) &MacAddrNode, sizeof (MacAddrNode));\r
+ DevicePtr += sizeof (MacAddrNode);\r
+ CopyMem (DevicePtr, (CHAR8 *) EndNode, sizeof (EFI_DEVICE_PATH_PROTOCOL));\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+\r
+/**\r
+ Install a GUID/Pointer pair into the system's configuration table.\r
+\r
+ none\r
+\r
+ @retval EFI_SUCCESS Install a GUID/Pointer pair into the system's\r
+ configuration table.\r
+ @retval other Did not successfully install the GUID/Pointer pair\r
+ into the configuration table.\r
+\r
+**/\r
+// TODO: VOID - add argument and description to function comment\r
+EFI_STATUS\r
+InstallConfigTable (\r
+ IN VOID\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_CONFIGURATION_TABLE *CfgPtr;\r
+ NII_TABLE *TmpData;\r
+ UINT16 Index;\r
+ NII_TABLE *UndiData;\r
+\r
+ if (pxe_31 == NULL) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ if(UndiDataPointer == NULL) {\r
+ return EFI_SUCCESS;\r
+ }\r
+\r
+ UndiData = (NII_TABLE *)UndiDataPointer;\r
+\r
+ UndiData->NumEntries = pxe_31->IFcnt;\r
+ UndiData->NextLink = NULL;\r
+\r
+ for (Index = 0; Index < pxe_31->IFcnt; Index++) {\r
+ UndiData->NiiEntry[Index].InterfacePointer = &UNDI32DeviceList[Index]->NIIProtocol_31;\r
+ UndiData->NiiEntry[Index].DevicePathPointer = UNDI32DeviceList[Index]->Undi32DevPath;\r
+ }\r
+\r
+ //\r
+ // see if there is an entry in the config table already\r
+ //\r
+ CfgPtr = gST->ConfigurationTable;\r
+\r
+ for (Index = 0; Index < gST->NumberOfTableEntries; Index++) {\r
+ Status = CompareGuid (\r
+ &CfgPtr->VendorGuid,\r
+ &gEfiNetworkInterfaceIdentifierProtocolGuid_31\r
+ );\r
+ if (Status != EFI_SUCCESS) {\r
+ break;\r
+ }\r
+\r
+ CfgPtr++;\r
+ }\r
+\r
+ if (Index < gST->NumberOfTableEntries) {\r
+ TmpData = (NII_TABLE *) CfgPtr->VendorTable;\r
+\r
+ //\r
+ // go to the last link\r
+ //\r
+ while (TmpData->NextLink != NULL) {\r
+ TmpData = TmpData->NextLink;\r
+ }\r
+\r
+ TmpData->NextLink = UndiData;\r
+\r
+ //\r
+ // 1st one in chain\r
+ //\r
+ UndiData = (NII_TABLE *) CfgPtr->VendorTable;\r
+ }\r
+\r
+ //\r
+ // create an entry in the configuration table for our GUID\r
+ //\r
+ Status = gBS->InstallConfigurationTable (\r
+ &gEfiNetworkInterfaceIdentifierProtocolGuid_31,\r
+ UndiData\r
+ );\r
+ return Status;\r
+}\r
+\r
+/**\r
+\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeUndi(\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_EVENT Event;\r
+ EFI_STATUS Status;\r
+\r
+ Status = EfiLibInstallDriverBinding (\r
+ ImageHandle,\r
+ SystemTable,\r
+ &gUndiDriverBinding,\r
+ ImageHandle\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->CreateEventEx (\r
+ EVT_NOTIFY_SIGNAL,\r
+ TPL_NOTIFY,\r
+ UndiNotifyExitBs,\r
+ NULL,\r
+ &gEfiEventExitBootServicesGuid,\r
+ &Event\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ Status = gBS->CreateEventEx (\r
+ EVT_NOTIFY_SIGNAL,\r
+ TPL_NOTIFY,\r
+ UndiNotifyVirtual,\r
+ NULL,\r
+ &gEfiEventVirtualAddressChangeGuid,\r
+ &Event\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return Status;\r
+}\r
--- /dev/null
+/** @file\r
+ EFI internal structures for the EFI UNDI driver.\r
+\r
+Copyright (c) 2006 - 2007, Intel Corporation.\r
+All rights reserved. This program and the accompanying materials\r
+are licensed and made available under the terms and conditions of the BSD License\r
+which accompanies this distribution. The full text of the license may be found at\r
+http://opensource.org/licenses/bsd-license.php\r
+\r
+THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _UNDI_32_H_\r
+#define _UNDI_32_H_\r
+\r
+#include <Uefi.h>\r
+\r
+#include <Guid/EventGroup.h>\r
+#include <Protocol/PciIo.h>\r
+#include <Protocol/NetworkInterfaceIdentifier.h>\r
+#include <Protocol/DevicePath.h>\r
+\r
+#include <Library/UefiDriverEntryPoint.h>\r
+#include <Library/UefiRuntimeLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/UefiLib.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DevicePathLib.h>\r
+\r
+#include <IndustryStandard/Pci.h>\r
+\r
+\r
+#include "E100b.h"\r
+\r
+#define MAX_NIC_INTERFACES 16\r
+\r
+#define EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL_REVISION_31 0x00010001\r
+#define PXE_ROMID_MINORVER_31 0x10\r
+#define PXE_STATFLAGS_DB_WRITE_TRUNCATED 0x2000\r
+\r
+//\r
+// UNDI_CALL_TABLE.state can have the following values\r
+//\r
+#define DONT_CHECK -1\r
+#define ANY_STATE -1\r
+#define MUST_BE_STARTED 1\r
+#define MUST_BE_INITIALIZED 2\r
+\r
+#define UNDI_DEV_SIGNATURE SIGNATURE_32('u','n','d','i')\r
+#define UNDI_DEV_FROM_THIS(a) CR(a, UNDI32_DEV, NIIProtocol_31, UNDI_DEV_SIGNATURE)\r
+#define UNDI_DEV_FROM_NIC(a) CR(a, UNDI32_DEV, NicInfo, UNDI_DEV_SIGNATURE)\r
+\r
+typedef struct {\r
+ UINTN Signature;\r
+ EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL NIIProtocol_31;\r
+ EFI_HANDLE DeviceHandle;\r
+ EFI_DEVICE_PATH_PROTOCOL *Undi32BaseDevPath;\r
+ EFI_DEVICE_PATH_PROTOCOL *Undi32DevPath;\r
+ NIC_DATA_INSTANCE NicInfo;\r
+} UNDI32_DEV;\r
+\r
+typedef struct {\r
+ UINT16 cpbsize;\r
+ UINT16 dbsize;\r
+ UINT16 opflags;\r
+ UINT16 state;\r
+ VOID (*api_ptr)();\r
+} UNDI_CALL_TABLE;\r
+\r
+typedef struct {\r
+ EFI_NETWORK_INTERFACE_IDENTIFIER_PROTOCOL *InterfacePointer;\r
+ EFI_DEVICE_PATH_PROTOCOL *DevicePathPointer;\r
+} NII_ENTRY;\r
+\r
+typedef struct NII_CONFIG_ENTRY {\r
+ UINT32 NumEntries;\r
+ UINT32 Reserved; // padding for alignment\r
+ struct NII_CONFIG_ENTRY *NextLink;\r
+ NII_ENTRY NiiEntry[1];\r
+} NII_TABLE;\r
+\r
+typedef VOID (*ptr)(VOID);\r
+typedef VOID (*bsptr_30)(UINTN);\r
+typedef VOID (*virtphys_30)(UINT64, UINT64);\r
+typedef VOID (*block_30)(UINT32);\r
+typedef VOID (*mem_io_30)(UINT8, UINT8, UINT64, UINT64);\r
+\r
+typedef VOID (*bsptr)(UINT64, UINTN);\r
+typedef VOID (*virtphys)(UINT64, UINT64, UINT64);\r
+typedef VOID (*block)(UINT64, UINT32);\r
+typedef VOID (*mem_io)(UINT64, UINT8, UINT8, UINT64, UINT64);\r
+\r
+typedef VOID (*map_mem)(UINT64, UINT64, UINT32, UINT32, UINT64);\r
+typedef VOID (*unmap_mem)(UINT64, UINT64, UINT32, UINT32, UINT64);\r
+typedef VOID (*sync_mem)(UINT64, UINT64, UINT32, UINT32, UINT64);\r
+\r
+extern UNDI_CALL_TABLE api_table[];\r
+extern PXE_SW_UNDI *pxe_31; // !pxe structure for 3.1 drivers\r
+extern UNDI32_DEV *UNDI32DeviceList[MAX_NIC_INTERFACES];\r
+\r
+//\r
+// functions defined in e100b.c\r
+//\r
+UINT8 InByte (NIC_DATA_INSTANCE *AdapterInfo, UINT32 Port);\r
+UINT16 InWord (NIC_DATA_INSTANCE *AdapterInfo, UINT32 Port);\r
+UINT32 InLong (NIC_DATA_INSTANCE *AdapterInfo, UINT32 Port);\r
+VOID OutByte (NIC_DATA_INSTANCE *AdapterInfo, UINT8 Data, UINT32 Port);\r
+VOID OutWord (NIC_DATA_INSTANCE *AdapterInfo, UINT16 Data, UINT32 Port);\r
+VOID OutLong (NIC_DATA_INSTANCE *AdapterInfo, UINT32 Data, UINT32 Port);\r
+\r
+UINTN E100bInit (NIC_DATA_INSTANCE *AdapterInfo);\r
+UINTN E100bReset (NIC_DATA_INSTANCE *AdapterInfo, INT32 OpFlags);\r
+UINTN E100bShutdown (NIC_DATA_INSTANCE *AdapterInfo);\r
+UINTN E100bTransmit (NIC_DATA_INSTANCE *AdapterInfo, UINT64 cpb, UINT16 opflags);\r
+UINTN E100bReceive (NIC_DATA_INSTANCE *AdapterInfo, UINT64 cpb, UINT64 db);\r
+UINTN E100bSetfilter (NIC_DATA_INSTANCE *AdapterInfo, UINT16 New_filter,\r
+ UINT64 cpb, UINT32 cpbsize);\r
+UINTN E100bStatistics(NIC_DATA_INSTANCE *AdapterInfo, UINT64 db, UINT16 dbsize);\r
+UINT8 E100bSetupIAAddr (NIC_DATA_INSTANCE *AdapterInfo);\r
+UINT8 E100bSetInterruptState (NIC_DATA_INSTANCE *AdapterInfo);\r
+\r
+UINT8 E100bGetEepromAddrLen (NIC_DATA_INSTANCE *AdapterInfo);\r
+UINT16 E100bReadEeprom (NIC_DATA_INSTANCE *AdapterInfo, INT32 Location, UINT8 address_len);\r
+INT16 E100bReadEepromAndStationAddress (NIC_DATA_INSTANCE *AdapterInfo);\r
+\r
+UINT16 next(UINT16);\r
+UINT8 SetupCBlink (NIC_DATA_INSTANCE *AdapterInfo);\r
+VOID SetFreeCB (NIC_DATA_INSTANCE *AdapterInfo,TxCB *);\r
+TxCB *GetFreeCB (NIC_DATA_INSTANCE *AdapterInfo);\r
+UINT16 CheckCBList (NIC_DATA_INSTANCE *AdapterInfo);\r
+\r
+UINT8 SelectiveReset (NIC_DATA_INSTANCE *AdapterInfo);\r
+UINT16 InitializeChip (NIC_DATA_INSTANCE *AdapterInfo);\r
+UINT8 SetupReceiveQueues (NIC_DATA_INSTANCE *AdapterInfo);\r
+VOID Recycle_RFD (NIC_DATA_INSTANCE *AdapterInfo, UINT16);\r
+VOID XmitWaitForCompletion (NIC_DATA_INSTANCE *AdapterInfo);\r
+INT8 CommandWaitForCompletion (TxCB *cmd_ptr, NIC_DATA_INSTANCE *AdapterInfo);\r
+\r
+BOOLEAN PhyDetect (NIC_DATA_INSTANCE *AdapterInfo);\r
+VOID PhyReset (NIC_DATA_INSTANCE *AdapterInfo);\r
+VOID\r
+MdiWrite (\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT8 RegAddress,\r
+ IN UINT8 PhyAddress,\r
+ IN UINT16 DataValue\r
+ );\r
+\r
+VOID\r
+MdiRead(\r
+ IN NIC_DATA_INSTANCE *AdapterInfo,\r
+ IN UINT8 RegAddress,\r
+ IN UINT8 PhyAddress,\r
+ IN OUT UINT16 *DataValue\r
+ );\r
+\r
+BOOLEAN SetupPhy (NIC_DATA_INSTANCE *AdapterInfo);\r
+VOID FindPhySpeedAndDpx (NIC_DATA_INSTANCE *AdapterInfo, UINT32 PhyId);\r
+\r
+\r
+\r
+//\r
+// functions defined in init.c\r
+//\r
+EFI_STATUS\r
+InstallConfigTable (\r
+ IN VOID\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+InitializeUNDIDriver (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ );\r
+\r
+VOID\r
+UNDI_notify_virtual (\r
+ EFI_EVENT event,\r
+ VOID *context\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+UndiNotifyExitBs (\r
+ EFI_EVENT Event,\r
+ VOID *Context\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+UndiDriverSupported (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+UndiDriverStart (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+UndiDriverStop (\r
+ IN EFI_DRIVER_BINDING_PROTOCOL *This,\r
+ IN EFI_HANDLE Controller,\r
+ IN UINTN NumberOfChildren,\r
+ IN EFI_HANDLE *ChildHandleBuffer\r
+ );\r
+\r
+EFI_STATUS\r
+AppendMac2DevPath (\r
+ IN OUT EFI_DEVICE_PATH_PROTOCOL **DevPtr,\r
+ IN EFI_DEVICE_PATH_PROTOCOL *BaseDevPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+TmpDelay (\r
+ IN UINT64 UnqId,\r
+ IN UINTN MicroSeconds\r
+ );\r
+\r
+VOID\r
+TmpMemIo (\r
+ IN UINT64 UnqId,\r
+ IN UINT8 ReadWrite,\r
+ IN UINT8 Len,\r
+ IN UINT64 Port,\r
+ IN UINT64 BufAddr\r
+ );\r
+\r
+//\r
+// functions defined in decode.c\r
+//\r
+VOID\r
+UNDI_GetState (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Start (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Stop (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_GetInitInfo (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_GetConfigInfo (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Initialize (\r
+ IN PXE_CDB *CdbPtr,\r
+ NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Reset (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Shutdown (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Interrupt (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_RecFilter (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_StnAddr (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Statistics (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_ip2mac (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_NVData (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Status (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_FillHeader (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Transmit (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID\r
+UNDI_Receive (\r
+ IN PXE_CDB *CdbPtr,\r
+ IN NIC_DATA_INSTANCE *AdapterInfo\r
+ );\r
+\r
+VOID UNDI_APIEntry_new(UINT64);\r
+VOID UNDI_APIEntry_Common(UINT64);\r
+\r
+PXE_IPV4 convert_mcip(PXE_MAC_ADDR *);\r
+INT32 validate_mcip (PXE_MAC_ADDR *MCastAddr);\r
+\r
+VOID PxeStructInit (PXE_SW_UNDI *PxePtr);\r
+VOID PxeUpdate (NIC_DATA_INSTANCE *NicPtr, PXE_SW_UNDI *PxePtr);\r
+\r
+#endif\r
--- /dev/null
+#/** @file\r
+# Component description file for Undi module.\r
+#\r
+# This module provides support for Universal Network Driver Interface\r
+# Copyright (c) 2006 - 2007, Intel Corporation\r
+#\r
+# All rights reserved. This program and the accompanying materials\r
+# are licensed and made available under the terms and conditions of the BSD License\r
+# which accompanies this distribution. The full text of the license may be found at\r
+# http://opensource.org/licenses/bsd-license.php\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+#\r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = UndiRuntimeDxe\r
+ FILE_GUID = A1f436EA-A127-4EF8-957C-8048606FF670\r
+ MODULE_TYPE = DXE_RUNTIME_DRIVER\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = InitializeUndi\r
+\r
+#\r
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC\r
+#\r
+\r
+[Sources.common]\r
+ Undi32.h\r
+ E100b.h\r
+ E100b.c\r
+ Decode.c\r
+ Init.c\r
+\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+\r
+\r
+[LibraryClasses]\r
+ UefiLib\r
+ UefiBootServicesTableLib\r
+ BaseMemoryLib\r
+ DebugLib\r
+ UefiRuntimeLib\r
+ UefiDriverEntryPoint\r
+ BaseLib\r
+\r
+[Protocols]\r
+ gEfiNetworkInterfaceIdentifierProtocolGuid_31\r
+ gEfiPciIoProtocolGuid\r
+ gEfiDevicePathProtocolGuid\r
+\r
+[Guids]\r
+ gEfiEventExitBootServicesGuid ## PRODUCES ## Event\r
+ gEfiEventVirtualAddressChangeGuid ## PRODUCES ## Event\r
+\r
+[Depex]\r
+ gEfiBdsArchProtocolGuid AND\r
+ gEfiCpuArchProtocolGuid AND\r
+ gEfiMetronomeArchProtocolGuid AND\r
+ gEfiMonotonicCounterArchProtocolGuid AND\r
+ gEfiRealTimeClockArchProtocolGuid AND\r
+ gEfiResetArchProtocolGuid AND\r
+ gEfiRuntimeArchProtocolGuid AND\r
+ gEfiSecurityArchProtocolGuid AND\r
+ gEfiTimerArchProtocolGuid AND\r
+ gEfiVariableWriteArchProtocolGuid AND\r
+ gEfiVariableArchProtocolGuid AND\r
+ gEfiWatchdogTimerArchProtocolGuid\r
projects / mirror_edk2.git / commitdiff