);\r
\r
if (UdmaOp == AtaUdmaReadExtOp || UdmaOp == AtaUdmaReadOp) {\r
- RegisterValue |= BMIC_nREAD;\r
+ RegisterValue |= BMIC_NREAD;\r
} else {\r
- RegisterValue &= ~((UINT8) BMIC_nREAD);\r
+ RegisterValue &= ~((UINT8) BMIC_NREAD);\r
}\r
\r
IdeDev->PciIo->Io.Write (\r
typedef union {\r
UINT16 AltStatus; /* when read */\r
UINT16 DeviceControl; /* when write */\r
-} IDE_AltStatus_OR_DeviceControl;\r
+} IDE_ALTSTATUS_OR_DEVICECONTROL;\r
\r
//\r
// IDE registers set\r
UINT16 Head;\r
IDE_CMD_OR_STATUS Reg;\r
\r
- IDE_AltStatus_OR_DeviceControl Alt;\r
+ IDE_ALTSTATUS_OR_DEVICECONTROL Alt;\r
UINT16 DriveAddress;\r
\r
UINT16 MasterSlave;\r
//\r
// Bus Master Reg\r
//\r
-#define BMIC_nREAD BIT3\r
+#define BMIC_NREAD BIT3\r
#define BMIC_START BIT0\r
#define BMIS_INTERRUPT BIT2\r
#define BMIS_ERROR BIT1\r
)\r
{\r
\r
- if (PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) {\r
+ if ((PciIoDevice->Pci.Hdr.Status & EFI_PCI_STATUS_CAPABILITY) != 0) {\r
return TRUE;\r
}\r
\r
)\r
{\r
EFI_STATUS Status;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *pConfiguration;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
UINT8 SubBusNumber;\r
UINT8 StartBusNumber;\r
UINT8 PaddedBusRange;\r
Status = PciResAlloc->StartBusEnumeration (\r
PciResAlloc,\r
RootBridgeHandle,\r
- (VOID **) &pConfiguration\r
+ (VOID **) &Configuration\r
);\r
\r
if (EFI_ERROR (Status)) {\r
//\r
// Get the bus number to start with\r
//\r
- StartBusNumber = (UINT8) (pConfiguration->AddrRangeMin);\r
- PaddedBusRange = (UINT8) (pConfiguration->AddrRangeMax);\r
+ StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
+ PaddedBusRange = (UINT8) (Configuration->AddrRangeMax);\r
\r
//\r
// Initialize the subordinate bus number\r
//\r
Status = PciScanBus (\r
RootBridgeDev,\r
- (UINT8) (pConfiguration->AddrRangeMin),\r
+ (UINT8) (Configuration->AddrRangeMin),\r
&SubBusNumber,\r
&PaddedBusRange\r
);\r
//\r
// Assign max bus number scanned\r
//\r
- pConfiguration->AddrLen = SubBusNumber - StartBusNumber + 1 + PaddedBusRange;\r
+ Configuration->AddrLen = SubBusNumber - StartBusNumber + 1 + PaddedBusRange;\r
\r
//\r
// Set bus number\r
Status = PciResAlloc->SetBusNumbers (\r
PciResAlloc,\r
RootBridgeHandle,\r
- pConfiguration\r
+ Configuration\r
);\r
\r
- gBS->FreePool (pConfiguration);\r
+ gBS->FreePool (Configuration);\r
\r
if (EFI_ERROR (Status)) {\r
return Status;\r
\r
UINT8 *Temp;\r
UINT64 ResStatus;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ptr;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *ACPIAddressDesc;\r
\r
Temp = (UINT8 *) AcpiConfig;\r
\r
while (*Temp == ACPI_ADDRESS_SPACE_DESCRIPTOR) {\r
\r
- ptr = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
- ResStatus = ptr->AddrTranslationOffset;\r
+ ACPIAddressDesc = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Temp;\r
+ ResStatus = ACPIAddressDesc->AddrTranslationOffset;\r
\r
- switch (ptr->ResType) {\r
+ switch (ACPIAddressDesc->ResType) {\r
case 0:\r
- if (ptr->AddrSpaceGranularity == 32) {\r
- if (ptr->SpecificFlag == 0x06) {\r
+ if (ACPIAddressDesc->AddrSpaceGranularity == 32) {\r
+ if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
//\r
// Pmem32\r
//\r
}\r
}\r
\r
- if (ptr->AddrSpaceGranularity == 64) {\r
- if (ptr->SpecificFlag == 0x06) {\r
+ if (ACPIAddressDesc->AddrSpaceGranularity == 64) {\r
+ if (ACPIAddressDesc->SpecificFlag == 0x06) {\r
//\r
// PMem64\r
//\r
// Check to see the granularity\r
//\r
if (Ptr->AddrSpaceGranularity == 32) {\r
- if (Ptr->SpecificFlag & 0x06) {\r
+ if ((Ptr->SpecificFlag & 0x06) != 0) {\r
*PMem32Base = Ptr->AddrRangeMin;\r
} else {\r
*Mem32Base = Ptr->AddrRangeMin;\r
}\r
\r
if (Ptr->AddrSpaceGranularity == 64) {\r
- if (Ptr->SpecificFlag & 0x06) {\r
+ if ((Ptr->SpecificFlag & 0x06) != 0) {\r
*PMem64Base = Ptr->AddrRangeMin;\r
} else {\r
*Mem64Base = Ptr->AddrRangeMin;\r
return FALSE;\r
}\r
\r
- if (CompareMem (DevicePath1, DevicePath2, Size1)) {\r
+ if (CompareMem (DevicePath1, DevicePath2, Size1) != 0) {\r
return FALSE;\r
}\r
\r
EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r
UINT16 MinBus;\r
EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r
- EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *pConfiguration;\r
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Configuration;\r
UINT8 StartBusNumber;\r
LIST_ENTRY RootBridgeList;\r
LIST_ENTRY *Link;\r
Status = PciResAlloc->StartBusEnumeration (\r
PciResAlloc,\r
RootBridgeHandle,\r
- (VOID **) &pConfiguration\r
+ (VOID **) &Configuration\r
);\r
if (EFI_ERROR (Status)) {\r
return Status;\r
//\r
// Get the bus number to start with\r
//\r
- StartBusNumber = (UINT8) (pConfiguration->AddrRangeMin);\r
+ StartBusNumber = (UINT8) (Configuration->AddrRangeMin);\r
\r
ResetAllPpbBusNumber (\r
RootBridgeDev,\r
StartBusNumber\r
);\r
\r
- gBS->FreePool (pConfiguration);\r
+ gBS->FreePool (Configuration);\r
Link = GetNextNode (&RootBridgeList, Link);\r
DestroyRootBridge (RootBridgeDev);\r
}\r
UINT16 OffsetPcir;\r
UINT32 RomBarOffset;\r
UINT32 RomBar;\r
- EFI_STATUS retStatus;\r
+ EFI_STATUS RetStatus;\r
BOOLEAN FirstCheck;\r
UINT8 *Image;\r
PCI_EXPANSION_ROM_HEADER *RomHeader;\r
RomDecode (PciDevice, RomBarIndex, RomBar, TRUE);\r
\r
RomBarOffset = RomBar;\r
- retStatus = EFI_NOT_FOUND;\r
+ RetStatus = EFI_NOT_FOUND;\r
FirstCheck = TRUE;\r
\r
do {\r
}\r
\r
if (RomImageSize > 0) {\r
- retStatus = EFI_SUCCESS;\r
+ RetStatus = EFI_SUCCESS;\r
Image = AllocatePool ((UINT32) RomImageSize);\r
if (Image == NULL) {\r
RomDecode (PciDevice, RomBarIndex, RomBar, FALSE);\r
gBS->FreePool (RomHeader);\r
gBS->FreePool (RomPcir);\r
\r
- return retStatus;\r
+ return RetStatus;\r
}\r
\r
/**\r
UINT8 *RomBarOffset;\r
EFI_HANDLE ImageHandle;\r
EFI_STATUS Status;\r
- EFI_STATUS retStatus;\r
+ EFI_STATUS RetStatus;\r
BOOLEAN FirstCheck;\r
BOOLEAN SkipImage;\r
UINT32 DestinationSize;\r
//\r
RomBar = PciDevice->PciIo.RomImage;\r
RomBarOffset = (UINT8 *) RomBar;\r
- retStatus = EFI_NOT_FOUND;\r
+ RetStatus = EFI_NOT_FOUND;\r
FirstCheck = TRUE;\r
\r
do {\r
(UINT64) (UINTN) PciDevice->PciIo.RomImage,\r
PciDevice->PciIo.RomSize\r
);\r
- retStatus = EFI_SUCCESS;\r
+ RetStatus = EFI_SUCCESS;\r
}\r
}\r
}\r
\r
} while (((Indicator & 0x80) == 0x00) && ((UINTN) (RomBarOffset - (UINT8 *) RomBar) < PciDevice->RomSize));\r
\r
- return retStatus;\r
+ return RetStatus;\r
\r
}\r
\r
{\r
EFI_STATUS Status;\r
UINT8 PowerManagementRegBlock;\r
- UINT16 PMCSR;\r
+ UINT16 PowerManagementCSR;\r
\r
PowerManagementRegBlock = 0;\r
\r
//\r
// Turn off the PWE assertion and put the device into D0 State\r
//\r
- PMCSR = 0x8000;\r
+ PowerManagementCSR = 0x8000;\r
\r
//\r
// Write PMCSR\r
EfiPciIoWidthUint16,\r
PowerManagementRegBlock + 4,\r
1,\r
- &PMCSR\r
+ &PowerManagementCSR\r
);\r
\r
return EFI_SUCCESS;\r
UINT64 Aperture;\r
LIST_ENTRY *CurrentLink;\r
PCI_RESOURCE_NODE *Node;\r
- UINT64 offset;\r
+ UINT64 Offset;\r
BOOLEAN IsaEnable;\r
BOOLEAN VGAEnable;\r
\r
//\r
// Consider the aperture alignment\r
//\r
- offset = Aperture & (Node->Alignment);\r
+ Offset = Aperture & (Node->Alignment);\r
\r
- if (offset != 0) {\r
+ if (Offset != 0) {\r
\r
- Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+ Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
\r
}\r
\r
&Aperture,\r
Node->Length \r
);\r
- offset = Aperture & (Node->Alignment);\r
- if (offset != 0) {\r
- Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+ Offset = Aperture & (Node->Alignment);\r
+ if (Offset != 0) {\r
+ Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
}\r
} else if (VGAEnable) {\r
SkipVGAAperture (\r
&Aperture,\r
Node->Length\r
);\r
- offset = Aperture & (Node->Alignment);\r
- if (offset != 0) {\r
- Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+ Offset = Aperture & (Node->Alignment);\r
+ if (Offset != 0) {\r
+ Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
}\r
}\r
}\r
// At last, adjust the aperture with the bridge's\r
// alignment\r
//\r
- offset = Aperture & (Bridge->Alignment);\r
+ Offset = Aperture & (Bridge->Alignment);\r
\r
- if (offset != 0) {\r
- Aperture = Aperture + (Bridge->Alignment + 1) - offset;\r
+ if (Offset != 0) {\r
+ Aperture = Aperture + (Bridge->Alignment + 1) - Offset;\r
}\r
\r
Bridge->Length = Aperture;\r
LIST_ENTRY *CurrentLink;\r
PCI_RESOURCE_NODE *Node;\r
\r
- UINT64 offset;\r
+ UINT64 Offset;\r
\r
Aperture = 0;\r
\r
// Apply padding resource if available\r
//\r
\r
- offset = Aperture & (Node->Alignment);\r
+ Offset = Aperture & (Node->Alignment);\r
\r
- if (offset != 0) {\r
+ if (Offset != 0) {\r
\r
- Aperture = Aperture + (Node->Alignment + 1) - offset;\r
+ Aperture = Aperture + (Node->Alignment + 1) - Offset;\r
\r
}\r
\r
// At last, adjust the aperture with the bridge's\r
// alignment\r
//\r
- offset = Aperture & (Bridge->Alignment);\r
- if (offset != 0) {\r
- Aperture = Aperture + (Bridge->Alignment + 1) - offset;\r
+ Offset = Aperture & (Bridge->Alignment);\r
+ if (Offset != 0) {\r
+ Aperture = Aperture + (Bridge->Alignment + 1) - Offset;\r
}\r
\r
//\r
// prefechable\r
//\r
if (Ptr->SpecificFlag == 0x6) {\r
- if (Ptr->AddrLen) {\r
+ if (Ptr->AddrLen != 0) {\r
Node = CreateResourceNode (\r
PciDev,\r
Ptr->AddrLen,\r
// Non-prefechable\r
//\r
if (Ptr->SpecificFlag == 0) {\r
- if (Ptr->AddrLen) {\r
+ if (Ptr->AddrLen != 0) {\r
Node = CreateResourceNode (\r
PciDev,\r
Ptr->AddrLen,\r
// prefechable\r
//\r
if (Ptr->SpecificFlag == 0x6) {\r
- if (Ptr->AddrLen) {\r
+ if (Ptr->AddrLen != 0) {\r
Node = CreateResourceNode (\r
PciDev,\r
Ptr->AddrLen,\r
// Non-prefechable\r
//\r
if (Ptr->SpecificFlag == 0) {\r
- if (Ptr->AddrLen) {\r
+ if (Ptr->AddrLen != 0) {\r
Node = CreateResourceNode (\r
PciDev,\r
Ptr->AddrLen,\r