QuarkSocPkg: IntelQNCLib: remove set but unused variables

This patch also removes a few PCI config space accesses, but that
shouldn't be a problem.

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Kelly Steele <kelly.steele@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

diff --git a/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c b/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c
index 5cb0fb8554603036c2922f84b999b67b730cc386..4b6f7ba773d4a80c24effcfd24287242406f8c82 100644 (file)
--- a/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c
+++ b/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/PciExpress.c
@@ -403,9 +403,6 @@ PcieSetAspmAuto (
   UINT32    EndpointPcieCapOffset;\r
   UINT16    RootPortAspm;\r
   UINT16    EndPointAspm;\r
-  UINT16    EndPointVendorId;\r
-  UINT16    EndPointDeviceId;\r
-  UINT8     EndPointRevId;\r
   UINT16    AspmVal;\r
   UINT32    PortLxLat;\r
   UINT32    EndPointLxLat;\r
@@ -438,14 +435,10 @@ PcieSetAspmAuto (
   EndPointAspm  = (QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, (EndpointPcieCapOffset + PCIE_LINK_CAP_OFFSET)) & B_QNC_PCIE_LCAP_APMS_MASK) >> V_QNC_PCIE_LCAP_APMS_OFFSET;\r
 \r
   //\r
-  // Mask APMC with values from lookup table.\r
+  // TODO: Mask APMC with values from lookup table.\r
   // RevID of 0xFF applies to all steppings.\r
   //\r
 \r
-  EndPointVendorId = QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, 0);\r
-  EndPointDeviceId = QNCMmPci16 (0, EndpointBus, EndpointDevice, EndpointFunction, 2);\r
-  EndPointRevId    = QNCMmPci8 (0, EndpointBus, EndpointDevice, EndpointFunction, 8);\r
-\r
   // TODO: Mask with latency/acceptable latency comparison results.\r
 \r
   AspmVal = RootPortAspm;\r
@@ -585,7 +578,6 @@ QNCRootPortInit (
 {\r
   UINT64            RPBase;\r
   UINT64            EndPointBase;\r
-  UINT64            LpcBase;\r
   UINT16            AspmVal;\r
   UINT16            SlotStatus;\r
   UINTN             Index;\r
@@ -593,7 +585,6 @@ QNCRootPortInit (
   UINT32            DwordReg;\r
 \r
   RPBase = PciExpressBar + (((PCI_BUS_NUMBER_QNC << 8) + ((PCI_DEVICE_NUMBER_PCIE_ROOTPORT) << 3) + ((PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 + RootPortIndex) << 0)) << 12);\r
-  LpcBase = PciExpressBar + (((PCI_BUS_NUMBER_QNC << 8) + (31 << 3) + (0 << 0)) << 12);\r
   CapOffset = PcieFindCapId (PCI_BUS_NUMBER_QNC, (UINT8)(PCI_DEVICE_NUMBER_PCIE_ROOTPORT), (UINT8)(PCI_FUNCTION_NUMBER_PCIE_ROOTPORT_0 + RootPortIndex), PCIE_CAPID);\r
 \r
   if (CapOffset == 0) {\r
@@ -906,7 +897,6 @@ PciExpressInit (
 {\r
   UINT64                            PciExpressBar;\r
   UINT32                            QNCRootComplexBar;\r
-  UINT32                            QNCGpioBase;\r
   UINT32                            QNCPmioBase;\r
   UINT32                            QNCGpeBase;\r
   UINTN                             RpEnableMask;\r
@@ -917,7 +907,6 @@ PciExpressInit (
   // Get BAR registers\r
   //\r
   QNCRootComplexBar  = QNC_RCRB_BASE;\r
-  QNCGpioBase        = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;\r
   QNCPmioBase        = LpcPciCfg32 (R_QNC_LPC_PM1BLK) & B_QNC_LPC_PM1BLK_MASK;\r
   QNCGpeBase         = LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & B_QNC_LPC_GPE0BLK_MASK;\r
   RpEnableMask = 0;                 // assume all root ports are disabled\r