Add definitions for Protected Region 1 register.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Shifei Lu <shifeix.a.lu@intel.com>
Reviewed-by: David Wei <david.wei@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17617 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
index 132c64b83742fa56eee29cc005a9b5acd580a906..7062a09b1becbe30a97823080a857bf22a47bc56 100644 (file)
--- a/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
+++ b/Vlv2DeviceRefCodePkg/ValleyView2Soc/SouthCluster/Include/PchRegs/PchRegsSpi.h
@@ -1,6 +1,6 @@
 /**\r
 \r
 /**\r
 \r

-Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved\r
+Copyright (c) 2011  - 2015, Intel Corporation. All rights reserved\r

 \r
   This program and the accompanying materials are licensed and made available under\r
   the terms and conditions of the BSD License that accompanies this distribution.\r
 \r
   This program and the accompanying materials are licensed and made available under\r
   the terms and conditions of the BSD License that accompanies this distribution.\r


@@ -62,6 +62,12 @@ Copyright (c) 2011  - 2014, Intel Corporation. All rights reserved
 #define B_PCH_SPI_PR0_RPE                    BIT15 // Read Protection Enable\r
 #define B_PCH_SPI_PR0_PRB_MASK               0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]\r
 \r
 #define B_PCH_SPI_PR0_RPE                    BIT15 // Read Protection Enable\r
 #define B_PCH_SPI_PR0_PRB_MASK               0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]\r
 \r

+#define R_PCH_SPI_PR1                        0x78  // Protected Region 1 Register\r
+#define B_PCH_SPI_PR1_WPE                    BIT31 // Write Protection Enable\r
+#define B_PCH_SPI_PR1_PRL_MASK               0x1FFF0000 // Protected Range Limit Mask, [28:16] here represents upper limit of address [24:12]\r
+#define B_PCH_SPI_PR1_RPE                    BIT15 // Read Protection Enable\r
+#define B_PCH_SPI_PR1_PRB_MASK               0x00001FFF // Protected Range Base Mask, [12:0] here represents base limit of address [24:12]\r
+\r

 #define R_PCH_SPI_PREOP                      0x94  // Prefix Opcode Configuration Register (16 bits)\r
 #define B_PCH_SPI_PREOP1_MASK                0xFF00 // Prefix Opcode 1 Mask\r
 #define B_PCH_SPI_PREOP0_MASK                0x00FF // Prefix Opcode 0 Mask\r
 #define R_PCH_SPI_PREOP                      0x94  // Prefix Opcode Configuration Register (16 bits)\r
 #define B_PCH_SPI_PREOP1_MASK                0xFF00 // Prefix Opcode 1 Mask\r
 #define B_PCH_SPI_PREOP0_MASK                0x00FF // Prefix Opcode 0 Mask\r