PcAtChipsetPkg: Fix spelling errors

https://bugzilla.tianocore.org/show_bug.cgi?id=2263

Cc: Ray Ni <ray.ni@intel.com>
Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>

diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
index ded3b5361922d2798172f0cf9778dc1971a77f5c..cbe986ebfd9f0ec9074039728edac902e6a8b388 100644 (file)
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimer.c
@@ -1,5 +1,5 @@
 /** @file\r
-  Timer Architectural Protocol module using High Precesion Event Timer (HPET)\r
+  Timer Architectural Protocol module using High Precision Event Timer (HPET)\r
 \r
   Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
@@ -246,7 +246,7 @@ HpetRead (
 /**\r
   Write a 64-bit HPET register.\r
 \r
-  @param  Offset  Specifies the ofsfert of the HPET register to write.\r
+  @param  Offset  Specifies the offset of the HPET register to write.\r
   @param  Value   Specifies the value to write to the HPET register specified by Offset.\r
 \r
   @return  The 64-bit value written to HPET register specified by Offset.\r
@@ -530,7 +530,7 @@ TimerDriverSetTimerPeriod (
     // If TimerPeriod is 0, then mask HPET Timer interrupts\r
     //\r
 \r
-    if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
+    if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
       //\r
       // Disable HPET MSI interrupt generation\r
       //\r
@@ -576,7 +576,7 @@ TimerDriverSetTimerPeriod (
     //\r
     // Enable HPET Timer interrupt generation\r
     //\r
-    if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
+    if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
       //\r
       // Program MSI Address and MSI Data values in the selected HPET Timer\r
       // Program HPET register with APIC ID of current BSP in case BSP has been switched\r
@@ -834,7 +834,7 @@ TimerDriverInitialize (
     //\r
     // Check to see if this HPET Timer supports MSI\r
     //\r
-    if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0) {\r
+    if (mTimerConfiguration.Bits.MsiInterruptCapability != 0) {\r
       //\r
       // Save the index of the first HPET Timer that supports MSI interrupts\r
       //\r
@@ -959,7 +959,7 @@ TimerDriverInitialize (
   // Show state of enabled HPET timer\r
   //\r
   DEBUG_CODE (\r
-    if (mTimerConfiguration.Bits.MsiInterruptCapablity != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
+    if (mTimerConfiguration.Bits.MsiInterruptCapability != 0 && FeaturePcdGet (PcdHpetMsiEnable)) {\r
       DEBUG ((DEBUG_INFO, "HPET Interrupt Mode MSI\n"));\r
     } else {\r
       DEBUG ((DEBUG_INFO, "HPET Interrupt Mode I/O APIC\n"));\r

diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
index ba2e075118f9b40ca0a58b5ba8bf7dcaaaa3736b..125eea0aab3424fd201bc84f74be0f27bdd7108f 100644 (file)
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.inf
@@ -1,5 +1,5 @@
 ## @file\r
-# Timer Architectural Protocol module using High Precesion Event Timer (HPET).\r
+# Timer Architectural Protocol module using High Precision Event Timer (HPET).\r
 #\r
 # Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>\r
 # SPDX-License-Identifier: BSD-2-Clause-Patent\r

diff --git a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
index e2320653b6f65b6c96b15fbfb9ed34bfde60f175..7d1797b1dfa5532f58f0dba48f4a625b7a69f9e7 100644 (file)
--- a/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
+++ b/PcAtChipsetPkg/HpetTimerDxe/HpetTimerDxe.uni
@@ -1,5 +1,5 @@
 // /** @file\r
-// Timer Architectural Protocol module using High Precesion Event Timer (HPET).\r
+// Timer Architectural Protocol module using High Precision Event Timer (HPET).\r
 //\r
 // Timer Architectural Protocol module using High Precision Event Timer (HPET).\r
 //\r

diff --git a/PcAtChipsetPkg/Include/Library/IoApicLib.h b/PcAtChipsetPkg/Include/Library/IoApicLib.h
index 200ef731fbef8a309c2aa948fb7d37344de51742..4ee092c0f213fdd9723a49e7820f31db99654488 100644 (file)
--- a/PcAtChipsetPkg/Include/Library/IoApicLib.h
+++ b/PcAtChipsetPkg/Include/Library/IoApicLib.h
@@ -63,7 +63,7 @@ IoApicEnableInterrupt (
   Configures an I/O APIC interrupt.\r
 \r
   Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical\r
-  mode to the Local APIC of the currntly executing CPU.  The default state of the\r
+  mode to the Local APIC of the currently executing CPU.  The default state of the\r
   entry is for the interrupt to be disabled (masked).  IoApicEnableInterrupts() must\r
   be used to enable(unmask) the I/O APIC Interrupt.\r
 \r

diff --git a/PcAtChipsetPkg/Include/Register/Hpet.h b/PcAtChipsetPkg/Include/Register/Hpet.h
index f7c0174e142baca070f34ea6400b2be1d31521b0..8437ec1f2dbb51bb4973e6066889129eefbbaa53 100644 (file)
--- a/PcAtChipsetPkg/Include/Register/Hpet.h
+++ b/PcAtChipsetPkg/Include/Register/Hpet.h
@@ -70,14 +70,14 @@ typedef union {
     UINT32  LevelTriggeredInterrupt:1;\r
     UINT32  InterruptEnable:1;\r
     UINT32  PeriodicInterruptEnable:1;\r
-    UINT32  PeriodicInterruptCapablity:1;\r
-    UINT32  CounterSizeCapablity:1;\r
+    UINT32  PeriodicInterruptCapability:1;\r
+    UINT32  CounterSizeCapability:1;\r
     UINT32  ValueSetEnable:1;\r
     UINT32  Reserved1:1;\r
     UINT32  CounterSizeEnable:1;\r
     UINT32  InterruptRoute:5;\r
     UINT32  MsiInterruptEnable:1;\r
-    UINT32  MsiInterruptCapablity:1;\r
+    UINT32  MsiInterruptCapability:1;\r
     UINT32  Reserved2:16;\r
     UINT32  InterruptRouteCapability;\r
   } Bits;\r

diff --git a/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c b/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c
index 7a3c9aca8d3ed4eba486fb7e6f17bbda22c12827..9e4a58049e494b7e40232dde601eaccc17157612 100644 (file)
--- a/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c
+++ b/PcAtChipsetPkg/Library/BaseIoApicLib/IoApicLib.c
@@ -94,7 +94,7 @@ IoApicEnableInterrupt (
   Configures an I/O APIC interrupt.\r
 \r
   Configure an I/O APIC Redirection Table Entry to deliver an interrupt in physical\r
-  mode to the Local APIC of the currntly executing CPU.  The default state of the\r
+  mode to the Local APIC of the currently executing CPU.  The default state of the\r
   entry is for the interrupt to be disabled (masked).  IoApicEnableInterrupts() must\r
   be used to enable(unmask) the I/O APIC Interrupt.\r
 \r

diff --git a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c b/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c
index 93affe151ed83a2c3f727df015b1981b7156c1ea..25c4cefc1381bac9907a89e1e440e81179e4f971 100644 (file)
--- a/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c
+++ b/PcAtChipsetPkg/Library/SerialIoLib/SerialPortLib.c
@@ -195,7 +195,7 @@ SerialPortRead (
 /**\r
   Polls a serial device to see if there is any data waiting to be read.\r
 \r
-  Polls aserial device to see if there is any data waiting to be read.\r
+  Polls a serial device to see if there is any data waiting to be read.\r
   If there is data waiting to be read from the serial device, then TRUE is returned.\r
   If there is no data waiting to be read from the serial device, then FALSE is returned.\r
 \r
@@ -339,13 +339,13 @@ SerialPortGetControl (
 }\r
 \r
 /**\r
-  Sets the baud rate, receive FIFO depth, transmit/receice time out, parity,\r
+  Sets the baud rate, receive FIFO depth, transmit/receive time out, parity,\r
   data bits, and stop bits on a serial device.\r
 \r
   @param BaudRate           The requested baud rate. A BaudRate value of 0 will use the\r
                             device's default interface speed.\r
                             On output, the value actually set.\r
-  @param ReveiveFifoDepth   The requested depth of the FIFO on the receive side of the\r
+  @param ReceiveFifoDepth   The requested depth of the FIFO on the receive side of the\r
                             serial interface. A ReceiveFifoDepth value of 0 will use\r
                             the device's default FIFO depth.\r
                             On output, the value actually set.\r
@@ -358,7 +358,7 @@ SerialPortGetControl (
                             DefaultParity will use the device's default parity value.\r
                             On output, the value actually set.\r
   @param DataBits           The number of data bits to use on the serial device. A DataBits\r
-                            vaule of 0 will use the device's default data bit setting.\r
+                            value of 0 will use the device's default data bit setting.\r
                             On output, the value actually set.\r
   @param StopBits           The number of stop bits to use on this serial device. A StopBits\r
                             value of DefaultStopBits will use the device's default number of\r

diff --git a/PcAtChipsetPkg/PcAtChipsetPkg.dec b/PcAtChipsetPkg/PcAtChipsetPkg.dec
index aad53b07c83257a47656755a34ed81e24095e65b..88de5cceea593176c3a2425a5963b66b789f2b9e 100644 (file)
--- a/PcAtChipsetPkg/PcAtChipsetPkg.dec
+++ b/PcAtChipsetPkg/PcAtChipsetPkg.dec
@@ -50,7 +50,7 @@
   # @Prompt HPET local APIC vector.\r
   gPcAtChipsetPkgTokenSpaceGuid.PcdHpetLocalApicVector|0x40|UINT8|0x0000000A\r
 \r
-  ## This PCD specifies the defaut period of the HPET Timer in 100 ns units.\r
+  ## This PCD specifies the default period of the HPET Timer in 100 ns units.\r
   #  The default value of 100000 100 ns units is the same as 10 ms.\r
   # @Prompt Default period of HPET timer.\r
   gPcAtChipsetPkgTokenSpaceGuid.PcdHpetDefaultTimerPeriod|100000|UINT64|0x0000000B\r

diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
index 8b68b0f19252fecd171fc4b71fc24b6b6a67c4c5..52af17941786ef81c3911512ee64551724e67209 100644 (file)
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.c
@@ -1051,9 +1051,9 @@ IsLeapYear (
 }\r
 \r
 /**\r
-  Converts time from EFI_TIME format defined by UEFI spec to RTC's.\r
+  Converts time from EFI_TIME format defined by UEFI spec to RTC format.\r
 \r
-  This function converts time from EFI_TIME format defined by UEFI spec to RTC's.\r
+  This function converts time from EFI_TIME format defined by UEFI spec to RTC format.\r
   If data mode of RTC is BCD, then converts EFI_TIME to it.\r
   If RTC is in 12-hour format, then converts EFI_TIME to it.\r
 \r

diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
index 038482d04d49ab4ebf9f8a606f3d16aed5d17c8a..47293ce44c5a1f4792892892f7da40d7f0a5a001 100644 (file)
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtc.h
@@ -110,7 +110,7 @@ typedef struct {
   UINT8 Uf : 1;       // Update End Interrupt Flag\r
   UINT8 Af : 1;       // Alarm Interrupt Flag\r
   UINT8 Pf : 1;       // Periodic Interrupt Flag\r
-  UINT8 Irqf : 1;     // Iterrupt Request Flag = PF & PIE | AF & AIE | UF & UIE\r
+  UINT8 Irqf : 1;     // Interrupt Request Flag = PF & PIE | AF & AIE | UF & UIE\r
 } RTC_REGISTER_C_BITS;\r
 \r
 typedef union {\r
@@ -234,7 +234,7 @@ PcRtcGetWakeupTime (
 /**\r
   The user Entry Point for PcRTC module.\r
 \r
-  This is the entrhy point for PcRTC module. It installs the UEFI runtime service\r
+  This is the entry point for PcRTC module. It installs the UEFI runtime service\r
   including GetTime(),SetTime(),GetWakeupTime(),and SetWakeupTime().\r
 \r
   @param  ImageHandle    The firmware allocated handle for the EFI image.\r
@@ -266,9 +266,9 @@ RtcTimeFieldsValid (
   );\r
 \r
 /**\r
-  Converts time from EFI_TIME format defined by UEFI spec to RTC's.\r
+  Converts time from EFI_TIME format defined by UEFI spec to RTC format.\r
 \r
-  This function converts time from EFI_TIME format defined by UEFI spec to RTC's.\r
+  This function converts time from EFI_TIME format defined by UEFI spec to RTC format.\r
   If data mode of RTC is BCD, then converts EFI_TIME to it.\r
   If RTC is in 12-hour format, then converts EFI_TIME to it.\r
 \r

diff --git a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
index dca3b8d9ff0629829ed728821602e29fbc3c8ebb..ccda6331373bfe4069b0a59495b5e5cc731c8fc8 100644 (file)
--- a/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
+++ b/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcRtcEntry.c
@@ -108,7 +108,7 @@ PcRtcEfiSetWakeupTime (
 /**\r
   The user Entry Point for PcRTC module.\r
 \r
-  This is the entrhy point for PcRTC module. It installs the UEFI runtime service\r
+  This is the entry point for PcRTC module. It installs the UEFI runtime service\r
   including GetTime(),SetTime(),GetWakeupTime(),and SetWakeupTime().\r
 \r
   @param  ImageHandle    The firmware allocated handle for the EFI image.\r