Import Pal.h and Sal.h.

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@2710 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/MdePkg/Include/IndustryStandard/Pal.h b/MdePkg/Include/IndustryStandard/Pal.h
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+/** @file\r
+  Main PAL API's defined in IPF PAL Spec.\r
+\r
+  Copyright (c) 2006 - 2007, Intel Corporation\r
+  All rights reserved. This program and the accompanying materials\r
+  are licensed and made available under the terms and conditions of the BSD License\r
+  which accompanies this distribution.  The full text of the license may be found at\r
+  http://opensource.org/licenses/bsd-license.php\r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+  Module Name:  PalApi.h\r
+\r
+**/\r
+\r
+#ifndef __PAL_API_H__\r
+#define __PAL_API_H__\r
+\r
+//\r
+// IPF Specific Functions\r
+//\r
+\r
+typedef struct {\r
+  UINT64                    Status;\r
+  UINT64                    r9;\r
+  UINT64                    r10;\r
+  UINT64                    r11;\r
+} PAL_CALL_RETURN;\r
+\r
+\r
+\r
+//\r
+// CacheType of PAL_CACHE_FLUSH.\r
+//\r
+#define PAL_CACHE_FLUSH_INSTRUCTION_ALL        1\r
+#define PAL_CACHE_FLUSH_DATA_ALL                                       2\r
+#define PAL_CACHE_FLUSH_ALL                                                            3\r
+#define PAL_CACHE_FLUSH_SYNC_TO_DATA                   4\r
+\r
+\r
+//\r
+// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
+// \r
+#define PAL_CACHE_FLUSH_INVIDED_LINES                  BIT0\r
+#define PAL_CACHE_FLUSH_PROBE_INTERRUPT                BIT1\r
+\r
+/**\r
+   \r
+  Flush the instruction or data caches. It is required by IPF.\r
+  The PAL procedure supports the Static Registers calling\r
+  convention. It could be called at virtual mode and physical\r
+  mode.\r
+\r
+  @param Index                                                         Index of PAL_CACHE_FLUSH within the\r
+                                                                                                               list of PAL procedures.\r
+  \r
+  @param CacheType                                     Unsigned 64-bit integer indicating\r
+                                                                                                               which cache to flush.\r
+\r
+  @param Operation                                     Formatted bit vector indicating the\r
+                                                                                                               operation of this call.\r
+\r
+  @param ProgressIndicator  Unsigned 64-bit integer specifying\r
+                            the starting position of the flush\r
+                            operation.\r
+  \r
+  @return R9                   Unsigned 64-bit integer specifying the vector\r
+                                                                       number of the pending interrupt.\r
+  \r
+  @return R10                  Unsigned 64-bit integer specifying the\r
+                  starting position of the flush operation.\r
+  \r
+  @return R11                  Unsigned 64-bit integer specifying the vector\r
+                                                                       number of the pending interrupt.\r
+  \r
+  @return Status       2 - Call completed without error, but a PMI\r
+                  was taken during the execution of this\r
+                  procedure.\r
+\r
+  @return Status       1 - Call has not completed flushing due to\r
+                  a pending interrupt.\r
+\r
+  @return Status  0 - Call completed without error\r
+\r
+  @return Status  -2 - Invalid argument\r
+\r
+  @return Status  -3 - Call completed with error\r
+   \r
+**/\r
+#define PAL_CACHE_FLUSH        1\r
+\r
+\r
+//\r
+// Attributes of PAL_CACHE_CONFIG_INFO1\r
+// \r
+#define PAL_CACHE_ATTR_WT      0\r
+#define PAL_CACHE_ATTR_WB              1\r
+\r
+//\r
+// PAL_CACHE_CONFIG_INFO1.StoreHint\r
+// \r
+#define PAL_CACHE_STORE_TEMPORAL                       0\r
+#define PAL_CACHE_STORE_NONE_TEMPORAL  3\r
+\r
+//\r
+// PAL_CACHE_CONFIG_INFO1.StoreHint\r
+// \r
+#define PAL_CACHE_STORE_TEMPORAL_LVL_1                         0\r
+#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL  3\r
+\r
+//\r
+// PAL_CACHE_CONFIG_INFO1.StoreHint\r
+// \r
+#define PAL_CACHE_LOAD_TEMPORAL_LVL_1                                  0\r
+#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1             1\r
+#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL   3\r
+\r
+//\r
+// Detail the characteristics of a given processor controlled\r
+// cache in the cache hierarchy.\r
+// \r
+typedef struct {\r
+       UINT64  IsUnified       : 1;\r
+       UINT64  Attributes      :       2;\r
+       UINT64  Associativity:8;\r
+       UINT64  LineSize:8;\r
+       UINT64  Stride:8;\r
+       UINT64  StoreLatency:8;\r
+       UINT64  StoreHint:8;\r
+       UINT64  LoadHint:8;\r
+} PAL_CACHE_INFO_RETURN1;\r
+\r
+//\r
+// Detail the characteristics of a given processor controlled\r
+// cache in the cache hierarchy.\r
+// \r
+typedef struct {\r
+       UINT64  CacheSize:32;\r
+       UINT64  AliasBoundary:8;\r
+       UINT64  TagLsBits:8;\r
+       UINT64  TagMsBits:8;\r
+} PAL_CACHE_INFO_RETURN2;\r
+\r
+/**\r
+   \r
+  Return detailed instruction or data cache information. It is\r
+  required by IPF. The PAL procedure supports the Static\r
+  Registers calling convention. It could be called at virtual\r
+  mode and physical mode.\r
+  \r
+  @param Index                                 Index of PAL_CACHE_INFO within the list of\r
+                                                                                       PAL procedures.\r
+  \r
+  @param CacheLevel            Unsigned 64-bit integer specifying the\r
+                      level in the cache hierarchy for which\r
+                      information is requested. This value must\r
+                      be between 0 and one less than the value\r
+                      returned in the cache_levels return value\r
+                      from PAL_CACHE_SUMMARY.\r
+  \r
+  @param CacheType    Unsigned 64-bit integer with a value of 1\r
+                      for instruction cache and 2 for data or\r
+                      unified cache. All other values are\r
+                      reserved.\r
+  \r
+  @param Reserved              Should be 0.\r
+  \r
+  \r
+  @return R9                   Detail the characteristics of a given\r
+                  processor controlled cache in the cache\r
+                  hierarchy. See PAL_CACHE_INFO_RETURN1.\r
+  \r
+  @return R10                  Detail the characteristics of a given\r
+                  processor controlled cache in the cache\r
+                  hierarchy. See PAL_CACHE_INFO_RETURN2.\r
+  \r
+  @return R11                  Reserved with 0.\r
+  \r
+  \r
+  @return Status  0 - Call completed without error\r
+\r
+  @return Status  -2 - Invalid argument\r
+\r
+  @return Status  -3 - Call completed with error\r
+   \r
+**/\r
+#define PAL_CACHE_INFO                 2\r
+\r
+\r
+\r
+//\r
+// Level of PAL_CACHE_INIT.\r
+// \r
+#define PAL_CACHE_INIT_ALL     0xffffffffffffffffULL\r
+\r
+//\r
+// Restrict of PAL_CACHE_INIT.\r
+// \r
+#define PAL_CACHE_INIT_NO_RESTRICT     0\r
+#define PAL_CACHE_INIT_RESTRICTED              1\r
+\r
+/**\r
+   \r
+  Initialize the instruction or data caches. It is required by\r
+  IPF. The PAL procedure supports the Static Registers calling\r
+  convention. It could be called at physical mode.\r
+\r
+  @param Index         Index of PAL_CACHE_INIT within the list of PAL\r
+                procedures.\r
+  \r
+  @param Level         Unsigned 64-bit integer containing the level of\r
+                cache to initialize. If the cache level can be\r
+                initialized independently, only that level will\r
+                be initialized. Otherwise\r
+                implementation-dependent side-effects will\r
+                occur.\r
+  \r
+  @param CacheType     Unsigned 64-bit integer with a value of 1 to\r
+                    initialize the instruction cache, 2 to\r
+                    initialize the data cache, or 3 to\r
+                    initialize both. All other values are\r
+                    reserved.\r
+\r
+  @param Restrict      Unsigned 64-bit integer with a value of 0 or\r
+                    1. All other values are reserved. If\r
+                    restrict is 1 and initializing the specified\r
+                    level and cache_type of the cache would\r
+                    cause side-effects, PAL_CACHE_INIT will\r
+                    return -4 instead of initializing the cache.\r
+ \r
+  \r
+  @return Status  0 - Call completed without error\r
+\r
+  @return Status  -2 - Invalid argument\r
+\r
+  @return Status  -3 - Call completed with error.\r
+  \r
+  @return Status  -4 - Call could not initialize the specified\r
+                  level and cache_type of the cache without\r
+                                                                       side-effects and restrict was 1.  \r
+   \r
+**/\r
+#define PAL_CACHE_INIT                 3 \r
+\r
+\r
+//\r
+// PAL_CACHE_PROTECTION.Method.\r
+// \r
+#define PAL_CACHE_PROTECTION_NONE_PROTECT              0\r
+#define PAL_CACHE_PROTECTION_ODD_PROTECT               1\r
+#define PAL_CACHE_PROTECTION_EVEN_PROTECT              2\r
+#define PAL_CACHE_PROTECTION_ECC_PROTECT               3\r
+\r
+\r
+\r
+//\r
+// PAL_CACHE_PROTECTION.TagOrData.\r
+// \r
+#define PAL_CACHE_PROTECTION_PROTECT_DATA              0\r
+#define PAL_CACHE_PROTECTION_PROTECT_TAG               1\r
+#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA          2\r
+#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG          3\r
+\r
+//\r
+// 32-bit protection information structures.\r
+// \r
+typedef struct {\r
+       UINT32  DataBits:8;\r
+       UINT32  TagProtLsb:6;\r
+       UINT32  TagProtMsb:6;\r
+       UINT32  ProtBits:6;\r
+       UINT32  Method:4;\r
+       UINT32  TagOrData:2;\r
+} PAL_CACHE_PROTECTION;\r
+\r
+/**\r
+   \r
+  Return instruction or data cache protection information. It is\r
+  required by IPF. The PAL procedure supports the Static\r
+  Registers calling convention. It could be called at physical\r
+  mode and Virtual mode.\r
+\r
+  @param Index         Index of PAL_CACHE_PROT_INFO within the list of\r
+                PAL procedures.\r
+\r
+  @param CacheLevel    Unsigned 64-bit integer specifying the level\r
+                    in the cache hierarchy for which information\r
+                    is requested. This value must be between 0\r
+                    and one less than the value returned in the\r
+                    cache_levels return value from\r
+                    PAL_CACHE_SUMMARY.\r
+\r
+  @param CacheType     Unsigned 64-bit integer with a value of 1\r
+                    for instruction cache and 2 for data or\r
+                    unified cache. All other values are\r
+                    reserved.\r
+  \r
+  @return R9                   Detail the characteristics of a given\r
+                  processor controlled cache in the cache\r
+                  hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
+  \r
+  @return R10                  Detail the characteristics of a given\r
+                  processor controlled cache in the cache\r
+                  hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
+  \r
+  @return R11                  Detail the characteristics of a given\r
+                  processor controlled cache in the cache\r
+                  hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
+  \r
+  \r
+  @return Status  0 - Call completed without error\r
+\r
+  @return Status  -2 - Invalid argument\r
+\r
+  @return Status  -3 - Call completed with error.\r
+   \r
+**/\r
+#define PAL_CACHE_PROT_INFO            38\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+///\r
+// ?????????\r
+\r
+\r
+\r
+/**\r
+   \r
+  Returns information on which logical processors share caches.\r
+  It is optional.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_CACHE_SHARED_INFO  43\r
+\r
+\r
+/**\r
+   \r
+  Return a summary of the cache hierarchy. It is required by\r
+  IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_CACHE_SUMMARY              4\r
+\r
+/**\r
+   \r
+  Return a list of supported memory attributes.. It is required\r
+  by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_MEM_ATTRIB                         5\r
+\r
+/**\r
+   \r
+  Used in architected sequence to transition pages from a\r
+  cacheable, speculative attribute to an uncacheable attribute.\r
+  It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_PREFETCH_VISIBILITY        41\r
+\r
+/**\r
+   \r
+  Return information needed for ptc.e instruction to purge\r
+  entire TC. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_PTCE_INFO          6\r
+\r
+/**\r
+   \r
+  Return detailed information about virtual memory features\r
+  supported in the processor. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_VM_INFO                    7\r
+\r
+\r
+/**\r
+   \r
+  Return virtual memory TC and hardware walker page sizes\r
+  supported in the processor. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_VM_PAGE_SIZE 34\r
+\r
+/**\r
+   \r
+  Return summary information about virtual memory features\r
+  supported in the processor. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_VM_SUMMARY         8\r
+\r
+/**\r
+   \r
+  Read contents of a translation register. It is required by\r
+  IPF.\r
+\r
+  @param CallingConvention  Stacked Register\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_VM_TR_READ         261 \r
+\r
+/**\r
+   \r
+  Return configurable processor bus interface features and their\r
+  current settings. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_BUS_GET_FEATURES 9\r
+\r
+\r
+/**\r
+   \r
+  Enable or disable configurable features in processor bus\r
+  interface. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_BUS_SET_FEATURES 10\r
+\r
+\r
+/**\r
+   \r
+  Return the number of instruction and data breakpoint\r
+  registers. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_DEBUG_INFO         11\r
+\r
+/**\r
+   \r
+  Return the fixed component of a processor¡¯s directed address.\r
+  It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_FIXED_ADDR 12\r
+\r
+/**\r
+   \r
+  Return the frequency of the output clock for use by the\r
+  platform, if generated by the processor. It is optinal.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_FREQ_BASE 13\r
+\r
+/**\r
+   \r
+  Return ratio of processor, bus, and interval time counter to\r
+  processor input clock or output clock for platform use, if\r
+  generated by the processor. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_FREQ_RATIOS 14\r
+\r
+/**\r
+   \r
+  Return information on which logical processors map to a\r
+  physical processor die. It is optinal.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_LOGICAL_TO_PHYSICAL 42\r
+\r
+/**\r
+   \r
+  Return the number and type of performance monitors. It is\r
+  required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_PERF_MON_INFO 15\r
+\r
+/**\r
+   \r
+  Specify processor interrupt block address and I/O port space\r
+  address. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_PLATFORM_ADDR 16\r
+\r
+\r
+/**\r
+   \r
+  Return configurable processor features and their current\r
+  setting. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_PROC_GET_FEATURES 17\r
+\r
+\r
+/**\r
+   \r
+  Enable or disable configurable processor features. It is\r
+  required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_PROC_SET_FEATURES 18\r
+\r
+/**\r
+   \r
+  Return AR and CR register information. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_REGISTER_INFO 39 \r
+\r
+/**\r
+   \r
+  Return RSE information. It is required by\r
+  IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_RSE_INFO 19\r
+\r
+/**\r
+   \r
+  Return version of PAL code. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_VERSION 20\r
+\r
+/**\r
+   \r
+  Clear all error information from processor error logging\r
+  registers. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_MC_CLEAR_LOG 21 \r
+\r
+/**\r
+   \r
+  Ensure that all operations that could cause an MCA have\r
+  completed. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_MC_DRAIN 22\r
+\r
+/**\r
+   \r
+  Return Processor Dynamic State for logging by SAL. It is\r
+  optional.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_MC_DYNAMIC_STATE 24 \r
+\r
+/**\r
+   \r
+  Return Processor Machine Check Information and Processor\r
+  Static State for logging by SAL. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_MC_ERROR_INFO 25 Req. Static Both \r
+\r
+/**\r
+   \r
+  Set/Reset Expected Machine Check Indicator. It is required by\r
+  IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_MC_EXPECTED 23 \r
+\r
+/**\r
+   \r
+  Register min-state save area with PAL for machine checks and\r
+  inits. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_MC_REGISTER_MEM 27 \r
+\r
+/**\r
+   \r
+  Restore minimal architected state and return to interrupted\r
+  process. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_MC_RESUME 26 \r
+\r
+/**\r
+   \r
+  Enter the low-power HALT state or an implementation-dependent\r
+  low-power state. It is optinal.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_HALT 28\r
+\r
+\r
+/**\r
+   \r
+  Return the low power capabilities of the processor. It is\r
+  required by IPF.\r
+\r
+  @param CallingConvention  Stacked Register\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_HALT_INFO 257\r
+\r
+\r
+/**\r
+   \r
+  Enter the low power LIGHT HALT state. It is required by\r
+  IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical/Virtual\r
+   \r
+**/\r
+#define PAL_HALT_LIGHT 29 \r
+\r
+/**\r
+   \r
+  Initialize tags and data of a cache line for processor\r
+  testing. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_CACHE_LINE_INIT 31\r
+\r
+/**\r
+   \r
+  Read tag and data of a cache line for diagnostic testing. It\r
+  is optional.\r
+\r
+  @param CallingConvention  Satcked Register\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_CACHE_READ 259 \r
+\r
+/**\r
+   \r
+  Write tag and data of a cache for diagnostic testing. It is\r
+  optional.\r
+\r
+  @param CallingConvention  Satcked Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_CACHE_WRITE 260\r
+\r
+/**\r
+   \r
+  Returns alignment and size requirements needed for the memory\r
+  buffer passed to the PAL_TEST_PROC procedure as well as\r
+  information on self-test control words for the processor self\r
+  tests. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_TEST_INFO 37\r
+\r
+/**\r
+   \r
+  Perform late processor self test. It is required by\r
+  IPF.\r
+\r
+  @param CallingConvention  Stacked Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_TEST_PROC 258\r
+\r
+/**\r
+   \r
+  Return information needed to relocate PAL procedures and PAL\r
+  PMI code to memory. It is required by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_COPY_INFO 30\r
+\r
+/**\r
+   \r
+  Relocate PAL procedures and PAL PMI code to memory. It is\r
+  required by IPF.\r
+\r
+  @param CallingConvention  Stacked Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_COPY_PAL 256\r
+\r
+/**\r
+   \r
+  Enter IA-32 System environment. It is optional.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_ENTER_IA_32_ENV 33\r
+\r
+/**\r
+   \r
+  Register PMI memory entrypoints with processor. It is required\r
+  by IPF.\r
+\r
+  @param CallingConvention  Static Registers\r
+\r
+  @param Mode               Physical\r
+   \r
+**/\r
+#define PAL_PMI_ENTRYPOINT 32\r
+\r
+\r
+\r
+#endif\r

diff --git a/MdePkg/Include/IndustryStandard/Sal.h b/MdePkg/Include/IndustryStandard/Sal.h
new file mode 100644 (file)
index 0000000..6f889aa
--- /dev/null
+++ b/MdePkg/Include/IndustryStandard/Sal.h
@@ -0,0 +1,721 @@
+/** @file\r
+  Main SAL API's defined in SAL 3.0 specification. \r
+\r
+  Copyright (c) 2006, Intel Corporation                                                         \r
+  All rights reserved. This program and the accompanying materials                          \r
+  are licensed and made available under the terms and conditions of the BSD License         \r
+  which accompanies this distribution.  The full text of the license may be found at        \r
+  http://opensource.org/licenses/bsd-license.php                                            \r
+\r
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     \r
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.             \r
+\r
+  Module Name:  SalApi.h\r
+\r
+**/\r
+\r
+#ifndef __SAL_API_H__\r
+#define __SAL_API_H__\r
+\r
+//\r
+// FIT Types \r
+// Table 2-2 of Intel Itanium Processor Family System Abstraction Layer Specification December 2003\r
+//\r
+#define EFI_SAL_FIT_FIT_HEADER_TYPE 0x00\r
+#define EFI_SAL_FIT_PAL_B_TYPE      0x01\r
+//\r
+// type from 0x02 to 0x0E is reserved.\r
+//\r
+#define EFI_SAL_FIT_PAL_A_TYPE  0x0F\r
+//\r
+// OEM-defined type range is from 0x10 to 0x7E. Here we defined the PEI_CORE type as 0x10\r
+//\r
+#define EFI_SAL_FIT_PEI_CORE_TYPE 0x10\r
+#define EFI_SAL_FIT_UNUSED_TYPE   0x7F\r
+\r
+//\r
+// EFI_SAL_STATUS \r
+//\r
+typedef UINTN EFI_SAL_STATUS;\r
+\r
+#define EFI_SAL_SUCCESS               ((EFI_SAL_STATUS) 0)\r
+#define EFI_SAL_MORE_RECORDS          ((EFI_SAL_STATUS) 3)\r
+#define EFI_SAL_NOT_IMPLEMENTED       ((EFI_SAL_STATUS) - 1)\r
+#define EFI_SAL_INVALID_ARGUMENT      ((EFI_SAL_STATUS) - 2)\r
+#define EFI_SAL_ERROR                 ((EFI_SAL_STATUS) - 3)\r
+#define EFI_SAL_VIRTUAL_ADDRESS_ERROR ((EFI_SAL_STATUS) - 4)\r
+#define EFI_SAL_NO_INFORMATION        ((EFI_SAL_STATUS) - 5)\r
+#define EFI_SAL_NOT_ENOUGH_SCRATCH    ((EFI_SAL_STATUS) - 9)\r
+\r
+//\r
+//  Return values from SAL\r
+//\r
+typedef struct {\r
+  EFI_SAL_STATUS  Status; // register r8\r
+  UINTN           r9;\r
+  UINTN           r10;\r
+  UINTN           r11;\r
+} SAL_RETURN_REGS;\r
+\r
+//\r
+//  Delivery Mode of IPF CPU.\r
+//\r
+typedef enum {\r
+  EFI_DELIVERY_MODE_INT,\r
+  EFI_DELIVERY_MODE_MPreserved1,\r
+  EFI_DELIVERY_MODE_PMI,\r
+  EFI_DELIVERY_MODE_MPreserved2,\r
+  EFI_DELIVERY_MODE_NMI,\r
+  EFI_DELIVERY_MODE_INIT,\r
+  EFI_DELIVERY_MODE_MPreserved3,\r
+  EFI_DELIVERY_MODE_ExtINT\r
+} EFI_DELIVERY_MODE;\r
+\r
+typedef SAL_RETURN_REGS (EFIAPI *SAL_PROC)\r
+  (\r
+    IN UINT64 FunctionId,\r
+    IN UINT64 Arg2,\r
+    IN UINT64 Arg3,\r
+    IN UINT64 Arg4,\r
+    IN UINT64 Arg5,\r
+    IN UINT64 Arg6,\r
+    IN UINT64 Arg7,\r
+    IN UINT64 Arg8\r
+  );\r
+\r
+//\r
+// SAL Procedure FunctionId definition\r
+//\r
+#define EFI_SAL_SET_VECTORS             0x01000000\r
+#define EFI_SAL_GET_STATE_INFO          0x01000001\r
+#define EFI_SAL_GET_STATE_INFO_SIZE     0x01000002\r
+#define EFI_SAL_CLEAR_STATE_INFO        0x01000003\r
+#define EFI_SAL_MC_RENDEZ               0x01000004\r
+#define EFI_SAL_MC_SET_PARAMS           0x01000005\r
+#define EFI_SAL_REGISTER_PHYSICAL_ADDR  0x01000006\r
+#define EFI_SAL_CACHE_FLUSH             0x01000008\r
+#define EFI_SAL_CACHE_INIT              0x01000009\r
+#define EFI_SAL_PCI_CONFIG_READ         0x01000010\r
+#define EFI_SAL_PCI_CONFIG_WRITE        0x01000011\r
+#define EFI_SAL_FREQ_BASE               0x01000012\r
+#define EFI_SAL_UPDATE_PAL              0x01000020\r
+\r
+#define EFI_SAL_FUNCTION_ID_MASK        0x0000ffff\r
+#define EFI_SAL_MAX_SAL_FUNCTION_ID     0x00000021\r
+\r
+//\r
+// SAL Procedure parameter definitions\r
+// Not much point in using typedefs or enums because all params\r
+// are UINT64 and the entry point is common\r
+//\r
+// EFI_SAL_SET_VECTORS\r
+//\r
+#define EFI_SAL_SET_MCA_VECTOR          0x0\r
+#define EFI_SAL_SET_INIT_VECTOR         0x1\r
+#define EFI_SAL_SET_BOOT_RENDEZ_VECTOR  0x2\r
+\r
+typedef struct {\r
+  UINT64  Length : 32;\r
+  UINT64  ChecksumValid : 1;\r
+  UINT64  Reserved1 : 7;\r
+  UINT64  ByteChecksum : 8;\r
+  UINT64  Reserved2 : 16;\r
+} SAL_SET_VECTORS_CS_N;\r
+\r
+//\r
+// EFI_SAL_GET_STATE_INFO, EFI_SAL_GET_STATE_INFO_SIZE,\r
+// EFI_SAL_CLEAR_STATE_INFO\r
+//\r
+#define EFI_SAL_MCA_STATE_INFO  0x0\r
+#define EFI_SAL_INIT_STATE_INFO 0x1\r
+#define EFI_SAL_CMC_STATE_INFO  0x2\r
+#define EFI_SAL_CP_STATE_INFO   0x3\r
+\r
+//\r
+// EFI_SAL_MC_SET_PARAMS\r
+//\r
+#define EFI_SAL_MC_SET_RENDEZ_PARAM 0x1\r
+#define EFI_SAL_MC_SET_WAKEUP_PARAM 0x2\r
+#define EFI_SAL_MC_SET_CPE_PARAM    0x3\r
+\r
+#define EFI_SAL_MC_SET_INTR_PARAM   0x1\r
+#define EFI_SAL_MC_SET_MEM_PARAM    0x2\r
+\r
+//\r
+// EFI_SAL_REGISTER_PAL_PHYSICAL_ADDR\r
+//\r
+#define EFI_SAL_REGISTER_PAL_ADDR 0x0\r
+\r
+//\r
+// EFI_SAL_CACHE_FLUSH\r
+//\r
+#define EFI_SAL_FLUSH_I_CACHE       0x01\r
+#define EFI_SAL_FLUSH_D_CACHE       0x02\r
+#define EFI_SAL_FLUSH_BOTH_CACHE    0x03\r
+#define EFI_SAL_FLUSH_MAKE_COHERENT 0x04\r
+\r
+//\r
+// EFI_SAL_PCI_CONFIG_READ, EFI_SAL_PCI_CONFIG_WRITE\r
+//\r
+#define EFI_SAL_PCI_CONFIG_ONE_BYTE   0x1\r
+#define EFI_SAL_PCI_CONFIG_TWO_BYTES  0x2\r
+#define EFI_SAL_PCI_CONFIG_FOUR_BYTES 0x4\r
+\r
+typedef struct {\r
+  UINT64  Register : 8;\r
+  UINT64  Function : 3;\r
+  UINT64  Device : 5;\r
+  UINT64  Bus : 8;\r
+  UINT64  Segment : 8;\r
+  UINT64  Reserved : 32;\r
+} SAL_PCI_ADDRESS;\r
+\r
+//\r
+// EFI_SAL_FREQ_BASE\r
+//\r
+#define EFI_SAL_CPU_INPUT_FREQ_BASE     0x0\r
+#define EFI_SAL_PLATFORM_IT_FREQ_BASE   0x1\r
+#define EFI_SAL_PLATFORM_RTC_FREQ_BASE  0x2\r
+\r
+//\r
+// EFI_SAL_UPDATE_PAL\r
+//\r
+#define EFI_SAL_UPDATE_BAD_PAL_VERSION  ((UINT64) -1)\r
+#define EFI_SAL_UPDATE_PAL_AUTH_FAIL    ((UINT64) -2)\r
+#define EFI_SAL_UPDATE_PAL_BAD_TYPE     ((UINT64) -3)\r
+#define EFI_SAL_UPDATE_PAL_READONLY     ((UINT64) -4)\r
+#define EFI_SAL_UPDATE_PAL_WRITE_FAIL   ((UINT64) -10)\r
+#define EFI_SAL_UPDATE_PAL_ERASE_FAIL   ((UINT64) -11)\r
+#define EFI_SAL_UPDATE_PAL_READ_FAIL    ((UINT64) -12)\r
+#define EFI_SAL_UPDATE_PAL_CANT_FIT     ((UINT64) -13)\r
+\r
+typedef struct {\r
+  UINT32  Size;\r
+  UINT32  MmddyyyyDate;\r
+  UINT16  Version;\r
+  UINT8   Type;\r
+  UINT8   Reserved[5];\r
+  UINT64  FwVendorId;\r
+} SAL_UPDATE_PAL_DATA_BLOCK;\r
+\r
+typedef struct _SAL_UPDATE_PAL_INFO_BLOCK {\r
+  struct _SAL_UPDATE_PAL_INFO_BLOCK *Next;\r
+  struct SAL_UPDATE_PAL_DATA_BLOCK  *DataBlock;\r
+  UINT8                             StoreChecksum;\r
+  UINT8                             Reserved[15];\r
+} SAL_UPDATE_PAL_INFO_BLOCK;\r
+\r
+//\r
+// SAL System Table Definitions\r
+//\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT32  Signature;\r
+  UINT32  Length;\r
+  UINT16  SalRevision;\r
+  UINT16  EntryCount;\r
+  UINT8   CheckSum;\r
+  UINT8   Reserved[7];\r
+  UINT16  SalAVersion;\r
+  UINT16  SalBVersion;\r
+  UINT8   OemId[32];\r
+  UINT8   ProductId[32];\r
+  UINT8   Reserved2[8];\r
+} SAL_SYSTEM_TABLE_HEADER;\r
+#pragma pack()\r
+\r
+#define EFI_SAL_ST_HEADER_SIGNATURE "SST_"\r
+#define EFI_SAL_REVISION            0x0300\r
+//\r
+// SAL System Types\r
+//\r
+#define EFI_SAL_ST_ENTRY_POINT        0\r
+#define EFI_SAL_ST_MEMORY_DESCRIPTOR  1\r
+#define EFI_SAL_ST_PLATFORM_FEATURES  2\r
+#define EFI_SAL_ST_TR_USAGE           3\r
+#define EFI_SAL_ST_PTC                4\r
+#define EFI_SAL_ST_AP_WAKEUP          5\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT8   Type; //  Type == 0\r
+  UINT8   Reserved[7];\r
+  UINT64  PalProcEntry;\r
+  UINT64  SalProcEntry;\r
+  UINT64  SalGlobalDataPointer;\r
+  UINT64  Reserved2[2];\r
+} SAL_ST_ENTRY_POINT_DESCRIPTOR;\r
+\r
+//\r
+// Not needed for Itanium-based OS boot\r
+//\r
+typedef struct {\r
+  UINT8   Type; //  Type == 1\r
+  UINT8   NeedVirtualRegistration;\r
+  UINT8   MemoryAttributes;\r
+  UINT8   PageAccessRights;\r
+  UINT8   SupportedAttributes;\r
+  UINT8   Reserved;\r
+  UINT8   MemoryType;\r
+  UINT8   MemoryUsage;\r
+  UINT64  PhysicalMemoryAddress;\r
+  UINT32  Length;\r
+  UINT32  Reserved1;\r
+  UINT64  OemReserved;\r
+} SAL_ST_MEMORY_DESCRIPTOR_ENTRY;\r
+\r
+#pragma pack()\r
+//\r
+// Memory Attributes\r
+//\r
+#define SAL_MDT_ATTRIB_WB 0x00\r
+//\r
+// #define SAL_MDT_ATTRIB_UC   0x02\r
+//\r
+#define SAL_MDT_ATTRIB_UC   0x04\r
+#define SAL_MDT_ATTRIB_UCE  0x05\r
+#define SAL_MDT_ATTRIB_WC   0x06\r
+\r
+//\r
+// Supported memory Attributes\r
+//\r
+#define SAL_MDT_SUPPORT_WB  0x1\r
+#define SAL_MDT_SUPPORT_UC  0x2\r
+#define SAL_MDT_SUPPORT_UCE 0x4\r
+#define SAL_MDT_SUPPORT_WC  0x8\r
+\r
+//\r
+// Virtual address registration\r
+//\r
+#define SAL_MDT_NO_VA   0x00\r
+#define SAL_MDT_NEED_VA 0x01\r
+//\r
+// MemoryType info\r
+//\r
+#define SAL_REGULAR_MEMORY  0x0000\r
+#define SAL_MMIO_MAPPING    0x0001\r
+#define SAL_SAPIC_IPI_BLOCK 0x0002\r
+#define SAL_IO_PORT_MAPPING 0x0003\r
+#define SAL_FIRMWARE_MEMORY 0x0004\r
+#define SAL_BLACK_HOLE      0x000A\r
+//\r
+// Memory Usage info\r
+//\r
+#define SAL_MDT_USAGE_UNSPECIFIED 0x00\r
+#define SAL_PAL_CODE              0x01\r
+#define SAL_BOOTSERVICE_CODE      0x02\r
+#define SAL_BOOTSERVICE_DATA      0x03\r
+#define SAL_RUNTIMESERVICE_CODE   0x04\r
+#define SAL_RUNTIMESERVICE_DATA   0x05\r
+#define SAL_IA32_OPTIONROM        0x06\r
+#define SAL_IA32_SYSTEMROM        0x07\r
+#define SAL_PMI_CODE              0x0a\r
+#define SAL_PMI_DATA              0x0b\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT8 Type;                     // Type == 2\r
+  UINT8 PlatformFeatures;\r
+  UINT8 Reserved[14];\r
+} SAL_ST_PLATFORM_FEATURES;\r
+#pragma pack()\r
+\r
+#define SAL_PLAT_FEAT_BUS_LOCK      0x01\r
+#define SAL_PLAT_FEAT_PLAT_IPI_HINT 0x02\r
+#define SAL_PLAT_FEAT_PROC_IPI_HINT 0x04\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT8   Type;                   // Type == 3\r
+  UINT8   TRType;\r
+  UINT8   TRNumber;\r
+  UINT8   Reserved[5];\r
+  UINT64  VirtualAddress;\r
+  UINT64  EncodedPageSize;\r
+  UINT64  Reserved1;\r
+} SAL_ST_TR_DECRIPTOR;\r
+#pragma pack()\r
+\r
+#define EFI_SAL_ST_TR_USAGE_INSTRUCTION 00\r
+#define EFI_SAL_ST_TR_USAGE_DATA        01\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT64  NumberOfProcessors;\r
+  UINT64  LocalIDRegister;\r
+} SAL_COHERENCE_DOMAIN_INFO;\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT8                     Type; // Type == 4\r
+  UINT8                     Reserved[3];\r
+  UINT32                    NumberOfDomains;\r
+  SAL_COHERENCE_DOMAIN_INFO *DomainInformation;\r
+} SAL_ST_CACHE_COHERENCE_DECRIPTOR;\r
+#pragma pack()\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+  UINT8   Type;                   // Type == 5\r
+  UINT8   WakeUpType;\r
+  UINT8   Reserved[6];\r
+  UINT64  ExternalInterruptVector;\r
+} SAL_ST_AP_WAKEUP_DECRIPTOR;\r
+#pragma pack()\r
+//\r
+// FIT Entry\r
+//\r
+#define EFI_SAL_FIT_ENTRY_PTR   (0x100000000 - 32)  // 4GB - 24\r
+#define EFI_SAL_FIT_PALA_ENTRY  (0x100000000 - 48)  // 4GB - 32\r
+#define EFI_SAL_FIT_PALB_TYPE   01\r
+\r
+typedef struct {\r
+  UINT64  Address;\r
+  UINT8   Size[3];\r
+  UINT8   Reserved;\r
+  UINT16  Revision;\r
+  UINT8   Type : 7;\r
+  UINT8   CheckSumValid : 1;\r
+  UINT8   CheckSum;\r
+} EFI_SAL_FIT_ENTRY;\r
+\r
+//\r
+//  SAL Common Record Header\r
+//\r
+typedef struct {\r
+  UINT16  Length;\r
+  UINT8   Data[1024];\r
+} SAL_OEM_DATA;\r
+\r
+typedef struct {\r
+  UINT8 Seconds;\r
+  UINT8 Minutes;\r
+  UINT8 Hours;\r
+  UINT8 Reserved;\r
+  UINT8 Day;\r
+  UINT8 Month;\r
+  UINT8 Year;\r
+  UINT8 Century;\r
+} SAL_TIME_STAMP;\r
+\r
+typedef struct {\r
+  UINT64          RecordId;\r
+  UINT16          Revision;\r
+  UINT8           ErrorSeverity;\r
+  UINT8           ValidationBits;\r
+  UINT32          RecordLength;\r
+  SAL_TIME_STAMP  TimeStamp;\r
+  UINT8           OemPlatformId[16];\r
+} SAL_RECORD_HEADER;\r
+\r
+typedef struct {\r
+  GUID                 Guid;\r
+  UINT16    Revision;\r
+  UINT8     ErrorRecoveryInfo;\r
+  UINT8     Reserved;\r
+  UINT32    SectionLength;\r
+} SAL_SEC_HEADER;\r
+\r
+//\r
+// SAL Processor Record\r
+//\r
+#define SAL_PROCESSOR_ERROR_RECORD_INFO \\r
+  { \\r
+    0xe429faf1, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
+  }\r
+\r
+#define CHECK_INFO_VALID_BIT_MASK   0x1\r
+#define REQUESTOR_ID_VALID_BIT_MASK 0x2\r
+#define RESPONDER_ID_VALID_BIT_MASK 0x4\r
+#define TARGER_ID_VALID_BIT_MASK    0x8\r
+#define PRECISE_IP_VALID_BIT_MASK   0x10\r
+\r
+typedef struct {\r
+  UINT64  InfoValid : 1;\r
+  UINT64  ReqValid : 1;\r
+  UINT64  RespValid : 1;\r
+  UINT64  TargetValid : 1;\r
+  UINT64  IpValid : 1;\r
+  UINT64  Reserved : 59;\r
+  UINT64  Info;\r
+  UINT64  Req;\r
+  UINT64  Resp;\r
+  UINT64  Target;\r
+  UINT64  Ip;\r
+} MOD_ERROR_INFO;\r
+\r
+typedef struct {\r
+  UINT8 CpuidInfo[40];\r
+  UINT8 Reserved;\r
+} CPUID_INFO;\r
+\r
+typedef struct {\r
+  UINT64  FrLow;\r
+  UINT64  FrHigh;\r
+} FR_STRUCT;\r
+\r
+#define MIN_STATE_VALID_BIT_MASK  0x1\r
+#define BR_VALID_BIT_MASK         0x2\r
+#define CR_VALID_BIT_MASK         0x4\r
+#define AR_VALID_BIT_MASK         0x8\r
+#define RR_VALID_BIT_MASK         0x10\r
+#define FR_VALID_BIT_MASK         0x20\r
+\r
+typedef struct {\r
+  UINT64    ValidFieldBits;\r
+  UINT8     MinStateInfo[1024];\r
+  UINT64    Br[8];\r
+  UINT64    Cr[128];\r
+  UINT64    Ar[128];\r
+  UINT64    Rr[8];\r
+  FR_STRUCT Fr[128];\r
+} PSI_STATIC_STRUCT;\r
+\r
+#define PROC_ERROR_MAP_VALID_BIT_MASK       0x1\r
+#define PROC_STATE_PARAMETER_VALID_BIT_MASK 0x2\r
+#define PROC_CR_LID_VALID_BIT_MASK          0x4\r
+#define PROC_STATIC_STRUCT_VALID_BIT_MASK   0x8\r
+#define CPU_INFO_VALID_BIT_MASK             0x1000000\r
+\r
+typedef struct {\r
+  SAL_SEC_HEADER    SectionHeader;\r
+  UINT64            ValidationBits;\r
+  UINT64            ProcErrorMap;\r
+  UINT64            ProcStateParameter;\r
+  UINT64            ProcCrLid;\r
+  MOD_ERROR_INFO    CacheError[15];\r
+  MOD_ERROR_INFO    TlbError[15];\r
+  MOD_ERROR_INFO    BusError[15];\r
+  MOD_ERROR_INFO    RegFileCheck[15];\r
+  MOD_ERROR_INFO    MsCheck[15];\r
+  CPUID_INFO        CpuInfo;\r
+  PSI_STATIC_STRUCT PsiValidData;\r
+} SAL_PROCESSOR_ERROR_RECORD;\r
+\r
+//\r
+//  Sal Platform memory Error Record\r
+//\r
+#define SAL_MEMORY_ERROR_RECORD_INFO \\r
+  { \\r
+    0xe429faf2, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
+  }\r
+\r
+#define MEMORY_ERROR_STATUS_VALID_BIT_MASK                0x1\r
+#define MEMORY_PHYSICAL_ADDRESS_VALID_BIT_MASK            0x2\r
+#define MEMORY_ADDR_BIT_MASK                              0x4\r
+#define MEMORY_NODE_VALID_BIT_MASK                        0x8\r
+#define MEMORY_CARD_VALID_BIT_MASK                        0x10\r
+#define MEMORY_MODULE_VALID_BIT_MASK                      0x20\r
+#define MEMORY_BANK_VALID_BIT_MASK                        0x40\r
+#define MEMORY_DEVICE_VALID_BIT_MASK                      0x80\r
+#define MEMORY_ROW_VALID_BIT_MASK                         0x100\r
+#define MEMORY_COLUMN_VALID_BIT_MASK                      0x200\r
+#define MEMORY_BIT_POSITION_VALID_BIT_MASK                0x400\r
+#define MEMORY_PLATFORM_REQUESTOR_ID_VALID_BIT_MASK       0x800\r
+#define MEMORY_PLATFORM_RESPONDER_ID_VALID_BIT_MASK       0x1000\r
+#define MEMORY_PLATFORM_TARGET_VALID_BIT_MASK             0x2000\r
+#define MEMORY_PLATFORM_BUS_SPECIFIC_DATA_VALID_BIT_MASK  0x4000\r
+#define MEMORY_PLATFORM_OEM_ID_VALID_BIT_MASK             0x8000\r
+#define MEMORY_PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK    0x10000\r
+\r
+typedef struct {\r
+  SAL_SEC_HEADER  SectionHeader;\r
+  UINT64          ValidationBits;\r
+  UINT64          MemErrorStatus;\r
+  UINT64          MemPhysicalAddress;\r
+  UINT64          MemPhysicalAddressMask;\r
+  UINT16          MemNode;\r
+  UINT16          MemCard;\r
+  UINT16          MemModule;\r
+  UINT16          MemBank;\r
+  UINT16          MemDevice;\r
+  UINT16          MemRow;\r
+  UINT16          MemColumn;\r
+  UINT16          MemBitPosition;\r
+  UINT64          ModRequestorId;\r
+  UINT64          ModResponderId;\r
+  UINT64          ModTargetId;\r
+  UINT64          BusSpecificData;\r
+  UINT8           MemPlatformOemId[16];\r
+} SAL_MEMORY_ERROR_RECORD;\r
+\r
+//\r
+//  PCI BUS Errors\r
+//\r
+#define SAL_PCI_BUS_ERROR_RECORD_INFO \\r
+  { \\r
+    0xe429faf4, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
+  }\r
+\r
+#define PCI_BUS_ERROR_STATUS_VALID_BIT_MASK     0x1\r
+#define PCI_BUS_ERROR_TYPE_VALID_BIT_MASK       0x2\r
+#define PCI_BUS_ID_VALID_BIT_MASK               0x4\r
+#define PCI_BUS_ADDRESS_VALID_BIT_MASK          0x8\r
+#define PCI_BUS_DATA_VALID_BIT_MASK             0x10\r
+#define PCI_BUS_CMD_VALID_BIT_MASK              0x20\r
+#define PCI_BUS_REQUESTOR_ID_VALID_BIT_MASK     0x40\r
+#define PCI_BUS_RESPONDER_ID_VALID_BIT_MASK     0x80\r
+#define PCI_BUS_TARGET_VALID_BIT_MASK           0x100\r
+#define PCI_BUS_OEM_ID_VALID_BIT_MASK           0x200\r
+#define PCI_BUS_OEM_DATA_STRUCT_VALID_BIT_MASK  0x400\r
+\r
+typedef struct {\r
+  UINT8 BusNumber;\r
+  UINT8 SegmentNumber;\r
+} PCI_BUS_ID;\r
+\r
+typedef struct {\r
+  SAL_SEC_HEADER  SectionHeader;\r
+  UINT64          ValidationBits;\r
+  UINT64          PciBusErrorStatus;\r
+  UINT16          PciBusErrorType;\r
+  PCI_BUS_ID      PciBusId;\r
+  UINT32          Reserved;\r
+  UINT64          PciBusAddress;\r
+  UINT64          PciBusData;\r
+  UINT64          PciBusCommand;\r
+  UINT64          PciBusRequestorId;\r
+  UINT64          PciBusResponderId;\r
+  UINT64          PciBusTargetId;\r
+  UINT8           PciBusOemId[16];\r
+} SAL_PCI_BUS_ERROR_RECORD;\r
+\r
+//\r
+//  PCI Component Errors\r
+//\r
+#define SAL_PCI_COMP_ERROR_RECORD_INFO \\r
+  { \\r
+    0xe429faf6, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
+  }\r
+\r
+#define PCI_COMP_ERROR_STATUS_VALID_BIT_MASK    0x1\r
+#define PCI_COMP_INFO_VALID_BIT_MASK            0x2\r
+#define PCI_COMP_MEM_NUM_VALID_BIT_MASK         0x4\r
+#define PCI_COMP_IO_NUM_VALID_BIT_MASK          0x8\r
+#define PCI_COMP_REG_DATA_PAIR_VALID_BIT_MASK   0x10\r
+#define PCI_COMP_OEM_DATA_STRUCT_VALID_BIT_MASK 0x20\r
+\r
+typedef struct {\r
+  UINT16  VendorId;\r
+  UINT16  DeviceId;\r
+  UINT8   ClassCode[3];\r
+  UINT8   FunctionNumber;\r
+  UINT8   DeviceNumber;\r
+  UINT8   BusNumber;\r
+  UINT8   SegmentNumber;\r
+  UINT8   Reserved[5];\r
+} PCI_COMP_INFO;\r
+\r
+typedef struct {\r
+  SAL_SEC_HEADER  SectionHeader;\r
+  UINT64          ValidationBits;\r
+  UINT64          PciComponentErrorStatus;\r
+  PCI_COMP_INFO   PciComponentInfo;\r
+  UINT32          PciComponentMemNum;\r
+  UINT32          PciComponentIoNum;\r
+  UINT8           PciBusOemId[16];\r
+} SAL_PCI_COMPONENT_ERROR_RECORD;\r
+\r
+//\r
+//  Sal Device Errors Info.\r
+//\r
+#define SAL_DEVICE_ERROR_RECORD_INFO \\r
+  { \\r
+    0xe429faf3, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
+  }\r
+\r
+#define SEL_RECORD_ID_VALID_BIT_MASK      0x1;\r
+#define SEL_RECORD_TYPE_VALID_BIT_MASK    0x2;\r
+#define SEL_GENERATOR_ID_VALID_BIT_MASK   0x4;\r
+#define SEL_EVM_REV_VALID_BIT_MASK        0x8;\r
+#define SEL_SENSOR_TYPE_VALID_BIT_MASK    0x10;\r
+#define SEL_SENSOR_NUM_VALID_BIT_MASK     0x20;\r
+#define SEL_EVENT_DIR_TYPE_VALID_BIT_MASK 0x40;\r
+#define SEL_EVENT_DATA1_VALID_BIT_MASK    0x80;\r
+#define SEL_EVENT_DATA2_VALID_BIT_MASK    0x100;\r
+#define SEL_EVENT_DATA3_VALID_BIT_MASK    0x200;\r
+\r
+typedef struct {\r
+  SAL_SEC_HEADER  SectionHeader;\r
+  UINT64          ValidationBits;\r
+  UINT16          SelRecordId;\r
+  UINT8           SelRecordType;\r
+  UINT32          TimeStamp;\r
+  UINT16          GeneratorId;\r
+  UINT8           EvmRevision;\r
+  UINT8           SensorType;\r
+  UINT8           SensorNum;\r
+  UINT8           EventDirType;\r
+  UINT8           Data1;\r
+  UINT8           Data2;\r
+  UINT8           Data3;\r
+} SAL_DEVICE_ERROR_RECORD;\r
+\r
+//\r
+//  Sal SMBIOS Device Errors Info.\r
+//\r
+#define SAL_SMBIOS_ERROR_RECORD_INFO \\r
+  { \\r
+    0xe429faf5, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
+  }\r
+\r
+#define SMBIOS_EVENT_TYPE_VALID_BIT_MASK  0x1\r
+#define SMBIOS_LENGTH_VALID_BIT_MASK      0x2\r
+#define SMBIOS_TIME_STAMP_VALID_BIT_MASK  0x4\r
+#define SMBIOS_DATA_VALID_BIT_MASK        0x8\r
+\r
+typedef struct {\r
+  SAL_SEC_HEADER  SectionHeader;\r
+  UINT64          ValidationBits;\r
+  UINT8           SmbiosEventType;\r
+  UINT8           SmbiosLength;\r
+  UINT8           SmbiosBcdTimeStamp[6];\r
+} SAL_SMBIOS_DEVICE_ERROR_RECORD;\r
+\r
+//\r
+//  Sal Platform Specific Errors Info.\r
+//\r
+#define SAL_PLATFORM_ERROR_RECORD_INFO \\r
+  { \\r
+    0xe429faf7, 0x3cb7, 0x11d4, {0xbc, 0xa7, 0x0, 0x80, 0xc7, 0x3c, 0x88, 0x81 } \\r
+  }\r
+\r
+#define PLATFORM_ERROR_STATUS_VALID_BIT_MASK    0x1\r
+#define PLATFORM_REQUESTOR_ID_VALID_BIT_MASK    0x2\r
+#define PLATFORM_RESPONDER_ID_VALID_BIT_MASK    0x4\r
+#define PLATFORM_TARGET_VALID_BIT_MASK          0x8\r
+#define PLATFORM_SPECIFIC_DATA_VALID_BIT_MASK   0x10\r
+#define PLATFORM_OEM_ID_VALID_BIT_MASK          0x20\r
+#define PLATFORM_OEM_DATA_STRUCT_VALID_BIT_MASK 0x40\r
+#define PLATFORM_OEM_DEVICE_PATH_VALID_BIT_MASK 0x80\r
+\r
+typedef struct {\r
+  SAL_SEC_HEADER  SectionHeader;\r
+  UINT64          ValidationBits;\r
+  UINT64          PlatformErrorStatus;\r
+  UINT64          PlatformRequestorId;\r
+  UINT64          PlatformResponderId;\r
+  UINT64          PlatformTargetId;\r
+  UINT64          PlatformBusSpecificData;\r
+  UINT8           OemComponentId[16];\r
+} SAL_PLATFORM_SPECIFIC_ERROR_RECORD;\r
+\r
+//\r
+// Union of all the possible Sal Record Types\r
+//\r
+typedef union {\r
+  SAL_RECORD_HEADER                   *RecordHeader;\r
+  SAL_PROCESSOR_ERROR_RECORD          *SalProcessorRecord;\r
+  SAL_PCI_BUS_ERROR_RECORD            *SalPciBusRecord;\r
+  SAL_PCI_COMPONENT_ERROR_RECORD      *SalPciComponentRecord;\r
+  SAL_DEVICE_ERROR_RECORD             *ImpiRecord;\r
+  SAL_SMBIOS_DEVICE_ERROR_RECORD      *SmbiosRecord;\r
+  SAL_PLATFORM_SPECIFIC_ERROR_RECORD  *PlatformRecord;\r
+  SAL_MEMORY_ERROR_RECORD             *MemoryRecord;\r
+  UINT8                               *Raw;\r
+} SAL_ERROR_RECORDS_POINTERS;\r
+\r
+#pragma pack()\r
+\r
+#endif\r