--- /dev/null
+/** @file\r
+ MSR Definitions for Intel(R) Xeon(R) Processor D product Family.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-13.\r
+\r
+**/\r
+\r
+#ifndef __XEON_D_MSR_H__\r
+#define __XEON_D_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number Enable Control (R/W).\r
+\r
+ @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_PPIN_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);\r
+ AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LockOut (R/WO) See Table 35-21.\r
+ ///\r
+ UINT32 LockOut:1;\r
+ ///\r
+ /// [Bit 1] Enable_PPIN (R/W) See Table 35-21.\r
+ ///\r
+ UINT32 Enable_PPIN:1;\r
+ UINT32 Reserved1:30;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_PPIN_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Protected Processor Inventory Number (R/O). Protected Processor\r
+ Inventory Number (R/O) See Table 35-21.\r
+\r
+ @param ECX MSR_XEON_D_PPIN (0x0000004F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_PPIN 0x0000004F\r
+\r
+\r
+/**\r
+ Package. See http://biosbits.org.\r
+\r
+ @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 35-21.\r
+ ///\r
+ UINT32 MaximumNonTurboRatio:8;\r
+ UINT32 Reserved2:7;\r
+ ///\r
+ /// [Bit 23] Package. PPIN_CAP (R/O) See Table 35-21.\r
+ ///\r
+ UINT32 PPIN_CAP:1;\r
+ UINT32 Reserved3:4;\r
+ ///\r
+ /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
+ /// Table 35-21.\r
+ ///\r
+ UINT32 RatioLimit:1;\r
+ ///\r
+ /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
+ /// Table 35-21.\r
+ ///\r
+ UINT32 TDPLimit:1;\r
+ ///\r
+ /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 35-21.\r
+ ///\r
+ UINT32 TJOFFSET:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 35-21.\r
+ ///\r
+ UINT32 MaximumEfficiencyRatio:8;\r
+ UINT32 Reserved6:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_PLATFORM_INFO_REGISTER;\r
+\r
+\r
+/**\r
+ Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
+ specific C-state code names, unrelated to MWAIT extension C-state parameters\r
+ or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
+\r
+ @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);\r
+ AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
+ /// processor-specific C-state code name (consuming the least power) for\r
+ /// the package. The default is set as factory-configured package C-state\r
+ /// limit. The following C-state code name encodings are supported: 000b:\r
+ /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
+ /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
+ /// supported by the processor are available.\r
+ ///\r
+ UINT32 Limit:3;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
+ ///\r
+ UINT32 IO_MWAIT:1;\r
+ UINT32 Reserved2:4;\r
+ ///\r
+ /// [Bit 15] CFG Lock (R/WO).\r
+ ///\r
+ UINT32 CFGLock:1;\r
+ ///\r
+ /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
+ /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
+ ///\r
+ UINT32 CStateConversion:1;\r
+ UINT32 Reserved3:8;\r
+ ///\r
+ /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C3AutoDemotion:1;\r
+ ///\r
+ /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
+ ///\r
+ UINT32 C1AutoDemotion:1;\r
+ ///\r
+ /// [Bit 27] Enable C3 Undemotion (R/W).\r
+ ///\r
+ UINT32 C3Undemotion:1;\r
+ ///\r
+ /// [Bit 28] Enable C1 Undemotion (R/W).\r
+ ///\r
+ UINT32 C1Undemotion:1;\r
+ ///\r
+ /// [Bit 29] Package C State Demotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateDemotion:1;\r
+ ///\r
+ /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
+ ///\r
+ UINT32 CStateUndemotion:1;\r
+ UINT32 Reserved4:1;\r
+ UINT32 Reserved5:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Thread. Global Machine Check Capability (R/O).\r
+\r
+ @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Count.\r
+ ///\r
+ UINT32 Count:8;\r
+ ///\r
+ /// [Bit 8] MCG_CTL_P.\r
+ ///\r
+ UINT32 MCG_CTL_P:1;\r
+ ///\r
+ /// [Bit 9] MCG_EXT_P.\r
+ ///\r
+ UINT32 MCG_EXT_P:1;\r
+ ///\r
+ /// [Bit 10] MCP_CMCI_P.\r
+ ///\r
+ UINT32 MCP_CMCI_P:1;\r
+ ///\r
+ /// [Bit 11] MCG_TES_P.\r
+ ///\r
+ UINT32 MCG_TES_P:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 23:16] MCG_EXT_CNT.\r
+ ///\r
+ UINT32 MCG_EXT_CNT:8;\r
+ ///\r
+ /// [Bit 24] MCG_SER_P.\r
+ ///\r
+ UINT32 MCG_SER_P:1;\r
+ ///\r
+ /// [Bit 25] MCG_EM_P.\r
+ ///\r
+ UINT32 MCG_EM_P:1;\r
+ ///\r
+ /// [Bit 26] MCG_ELOG_P.\r
+ ///\r
+ UINT32 MCG_ELOG_P:1;\r
+ UINT32 Reserved2:5;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_MCG_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
+ Enhancement. Accessible only while in SMM.\r
+\r
+ @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);\r
+ AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:26;\r
+ ///\r
+ /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
+ /// SMM code access restriction is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 SMM_Code_Access_Chk:1;\r
+ ///\r
+ /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
+ /// SMM long flow indicator is supported and a host-space interface\r
+ /// available to SMM handler.\r
+ ///\r
+ UINT32 Long_Flow_Indication:1;\r
+ UINT32 Reserved3:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_SMM_MCA_CAP_REGISTER;\r
+\r
+\r
+/**\r
+ Package.\r
+\r
+ @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);\r
+ AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bits 23:16] Temperature Target (RO) See Table 35-21.\r
+ ///\r
+ UINT32 TemperatureTarget:8;\r
+ ///\r
+ /// [Bits 27:24] TCC Activation Offset (R/W) See Table 35-21.\r
+ ///\r
+ UINT32 TCCActivationOffset:4;\r
+ UINT32 Reserved2:4;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.\r
+ ///\r
+ UINT32 Maximum1C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.\r
+ ///\r
+ UINT32 Maximum2C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.\r
+ ///\r
+ UINT32 Maximum3C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.\r
+ ///\r
+ UINT32 Maximum4C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.\r
+ ///\r
+ UINT32 Maximum5C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.\r
+ ///\r
+ UINT32 Maximum6C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.\r
+ ///\r
+ UINT32 Maximum7C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.\r
+ ///\r
+ UINT32 Maximum8C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.\r
+ ///\r
+ UINT32 Maximum9C:8;\r
+ ///\r
+ /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.\r
+ ///\r
+ UINT32 Maximum10C:8;\r
+ ///\r
+ /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.\r
+ ///\r
+ UINT32 Maximum11C:8;\r
+ ///\r
+ /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.\r
+ ///\r
+ UINT32 Maximum12C:8;\r
+ ///\r
+ /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.\r
+ ///\r
+ UINT32 Maximum13C:8;\r
+ ///\r
+ /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.\r
+ ///\r
+ UINT32 Maximum14C:8;\r
+ ///\r
+ /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.\r
+ ///\r
+ UINT32 Maximum15C:8;\r
+ ///\r
+ /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.\r
+ ///\r
+ UINT32 Maximum16C:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
+\r
+ @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
+ ///\r
+ UINT32 PowerUnits:4;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bits 12:8] Package. Energy Status Units Energy related information\r
+ /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
+ /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
+ /// micro-joules).\r
+ ///\r
+ UINT32 EnergyStatusUnits:5;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
+ /// Interfaces.".\r
+ ///\r
+ UINT32 TimeUnits:4;\r
+ UINT32 Reserved3:12;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
+ Domain.".\r
+\r
+ @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);\r
+ AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
+\r
+\r
+/**\r
+ Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
+\r
+\r
+/**\r
+ Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
+ RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
+\r
+\r
+/**\r
+ Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
+\r
+ @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);\r
+ AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
+\r
+\r
+/**\r
+ Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
+ refers to processor core frequency).\r
+\r
+ @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);\r
+ AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
+ /// reduced below the operating system request due to assertion of\r
+ /// external PROCHOT.\r
+ ///\r
+ UINT32 PROCHOT_Status:1;\r
+ ///\r
+ /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
+ /// operating system request due to a thermal event.\r
+ ///\r
+ UINT32 ThermalStatus:1;\r
+ ///\r
+ /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to PBM limit.\r
+ ///\r
+ UINT32 PowerBudgetManagementStatus:1;\r
+ ///\r
+ /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
+ /// frequency is reduced below the operating system request due to PCS\r
+ /// limit.\r
+ ///\r
+ UINT32 PlatformConfigurationServicesStatus:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
+ /// When set, frequency is reduced below the operating system request\r
+ /// because the processor has detected that utilization is low.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlStatus:1;\r
+ ///\r
+ /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to a thermal alert from the\r
+ /// Voltage Regulator.\r
+ ///\r
+ UINT32 VRThermAlertStatus:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
+ /// reduced below the operating system request due to electrical design\r
+ /// point constraints (e.g. maximum electrical current consumption).\r
+ ///\r
+ UINT32 ElectricalDesignPointStatus:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
+ /// below the operating system request due to Multi-Core Turbo limits.\r
+ ///\r
+ UINT32 MultiCoreTurboStatus:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
+ /// below max non-turbo P1.\r
+ ///\r
+ UINT32 FrequencyP1Status:1;\r
+ ///\r
+ /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
+ /// set, frequency is reduced below max n-core turbo frequency.\r
+ ///\r
+ UINT32 TurboFrequencyLimitingStatus:1;\r
+ ///\r
+ /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
+ /// reduced below the operating system request.\r
+ ///\r
+ UINT32 FrequencyLimitingStatus:1;\r
+ ///\r
+ /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PROCHOT_Log:1;\r
+ ///\r
+ /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ThermalLog:1;\r
+ ///\r
+ /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PowerBudgetManagementLog:1;\r
+ ///\r
+ /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
+ /// the PCS Status bit has asserted since the log bit was last cleared.\r
+ /// This log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 PlatformConfigurationServicesLog:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
+ /// indicates that the AUBFC Status bit has asserted since the log bit was\r
+ /// last cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 AutonomousUtilizationBasedFrequencyControlLog:1;\r
+ ///\r
+ /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
+ /// Alert Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 VRThermAlertLog:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
+ /// Status bit has asserted since the log bit was last cleared. This log\r
+ /// bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 ElectricalDesignPointLog:1;\r
+ UINT32 Reserved7:1;\r
+ ///\r
+ /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
+ /// Turbo Status bit has asserted since the log bit was last cleared. This\r
+ /// log bit will remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 MultiCoreTurboLog:1;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
+ /// Frequency P1 Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CoreFrequencyP1Log:1;\r
+ ///\r
+ /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
+ /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
+ /// has asserted since the log bit was last cleared. This log bit will\r
+ /// remain set until cleared by software writing 0.\r
+ ///\r
+ UINT32 TurboFrequencyLimitingLog:1;\r
+ ///\r
+ /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
+ /// Frequency Limiting Status bit has asserted since the log bit was last\r
+ /// cleared. This log bit will remain set until cleared by software\r
+ /// writing 0.\r
+ ///\r
+ UINT32 CoreFrequencyLimitingLog:1;\r
+ UINT32 Reserved9:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
+ ECX=0):EBX.PQM[bit 12] = 1.\r
+\r
+ @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);\r
+ AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3\r
+ /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:\r
+ /// Local memory bandwidth monitoring All other encoding reserved.\r
+ ///\r
+ UINT32 EventID:8;\r
+ UINT32 Reserved1:24;\r
+ ///\r
+ /// [Bits 41:32] RMID (RW).\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved2:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;\r
+\r
+\r
+/**\r
+ THREAD. Resource Association Register (R/W).\r
+\r
+ @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);\r
+ AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 9:0] RMID.\r
+ ///\r
+ UINT32 RMID:10;\r
+ UINT32 Reserved1:22;\r
+ ///\r
+ /// [Bits 51:32] COS (R/W).\r
+ ///\r
+ UINT32 COS:20;\r
+ UINT32 Reserved2:12;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;\r
+\r
+\r
+/**\r
+ Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
+ ECX=1):EDX.COS_MAX[15:0] >= n.\r
+\r
+ @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);\r
+ AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
+#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
+/// @}\r
+\r
+/**\r
+ MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0\r
+ to #MSR_XEON_D_IA32_L3_QOS_MASK_15.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.\r
+ ///\r
+ UINT32 CBM:20;\r
+ UINT32 Reserved2:12;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
+ RW if MSR_PLATFORM_INFO.[28] = 1.\r
+\r
+ @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:32;\r
+ UINT32 Reserved2:31;\r
+ ///\r
+ /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
+ /// the processor uses override configuration specified in\r
+ /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
+ /// uses factory-set configuration (Default).\r
+ ///\r
+ UINT32 TurboRatioLimitConfigurationSemaphore:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ * Bank MC5 reports MC error from the Intel QPI 0 module.\r
+ * Bank MC6 reports MC error from the integrated I/O module.\r
+ * Bank MC7 reports MC error from the home agent HA 0.\r
+ * Bank MC8 reports MC error from the home agent HA 1.\r
+ * Banks MC9 through MC16 report MC error from each channel of the integrated\r
+ memory controllers.\r
+ * Bank MC17 reports MC error from the following pair of CBo/L3 Slices\r
+ (if the pair is present): CBo0, CBo3, CBo6, CBo9, CBo12, CBo15.\r
+ * Bank MC18 reports MC error from the following pair of CBo/L3 Slices\r
+ (if the pair is present): CBo1, CBo4, CBo7, CBo10, CBo13, CBo16.\r
+ * Bank MC19 reports MC error from the following pair of CBo/L3 Slices\r
+ (if the pair is present): CBo2, CBo5, CBo8, CBo11, CBo14, CBo17.\r
+ * Bank MC20 reports MC error from the Intel QPI 1 module.\r
+ * Bank MC21 reports MC error from the Intel QPI 2 module.\r
+\r
+ @param ECX MSR_XEON_D_MCi_CTL\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_MC5_CTL);\r
+ AsmWriteMsr64 (MSR_XEON_D_MC5_CTL, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_XEON_D_MC5_CTL 0x00000414\r
+#define MSR_XEON_D_MC6_CTL 0x00000418\r
+#define MSR_XEON_D_MC7_CTL 0x0000041C\r
+#define MSR_XEON_D_MC8_CTL 0x00000420\r
+#define MSR_XEON_D_MC9_CTL 0x00000424\r
+#define MSR_XEON_D_MC10_CTL 0x00000428\r
+#define MSR_XEON_D_MC11_CTL 0x0000042C\r
+#define MSR_XEON_D_MC12_CTL 0x00000430\r
+#define MSR_XEON_D_MC13_CTL 0x00000434\r
+#define MSR_XEON_D_MC14_CTL 0x00000438\r
+#define MSR_XEON_D_MC15_CTL 0x0000043C\r
+#define MSR_XEON_D_MC16_CTL 0x00000440\r
+#define MSR_XEON_D_MC17_CTL 0x00000444\r
+#define MSR_XEON_D_MC18_CTL 0x00000448\r
+#define MSR_XEON_D_MC19_CTL 0x0000044C\r
+#define MSR_XEON_D_MC20_CTL 0x00000450\r
+#define MSR_XEON_D_MC21_CTL 0x00000454\r
+/// @}\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ @param ECX MSR_XEON_D_MCi_STATUS\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_MC6_STATUS);\r
+ AsmWriteMsr64 (MSR_XEON_D_MC6_STATUS, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_XEON_D_MC5_STATUS 0x00000415\r
+#define MSR_XEON_D_MC6_STATUS 0x00000419\r
+#define MSR_XEON_D_MC7_STATUS 0x0000041D\r
+#define MSR_XEON_D_MC8_STATUS 0x00000421\r
+#define MSR_XEON_D_MC9_STATUS 0x00000425\r
+#define MSR_XEON_D_MC10_STATUS 0x00000429\r
+#define MSR_XEON_D_MC11_STATUS 0x0000042D\r
+#define MSR_XEON_D_MC12_STATUS 0x00000431\r
+#define MSR_XEON_D_MC13_STATUS 0x00000435\r
+#define MSR_XEON_D_MC14_STATUS 0x00000439\r
+#define MSR_XEON_D_MC15_STATUS 0x0000043D\r
+#define MSR_XEON_D_MC16_STATUS 0x00000441\r
+#define MSR_XEON_D_MC17_STATUS 0x00000445\r
+#define MSR_XEON_D_MC18_STATUS 0x00000449\r
+#define MSR_XEON_D_MC19_STATUS 0x0000044D\r
+#define MSR_XEON_D_MC20_STATUS 0x00000451\r
+#define MSR_XEON_D_MC21_STATUS 0x00000455\r
+/// @}\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ @param ECX MSR_XEON_D_MCi_ADDR\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_MC6_ADDR);\r
+ AsmWriteMsr64 (MSR_XEON_D_MC6_ADDR, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_XEON_D_MC5_ADDR 0x00000416\r
+#define MSR_XEON_D_MC6_ADDR 0x0000041A\r
+#define MSR_XEON_D_MC7_ADDR 0x0000041E\r
+#define MSR_XEON_D_MC8_ADDR 0x00000422\r
+#define MSR_XEON_D_MC9_ADDR 0x00000426\r
+#define MSR_XEON_D_MC10_ADDR 0x0000042A\r
+#define MSR_XEON_D_MC11_ADDR 0x0000042E\r
+#define MSR_XEON_D_MC12_ADDR 0x00000432\r
+#define MSR_XEON_D_MC13_ADDR 0x00000436\r
+#define MSR_XEON_D_MC14_ADDR 0x0000043A\r
+#define MSR_XEON_D_MC15_ADDR 0x0000043E\r
+#define MSR_XEON_D_MC16_ADDR 0x00000442\r
+#define MSR_XEON_D_MC17_ADDR 0x00000446\r
+#define MSR_XEON_D_MC18_ADDR 0x0000044A\r
+#define MSR_XEON_D_MC19_ADDR 0x0000044E\r
+#define MSR_XEON_D_MC20_ADDR 0x00000452\r
+#define MSR_XEON_D_MC21_ADDR 0x00000456\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. See Section 15.3.2.1, "IA32_MCi_CTL MSRs." through Section\r
+ 15.3.2.4, "IA32_MCi_MISC MSRs.".\r
+\r
+ @param ECX MSR_XEON_D_MCi_MISC\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_XEON_D_MC6_MISC);\r
+ AsmWriteMsr64 (MSR_XEON_D_MC6_MISC, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_XEON_D_MC5_MISC 0x00000417\r
+#define MSR_XEON_D_MC6_MISC 0x0000041B\r
+#define MSR_XEON_D_MC7_MISC 0x0000041F\r
+#define MSR_XEON_D_MC8_MISC 0x00000423\r
+#define MSR_XEON_D_MC9_MISC 0x00000427\r
+#define MSR_XEON_D_MC10_MISC 0x0000042B\r
+#define MSR_XEON_D_MC11_MISC 0x0000042F\r
+#define MSR_XEON_D_MC12_MISC 0x00000433\r
+#define MSR_XEON_D_MC13_MISC 0x00000437\r
+#define MSR_XEON_D_MC14_MISC 0x0000043B\r
+#define MSR_XEON_D_MC15_MISC 0x0000043F\r
+#define MSR_XEON_D_MC16_MISC 0x00000443\r
+#define MSR_XEON_D_MC17_MISC 0x00000447\r
+#define MSR_XEON_D_MC18_MISC 0x0000044B\r
+#define MSR_XEON_D_MC19_MISC 0x0000044F\r
+#define MSR_XEON_D_MC20_MISC 0x00000453\r
+#define MSR_XEON_D_MC21_MISC 0x00000457\r
+/// @}\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
+\r
+ @param ECX MSR_XEON_D_PKG_C8_RESIDENCY (0x00000630)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_D_PKG_C8_RESIDENCY, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_PKG_C8_RESIDENCY 0x00000630\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_PKG_C8_RESIDENCY\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Package C8 Residency Counter. (R/O) Value since last reset\r
+ /// that this package is in processor-specific C8 states. Count at the\r
+ /// same frequency as the TSC.\r
+ ///\r
+ UINT32 C8ResidencyCounter:32;\r
+ ///\r
+ /// [Bits 59:32] Package C8 Residency Counter. (R/O) Value since last\r
+ /// reset that this package is in processor-specific C8 states. Count at\r
+ /// the same frequency as the TSC.\r
+ ///\r
+ UINT32 C8ResidencyCounterHi:28;\r
+ UINT32 Reserved:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_PKG_C8_RESIDENCY_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
+\r
+ @param ECX MSR_XEON_D_PKG_C9_RESIDENCY (0x00000631)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_D_PKG_C9_RESIDENCY, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_PKG_C9_RESIDENCY 0x00000631\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_PKG_C9_RESIDENCY\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Package C9 Residency Counter. (R/O) Value since last reset\r
+ /// that this package is in processor-specific C9 states. Count at the\r
+ /// same frequency as the TSC.\r
+ ///\r
+ UINT32 C9ResidencyCounter:32;\r
+ ///\r
+ /// [Bits 59:32] Package C9 Residency Counter. (R/O) Value since last\r
+ /// reset that this package is in processor-specific C9 states. Count at\r
+ /// the same frequency as the TSC.\r
+ ///\r
+ UINT32 C9ResidencyCounterHi:28;\r
+ UINT32 Reserved:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_PKG_C9_RESIDENCY_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Note: C-state values are processor specific C-state code names,\r
+ unrelated to MWAIT extension C-state parameters or ACPI C-States.\r
+\r
+ @param ECX MSR_XEON_D_PKG_C10_RESIDENCY (0x00000632)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY);\r
+ AsmWriteMsr64 (MSR_XEON_D_PKG_C10_RESIDENCY, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_PKG_C10_RESIDENCY 0x00000632\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_PKG_C10_RESIDENCY\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 31:0] Package C10 Residency Counter. (R/O) Value since last\r
+ /// reset that this package is in processor-specific C10 states. Count at\r
+ /// the same frequency as the TSC.\r
+ ///\r
+ UINT32 C10ResidencyCounter:32;\r
+ ///\r
+ /// [Bits 59:32] Package C10 Residency Counter. (R/O) Value since last\r
+ /// reset that this package is in processor-specific C10 states. Count at\r
+ /// the same frequency as the TSC.\r
+ ///\r
+ UINT32 C10ResidencyCounterHi:28;\r
+ UINT32 Reserved:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_PKG_C10_RESIDENCY_REGISTER;\r
+\r
+\r
+/**\r
+ Package. Cache Allocation Technology Configuration (R/W).\r
+\r
+ @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);\r
+ AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.\r
+ ///\r
+ UINT32 CAT:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;\r
+\r
+#endif\r
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