MdeModulePkg/PiSmmIpl: fix non-executable SMM RAM

This patch fixes an issue introduced by commit

  5b91bf82c67b586b9588cbe4bbffa1588f6b5926

and

  0c9f2cb10b7ddec56a3440e77219fd3ab1725e5c

This issue will only happen if PcdDxeNxMemoryProtectionPolicy is
enabled for reserved memory, which will mark SMM RAM as NX (non-
executable) during DXE core initialization. SMM IPL driver will
unset the NX attribute for SMM RAM to allow loading and running
SMM core/drivers.

But above commit will fail the unset operation of the NX attribute
due to a fact that SMM RAM has zero cache attribute (MRC code always
sets 0 attribute to reserved memory), which will cause GCD internal
method ConverToCpuArchAttributes() to return 0 attribute, which is
taken as invalid CPU paging attribute and skip the calling of
gCpu->SetMemoryAttributes().

The solution is to make use of existing functionality in PiSmmIpl
to make sure one cache attribute is set for SMM RAM. For performance
consideration, PiSmmIpl will always try to set SMM RAM to write-back.
But there's a hole in the code which will fail the setting write-back
attribute because of no corresponding cache capabilities. This patch
will add necessary cache capabilities before setting corresponding
attributes.

Cc: Star Zeng <star.zeng@intel.com>
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Jian J Wang <jian.j.wang@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>

diff --git a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
index 94d671bd747d15c0d31f10d99e16ee277fabbd40..7732693198c7e09aca727b36ccf294c3f3a65935 100644 (file)
--- a/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
+++ b/MdeModulePkg/Core/PiSmmCore/PiSmmIpl.c
@@ -42,6 +42,14 @@
 \r
 #include "PiSmmCorePrivateData.h"\r
 \r
 \r
 #include "PiSmmCorePrivateData.h"\r
 \r

+#define SMRAM_CAPABILITIES  (EFI_MEMORY_WB | EFI_MEMORY_UC)\r
+\r
+#define MEMORY_CACHE_ATTRIBUTES (EFI_MEMORY_UC | EFI_MEMORY_WC | \\r
+                                 EFI_MEMORY_WT | EFI_MEMORY_WB | \\r
+                                 EFI_MEMORY_WP | EFI_MEMORY_UCE)\r
+\r
+#define MEMORY_PAGE_ATTRIBUTES  (EFI_MEMORY_XP | EFI_MEMORY_RP | EFI_MEMORY_RO)\r
+\r

 //\r
 // Function prototypes from produced protocols\r
 //\r
 //\r
 // Function prototypes from produced protocols\r
 //\r


@@ -1617,34 +1625,48 @@ SmmIplEntry (
 \r
     GetSmramCacheRange (mCurrentSmramRange, &mSmramCacheBase, &mSmramCacheSize);\r
     //\r
 \r
     GetSmramCacheRange (mCurrentSmramRange, &mSmramCacheBase, &mSmramCacheSize);\r
     //\r

+    // Make sure we can change the desired memory attributes.\r
+    //\r
+    Status = gDS->GetMemorySpaceDescriptor (\r
+                    mSmramCacheBase,\r
+                    &MemDesc\r
+                    );\r
+    ASSERT_EFI_ERROR (Status);\r
+    if ((MemDesc.Capabilities & SMRAM_CAPABILITIES) != SMRAM_CAPABILITIES) {\r
+      gDS->SetMemorySpaceCapabilities (\r
+             mSmramCacheBase,\r
+             mSmramCacheSize,\r
+             MemDesc.Capabilities | SMRAM_CAPABILITIES\r
+             );\r
+    }\r
+    //\r

     // If CPU AP is present, attempt to set SMRAM cacheability to WB and clear\r
     // If CPU AP is present, attempt to set SMRAM cacheability to WB and clear\r

-    // XP if it's set.\r
+    // all paging attributes.\r

     // Note that it is expected that cacheability of SMRAM has been set to WB if CPU AP\r
     // is not available here.\r
     //\r
     CpuArch = NULL;\r
     Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&CpuArch);\r
     if (!EFI_ERROR (Status)) {\r
     // Note that it is expected that cacheability of SMRAM has been set to WB if CPU AP\r
     // is not available here.\r
     //\r
     CpuArch = NULL;\r
     Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&CpuArch);\r
     if (!EFI_ERROR (Status)) {\r

-      Status = gDS->SetMemorySpaceAttributes(\r
-                      mSmramCacheBase, \r
+      MemDesc.Attributes &= ~(MEMORY_CACHE_ATTRIBUTES | MEMORY_PAGE_ATTRIBUTES);\r
+      MemDesc.Attributes |= EFI_MEMORY_WB;\r
+      Status = gDS->SetMemorySpaceAttributes (\r
+                      mSmramCacheBase,\r

                       mSmramCacheSize,\r
                       mSmramCacheSize,\r

-                      EFI_MEMORY_WB\r
+                      MemDesc.Attributes\r

                       );\r
       if (EFI_ERROR (Status)) {\r
         DEBUG ((DEBUG_WARN, "SMM IPL failed to set SMRAM window to EFI_MEMORY_WB\n"));\r
       }\r
 \r
                       );\r
       if (EFI_ERROR (Status)) {\r
         DEBUG ((DEBUG_WARN, "SMM IPL failed to set SMRAM window to EFI_MEMORY_WB\n"));\r
       }\r
 \r

-      Status = gDS->GetMemorySpaceDescriptor(\r
-                      mCurrentSmramRange->PhysicalStart,\r
-                      &MemDesc\r
-                      );\r
-      if (!EFI_ERROR (Status) && (MemDesc.Attributes & EFI_MEMORY_XP) != 0) {\r
-        gDS->SetMemorySpaceAttributes (\r
-               mCurrentSmramRange->PhysicalStart,\r
-               mCurrentSmramRange->PhysicalSize,\r
-               MemDesc.Attributes & (~EFI_MEMORY_XP)\r
+      DEBUG_CODE (\r
+        gDS->GetMemorySpaceDescriptor (\r
+               mSmramCacheBase,\r
+               &MemDesc\r

                );\r
                );\r

-      }\r
+        DEBUG ((DEBUG_INFO, "SMRAM attributes: %016lx\n", MemDesc.Attributes));\r
+        ASSERT ((MemDesc.Attributes & MEMORY_PAGE_ATTRIBUTES) == 0);\r
+      );\r

     }\r
     //\r
     // if Loading module at Fixed Address feature is enabled, save the SMRAM base to Load\r
     }\r
     //\r
     // if Loading module at Fixed Address feature is enabled, save the SMRAM base to Load\r