ArmPkg/Drivers/CpuDxe/CpuDxe.inf
ArmPkg/Drivers/CpuPei/CpuPei.inf
ArmPkg/Drivers/PL390Gic/PL390GicDxe.inf
- ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
- ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
+ ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
+ ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
+
ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/ArmGicLib.h>\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicSendSgiTo (\r
+ IN INTN GicDistributorBase,\r
+ IN INTN TargetListFilter,\r
+ IN INTN CPUTargetList\r
+ )\r
+{\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
+}\r
+\r
+UINT32\r
+EFIAPI\r
+ArmGicAcknowledgeSgiFrom (\r
+ IN INTN GicInterruptInterfaceBase,\r
+ IN INTN CoreId\r
+ )\r
+{\r
+ INTN InterruptId;\r
+\r
+ InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+\r
+ // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
+ if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
+ // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
+\r
+UINT32\r
+EFIAPI\r
+ArmGicAcknowledgeSgi2From (\r
+ IN INTN GicInterruptInterfaceBase,\r
+ IN INTN CoreId,\r
+ IN INTN SgiId\r
+ )\r
+{\r
+ INTN InterruptId;\r
+\r
+ InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
+\r
+ // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
+ if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
+ // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
+ return 1;\r
+ } else {\r
+ return 0;\r
+ }\r
+}\r
#include <Library/UefiLib.h>
#include <Library/PcdLib.h>
#include <Library/IoLib.h>
+#include <Library/ArmGicLib.h>
#include <Protocol/Cpu.h>
#include <Protocol/HardwareInterrupt.h>
-#include <Drivers/PL390Gic.h>
-
// number of 32-bit registers needed to represent those interrupts as a bit
// (used for enable set, enable clear, pending set, pending clear, and active regs)
-#define GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32)
+#define ARM_GIC_NUM_REG_PER_INT_BITS (PcdGet32(PcdGicNumInterrupts) / 32)
// number of 32-bit registers needed to represent those interrupts as two bits
// (used for configuration reg)
-#define GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16)
+#define ARM_GIC_NUM_REG_PER_INT_CFG (PcdGet32(PcdGicNumInterrupts) / 16)
// number of 32-bit registers needed to represent interrupts as 8-bit priority field
// (used for priority regs)
-#define GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4)
+#define ARM_GIC_NUM_REG_PER_INT_BYTES (PcdGet32(PcdGicNumInterrupts) / 4)
-#define GIC_DEFAULT_PRIORITY 0x80
+#define ARM_GIC_DEFAULT_PRIORITY 0x80
extern EFI_HARDWARE_INTERRUPT_PROTOCOL gHardwareInterruptProtocol;
RegShift = Source % 32;
// write set-enable register
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset), 1 << RegShift);
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS;
}
RegShift = Source % 32;
// Write set-enable register
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDICER + (4*RegOffset), 1 << RegShift);
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDICER + (4*RegOffset), 1 << RegShift);
return EFI_SUCCESS;
}
RegOffset = Source / 32;
RegShift = Source % 32;
- if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
+ if ((MmioRead32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDISER + (4*RegOffset)) & (1<<RegShift)) == 0) {
*InterruptState = FALSE;
} else {
*InterruptState = TRUE;
return EFI_UNSUPPORTED;
}
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, Source);
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, Source);
return EFI_SUCCESS;
}
UINT32 GicInterrupt;
HARDWARE_INTERRUPT_HANDLER InterruptHandler;
- GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCIAR);
+ GicInterrupt = MmioRead32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCIAR);
+ //TODO: Comment me
if (GicInterrupt >= PcdGet32(PcdGicNumInterrupts)) {
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCEIOR, GicInterrupt);
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCEIOR, GicInterrupt);
return;
}
}
// Disable Gic Interface
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x0);
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0x0);
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x0);
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0x0);
// Disable Gic Distributor
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x0);
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x0);
}
/**
RegOffset = Index / 4;
RegShift = (Index % 4) * 8;
MmioAndThenOr32 (
- PcdGet32(PcdGicDistributorBase) + GIC_ICDIPR + (4*RegOffset),
+ PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPR + (4*RegOffset),
~(0xff << RegShift),
- GIC_DEFAULT_PRIORITY << RegShift
+ ARM_GIC_DEFAULT_PRIORITY << RegShift
);
}
// Configure interrupts for cpu 0
- for (Index = 0; Index < GIC_NUM_REG_PER_INT_BYTES; Index++) {
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDIPTR + (Index*4), 0x01010101);
+ for (Index = 0; Index < ARM_GIC_NUM_REG_PER_INT_BYTES; Index++) {
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDIPTR + (Index*4), 0x01010101);
}
// Set binary point reg to 0x7 (no preemption)
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCBPR, 0x7);
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCBPR, 0x7);
// Set priority mask reg to 0xff to allow all priorities through
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCPMR, 0xff);
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCPMR, 0xff);
// Enable gic cpu interface
- MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + GIC_ICCICR, 0x1);
+ MmioWrite32 (PcdGet32(PcdGicInterruptInterfaceBase) + ARM_GIC_ICCICR, 0x1);
// Enable gic distributor
- MmioWrite32 (PcdGet32(PcdGicDistributorBase) + GIC_ICDDCR, 0x1);
+ MmioWrite32 (PcdGet32(PcdGicDistributorBase) + ARM_GIC_ICDDCR, 0x1);
ZeroMem (&gRegisteredInterruptHandlers, sizeof (gRegisteredInterruptHandlers));
[Sources.common]
PL390GicDxe.c
-
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
UefiDriverEntryPoint
IoLib
-[Guids]
-
-
[Protocols]
gHardwareInterruptProtocolGuid
gEfiCpuArchProtocolGuid
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL390GicLib\r
+ FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmGicLib\r
+\r
+[Sources]\r
+ PL390Gic.c\r
+ PL390GicNonSec.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ MdePkg/MdePkg.dec\r
\r
#include <Uefi.h>\r
#include <Library/IoLib.h>\r
-#include <Drivers/PL390Gic.h>\r
+#include <Library/ArmGicLib.h>\r
\r
\r
VOID\r
EFIAPI\r
-PL390GicEnableInterruptInterface (\r
+ArmGicEnableInterruptInterface (\r
IN INTN GicInterruptInterfaceBase\r
)\r
{ \r
* Enable the CPU interface in Non-Secure world\r
* Note: The ICCICR register is banked when Security extensions are implemented\r
*/\r
- MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCICR,0x00000001);\r
+ MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,0x00000001);\r
}\r
\r
VOID\r
EFIAPI\r
-PL390GicEnableDistributor (\r
+ArmGicEnableDistributor (\r
IN INTN GicDistributorBase\r
)\r
{\r
* Enable GIC distributor in Non-Secure world.\r
* Note: The ICDDCR register is banked when Security extensions are implemented\r
*/\r
- MmioWrite32 (GicDistributorBase + GIC_ICDDCR, 0x00000001);\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-PL390GicSendSgiTo (\r
- IN INTN GicDistributorBase,\r
- IN INTN TargetListFilter,\r
- IN INTN CPUTargetList\r
- )\r
-{\r
- MmioWrite32 (GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
-}\r
-\r
-UINT32\r
-EFIAPI\r
-PL390GicAcknowledgeSgiFrom (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId\r
- )\r
-{\r
- INTN InterruptId;\r
-\r
- InterruptId = MmioRead32 (GicInterruptInterfaceBase + GIC_ICCIAR);\r
-\r
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
- MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
- return 1;\r
- } else {\r
- return 0;\r
- }\r
-}\r
-\r
-UINT32\r
-EFIAPI\r
-PL390GicAcknowledgeSgi2From (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId,\r
- IN INTN SgiId\r
- )\r
-{\r
- INTN InterruptId;\r
-\r
- InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
-\r
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
- MmioWrite32 (GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
- return 1;\r
- } else {\r
- return 0;\r
- }\r
+ MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x00000001);\r
}\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL390GicNonSec\r
- FILE_GUID = 03d05ee4-cdeb-458c-9dfc-993f09bdf405\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PL390GicNonSecLib\r
-\r
-[Sources]\r
- PL390GicNonSec.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[FixedPcd]\r
\r
#include <Uefi.h>\r
#include <Library/IoLib.h>\r
-#include <Drivers/PL390Gic.h>\r
+#include <Library/ArmGicLib.h>\r
\r
/*\r
* This function configures the all interrupts to be Non-secure.\r
*/\r
VOID\r
EFIAPI\r
-PL390GicSetupNonSecure (\r
+ArmGicSetupNonSecure (\r
IN INTN GicDistributorBase,\r
IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + GIC_ICCPMR);\r
+ UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);\r
\r
// Set priority Mask so that no interrupts get through to CPU\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0);\r
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);\r
\r
// Check if there are any pending interrupts\r
- while(0 != (MmioRead32(GicDistributorBase + GIC_ICDICPR) & 0xF)) {\r
+ //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.\r
+ while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {\r
// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal\r
- UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
+ UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);\r
\r
// Write to End of interrupt signal\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);\r
}\r
\r
// Ensure all GIC interrupts are Non-Secure\r
- MmioWrite32(GicDistributorBase + GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
- MmioWrite32(GicDistributorBase + GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
- MmioWrite32(GicDistributorBase + GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
+ MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]\r
+ MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt\r
+ MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)\r
\r
// Ensure all interrupts can get through the priority mask\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, CachedPriorityMask);\r
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);\r
}\r
\r
VOID\r
EFIAPI\r
-PL390GicEnableInterruptInterface (\r
+ArmGicEnableInterruptInterface (\r
IN INTN GicInterruptInterfaceBase\r
)\r
{\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */\r
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */\r
\r
/*\r
* Enable CPU interface in Secure world\r
* Enable CPU inteface in Non-secure World\r
* Signal Secure Interrupts to CPU using FIQ line *\r
*/\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCICR,\r
- GIC_ICCICR_ENABLE_SECURE(1) |\r
- GIC_ICCICR_ENABLE_NS(1) |\r
- GIC_ICCICR_ACK_CTL(0) |\r
- GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(1) |\r
- GIC_ICCICR_USE_SBPR(0));\r
+ MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,\r
+ ARM_GIC_ICCICR_ENABLE_SECURE |\r
+ ARM_GIC_ICCICR_ENABLE_NS |\r
+ ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);\r
}\r
\r
VOID\r
EFIAPI\r
-PL390GicEnableDistributor (\r
+ArmGicEnableDistributor (\r
IN INTN GicDistributorBase\r
)\r
{\r
- MmioWrite32(GicDistributorBase + GIC_ICDDCR, 1); // turn on the GIC distributor\r
-}\r
-\r
-VOID\r
-EFIAPI\r
-PL390GicSendSgiTo (\r
- IN INTN GicDistributorBase,\r
- IN INTN TargetListFilter,\r
- IN INTN CPUTargetList\r
- )\r
-{\r
- MmioWrite32(GicDistributorBase + GIC_ICDSGIR, ((TargetListFilter & 0x3) << 24) | ((CPUTargetList & 0xFF) << 16));\r
-}\r
-\r
-UINT32\r
-EFIAPI\r
-PL390GicAcknowledgeSgiFrom (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId\r
- )\r
-{\r
- INTN InterruptId;\r
-\r
- InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
-\r
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
- if (((CoreId & 0x7) << 10) == (InterruptId & 0x1C00)) {\r
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
- return 1;\r
- } else {\r
- return 0;\r
- }\r
-}\r
-\r
-UINT32\r
-EFIAPI\r
-PL390GicAcknowledgeSgi2From (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId,\r
- IN INTN SgiId\r
- )\r
-{\r
- INTN InterruptId;\r
-\r
- InterruptId = MmioRead32(GicInterruptInterfaceBase + GIC_ICCIAR);\r
-\r
- // Check if the Interrupt ID is valid, The read from Interrupt Ack register returns CPU ID and Interrupt ID\r
- if((((CoreId & 0x7) << 10) | (SgiId & 0x3FF)) == (InterruptId & 0x1FFF)) {\r
- // Got SGI number 0 hence signal End of Interrupt by writing to ICCEOIR\r
- MmioWrite32(GicInterruptInterfaceBase + GIC_ICCEIOR, InterruptId);\r
- return 1;\r
- } else {\r
- return 0;\r
- }\r
+ MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1); // turn on the GIC distributor\r
}\r
+++ /dev/null
-#/* @file\r
-# Copyright (c) 2011, ARM Limited. All rights reserved.\r
-# \r
-# This program and the accompanying materials \r
-# are licensed and made available under the terms and conditions of the BSD License \r
-# which accompanies this distribution. The full text of the license may be found at \r
-# http://opensource.org/licenses/bsd-license.php \r
-#\r
-# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-#\r
-#*/\r
-\r
-[Defines]\r
- INF_VERSION = 0x00010005\r
- BASE_NAME = PL390GicSec\r
- FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b\r
- MODULE_TYPE = SEC\r
- VERSION_STRING = 1.0\r
- LIBRARY_CLASS = PL390GicSecLib\r
-\r
-[Sources]\r
- PL390GicSec.c\r
-\r
-[Packages]\r
- ArmPkg/ArmPkg.dec\r
- MdePkg/MdePkg.dec\r
-\r
-[FixedPcd]\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL390GicSecLib\r
+ FILE_GUID = 85f3cf80-b5f4-11df-9855-0002a5d5c51b\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = ArmGicSecLib\r
+\r
+[Sources]\r
+ PL390Gic.c\r
+ PL390GicSec.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ MdePkg/MdePkg.dec\r
+++ /dev/null
-/** @file\r
-*\r
-* Copyright (c) 2011, ARM Limited. All rights reserved.\r
-* \r
-* This program and the accompanying materials \r
-* are licensed and made available under the terms and conditions of the BSD License \r
-* which accompanies this distribution. The full text of the license may be found at \r
-* http://opensource.org/licenses/bsd-license.php \r
-*\r
-* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
-* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
-*\r
-**/\r
-\r
-#ifndef __PL390GIC_H\r
-#define __PL390GIC_H\r
-\r
-//\r
-// GIC definitions\r
-//\r
-\r
-// Distributor\r
-#define GIC_ICDDCR 0x000 // Distributor Control Register\r
-#define GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
-#define GIC_ICDIIDR 0x008 // Implementer Identification Register\r
-\r
-// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BITS (see GIC spec)\r
-#define GIC_ICDISR 0x080 // Interrupt Security Registers\r
-#define GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
-#define GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
-#define GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
-#define GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
-#define GIC_ICDABR 0x300 // Active Bit Registers\r
-\r
-// each reg base below repeats for VE_NUM_GIC_REG_PER_INT_BYTES\r
-#define GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
-\r
-// each reg base below repeats for VE_NUM_GIC_INTERRUPTS\r
-#define GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
-#define GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
-\r
-// just one of these\r
-#define GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
-\r
-// Cpu interface\r
-#define GIC_ICCICR 0x00 // CPU Interface Control Register\r
-#define GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
-#define GIC_ICCBPR 0x08 // Binary Point Register\r
-#define GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
-#define GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
-#define GIC_ICCRPR 0x14 // Running Priority Register\r
-#define GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
-#define GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
-#define GIC_ICCIDR 0xFC // Identification Register\r
-\r
-#define GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
-#define GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
-#define GIC_ICDSGIR_FILTER_ITSELF 0x2\r
-\r
-//Bit-masks to configure the CPU Interface Control register\r
-#define GIC_ICCICR_ENABLE_SECURE(a) ((a << 0) & 0x01)\r
-#define GIC_ICCICR_ENABLE_NS(a) ((a << 1) & 0x02)\r
-#define GIC_ICCICR_ACK_CTL(a) ((a << 2) & 0x04)\r
-#define GIC_ICCICR_SIGNAL_SECURE_TO_FIQ(a)((a << 3) & 0x08)\r
-#define GIC_ICCICR_USE_SBPR(a) ((a << 4) & 0x10)\r
-\r
-\r
-//\r
-// GIC SEC interfaces\r
-//\r
-VOID\r
-EFIAPI\r
-PL390GicSetupNonSecure (\r
- IN INTN GicDistributorBase,\r
- IN INTN GicInterruptInterfaceBase\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-PL390GicEnableInterruptInterface (\r
- IN INTN GicInterruptInterfaceBase\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-PL390GicEnableDistributor (\r
- IN INTN GicDistributorBase\r
- );\r
-\r
-VOID\r
-EFIAPI\r
-PL390GicSendSgiTo (\r
- IN INTN GicDistributorBase,\r
- IN INTN TargetListFilter,\r
- IN INTN CPUTargetList\r
- );\r
-\r
-UINT32\r
-EFIAPI\r
-PL390GicAcknowledgeSgiFrom (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId\r
- );\r
-\r
-UINT32\r
-EFIAPI\r
-PL390GicAcknowledgeSgi2From (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN CoreId,\r
- IN INTN SgiId\r
- );\r
-\r
-UINTN\r
-EFIAPI\r
-PL390GicSetPriorityMask (\r
- IN INTN GicInterruptInterfaceBase,\r
- IN INTN PriorityMask\r
- );\r
-\r
-#endif\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#ifndef __PL390GIC_H\r
+#define __PL390GIC_H\r
+\r
+//\r
+// GIC definitions\r
+//\r
+\r
+//\r
+// GIC Distributor\r
+//\r
+#define ARM_GIC_ICDDCR 0x000 // Distributor Control Register\r
+#define ARM_GIC_ICDICTR 0x004 // Interrupt Controller Type Register\r
+#define ARM_GIC_ICDIIDR 0x008 // Implementer Identification Register\r
+\r
+// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BITS (see GIC spec)\r
+#define ARM_GIC_ICDISR 0x080 // Interrupt Security Registers\r
+#define ARM_GIC_ICDISER 0x100 // Interrupt Set-Enable Registers\r
+#define ARM_GIC_ICDICER 0x180 // Interrupt Clear-Enable Registers\r
+#define ARM_GIC_ICDSPR 0x200 // Interrupt Set-Pending Registers\r
+#define ARM_GIC_ICDICPR 0x280 // Interrupt Clear-Pending Registers\r
+#define ARM_GIC_ICDABR 0x300 // Active Bit Registers\r
+\r
+// Each reg base below repeats for VE_NUM_ARM_GIC_REG_PER_INT_BYTES\r
+#define ARM_GIC_ICDIPR 0x400 // Interrupt Priority Registers\r
+\r
+// Each reg base below repeats for VE_NUM_ARM_GIC_INTERRUPTS\r
+#define ARM_GIC_ICDIPTR 0x800 // Interrupt Processor Target Registers\r
+#define ARM_GIC_ICDICFR 0xC00 // Interrupt Configuration Registers\r
+\r
+#define ARM_GIC_ICDPPISR 0xD00 // PPI Status register\r
+\r
+// just one of these\r
+#define ARM_GIC_ICDSGIR 0xF00 // Software Generated Interrupt Register\r
+\r
+//\r
+// GIC Cpu interface\r
+//\r
+#define ARM_GIC_ICCICR 0x00 // CPU Interface Control Register\r
+#define ARM_GIC_ICCPMR 0x04 // Interrupt Priority Mask Register\r
+#define ARM_GIC_ICCBPR 0x08 // Binary Point Register\r
+#define ARM_GIC_ICCIAR 0x0C // Interrupt Acknowledge Register\r
+#define ARM_GIC_ICCEIOR 0x10 // End Of Interrupt Register\r
+#define ARM_GIC_ICCRPR 0x14 // Running Priority Register\r
+#define ARM_GIC_ICCPIR 0x18 // Highest Pending Interrupt Register\r
+#define ARM_GIC_ICCABPR 0x1C // Aliased Binary Point Register\r
+#define ARM_GIC_ICCIDR 0xFC // Identification Register\r
+\r
+#define ARM_GIC_ICDSGIR_FILTER_TARGETLIST 0x0\r
+#define ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE 0x1\r
+#define ARM_GIC_ICDSGIR_FILTER_ITSELF 0x2\r
+\r
+// Bit-masks to configure the CPU Interface Control register\r
+#define ARM_GIC_ICCICR_ENABLE_SECURE 0x01\r
+#define ARM_GIC_ICCICR_ENABLE_NS 0x02\r
+#define ARM_GIC_ICCICR_ACK_CTL 0x04\r
+#define ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ 0x08\r
+#define ARM_GIC_ICCICR_USE_SBPR 0x10\r
+\r
+\r
+//\r
+// GIC SEC interfaces\r
+//\r
+VOID\r
+EFIAPI\r
+ArmGicSetupNonSecure (\r
+ IN INTN GicDistributorBase,\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableInterruptInterface (\r
+ IN INTN GicInterruptInterfaceBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicEnableDistributor (\r
+ IN INTN GicDistributorBase\r
+ );\r
+\r
+VOID\r
+EFIAPI\r
+ArmGicSendSgiTo (\r
+ IN INTN GicDistributorBase,\r
+ IN INTN TargetListFilter,\r
+ IN INTN CPUTargetList\r
+ );\r
+\r
+UINT32\r
+EFIAPI\r
+ArmGicAcknowledgeSgiFrom (\r
+ IN INTN GicInterruptInterfaceBase,\r
+ IN INTN CoreId\r
+ );\r
+\r
+UINT32\r
+EFIAPI\r
+ArmGicAcknowledgeSgi2From (\r
+ IN INTN GicInterruptInterfaceBase,\r
+ IN INTN CoreId,\r
+ IN INTN SgiId\r
+ );\r
+\r
+UINTN\r
+EFIAPI\r
+ArmGicSetPriorityMask (\r
+ IN INTN GicInterruptInterfaceBase,\r
+ IN INTN PriorityMask\r
+ );\r
+\r
+#endif\r
# L2 Cache Driver\r
L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf\r
# ARM PL390 General Interrupt Driver in Secure and Non-secure\r
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf\r
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf\r
\r
!if $(EDK2_SKIP_PEICORE) == 1\r
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf\r
!if $(EDK2_SKIP_PEICORE) == 1\r
ArmPlatformPkg/PrePi/PeiUniCore.inf {\r
<LibraryClasses>\r
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf\r
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf\r
}\r
!else\r
ArmPlatformPkg/PrePeiCore/PrePeiCoreUniCore.inf {\r
<LibraryClasses>\r
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf\r
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
}\r
MdeModulePkg/Core/Pei/PeiMain.inf\r
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
# ARM PL011 UART Driver\r
PL011UartLib|ArmPlatformPkg/Drivers/PL011Uart/PL011Uart.inf\r
# ARM PL390 General Interrupt Driver in Secure and Non-secure\r
- PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf\r
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf\r
+ ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
\r
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf\r
\r
\r
# L2 Cache Driver\r
L2X0CacheLib|ArmPlatformPkg/Library/L2X0CacheLibNull/L2X0CacheLibNull.inf\r
- # ARM PL390 General Interrupt Driver in Secure\r
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf\r
\r
!if $(EDK2_SKIP_PEICORE) == 1\r
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf\r
!if $(EDK2_SKIP_PEICORE) == 1\r
ArmPlatformPkg/PrePi/PeiMPCore.inf {\r
<LibraryClasses>\r
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf\r
ArmPlatformLib|ArmPlatformPkg/ArmRealViewEbPkg/Library/ArmRealViewEbLibRTSM/ArmRealViewEbLib.inf\r
}\r
!else\r
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {\r
<LibraryClasses>\r
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf\r
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf\r
}\r
MdeModulePkg/Core/Pei/PeiMain.inf\r
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {\r
#DebugAgentLib|EmbeddedPkg/Library/GdbDebugAgent/GdbDebugAgent.inf
# ARM PL390 General Interrupt Driver in Secure and Non-secure
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSec.inf
- PL390GicNonSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicSecLib.inf
+ ArmGicLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
!if $(EDK2_SKIP_PEICORE) == 1
PrePiLib|EmbeddedPkg/Library/PrePiLib/PrePiLib.inf
!if $(EDK2_SKIP_PEICORE) == 1
ArmPlatformPkg/PrePi/PeiMPCore.inf {
<LibraryClasses>
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7MPCoreLib.inf
ArmPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressLibCTA9x4/ArmVExpressLib.inf
}
!else
ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf {
<LibraryClasses>
- PL390GicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicNonSec.inf
+ ArmGicSecLib|ArmPkg/Drivers/PL390Gic/PL390GicLib.inf
}
MdeModulePkg/Core/Pei/PeiMain.inf
MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
\r
#include <PiPei.h>\r
\r
+#include <Library/ArmGicLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PrintLib.h>\r
#include <Library/SerialPortLib.h>\r
#include <Chipset/ArmV7.h>
-#include <Drivers/PL390Gic.h>\r
\r
#define ARM_PRIMARY_CORE 0\r
\r
ArmCallWFI();\r
\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);\r
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);\r
\r
// Jump to secondary core entry point.\r
secondary_start ();\r
} else if (FeaturePcdGet (PcdSystemMemoryInitializeInSec)) {\r
if (CoreId == ARM_PRIMARY_CORE) {\r
// Signal the secondary cores they can jump to PEI phase\r
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
\r
// To enter into Non Secure state, we need to make a return from exception\r
*JumpAddress = PcdGet32(PcdNormalFvBaseAddress);\r
[LibraryClasses]
DebugLib
PcdLib
- PL390GicSecLib
+ ArmGicSecLib
PrintLib
SerialPortLib
*\r
**/\r
\r
+#include <Library/ArmGicLib.h>\r
#include <Library/ArmMPCoreMailBoxLib.h>\r
#include <Chipset/ArmV7.h>\r
-#include <Drivers/PL390Gic.h>\r
\r
#include "PrePeiCore.h"\r
\r
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
ArmCallWFI();\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+ ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
}\r
\r
secondary_start = (VOID (*)())secondary_entry_addr;\r
{\r
EFI_SEC_PEI_HAND_OFF SecCoreData;\r
\r
- //Enable the GIC Distributor\r
- PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+ // Enable the GIC Distributor\r
+ ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
\r
// If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
- if (FeaturePcdGet(PcdSendSgiToBringUpSecondaryCores)) {\r
+ if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r
// Sending SGI to all the Secondary CPU interfaces\r
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
}\r
\r
//\r
DebugLib\r
DebugAgentLib\r
IoLib\r
- PL390GicNonSecLib\r
+ ArmGicLib\r
PrintLib\r
SerialPortLib\r
\r
\r
#include "PrePi.h"\r
\r
+#include <Library/ArmGicLib.h>\r
#include <Library/ArmMPCoreMailBoxLib.h>\r
#include <Chipset/ArmV7.h>\r
-#include <Drivers/PL390Gic.h>\r
\r
VOID\r
PrimaryMain (\r
IN UINT64 StartTimeStamp\r
)\r
{\r
- //Enable the GIC Distributor\r
- PL390GicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
+ // Enable the GIC Distributor\r
+ ArmGicEnableDistributor(PcdGet32(PcdGicDistributorBase));\r
\r
// In some cases, the secondary cores are waiting for an SGI from the next stage boot loader toresume their initialization\r
if (!FixedPcdGet32(PcdSendSgiToBringUpSecondaryCores)) {\r
// Sending SGI to all the Secondary CPU interfaces\r
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);\r
}\r
\r
PrePiMain (UefiMemoryBase, StartTimeStamp);\r
while (secondary_entry_addr = ArmGetMPCoreMailbox(), secondary_entry_addr == 0) {\r
ArmCallWFI();\r
// Acknowledge the interrupt and send End of Interrupt signal.\r
- PL390GicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
+ ArmGicAcknowledgeSgiFrom(PcdGet32(PcdGicInterruptInterfaceBase),0/*CoreId*/);\r
}\r
\r
secondary_start = (VOID (*)())secondary_entry_addr;\r
DebugAgentLib\r
ArmLib\r
ArmMPCoreMailBoxLib\r
- PL390GicNonSecLib\r
+ ArmGicLib\r
IoLib\r
TimerLib\r
SerialPortLib\r
#include <Library/ArmPlatformLib.h>
#include <Chipset/ArmV7.h>
-#include <Drivers/PL390Gic.h>
+#include <Library/ArmGicLib.h>
#define ARM_PRIMARY_CORE 0
// 3: As all the cores are in secure state, use secure SGI's
//
- PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
- PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Send SGI to all Secondary core to wake them up from WFI state.
- PL390GicSendSgiTo (PcdGet32(PcdGicDistributorBase), GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
+ ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E);
} else {
// The secondary cores need to wait until the Trustzone chipsets configuration is done
// before switching to Non Secure World
// Enabled GIC CPU Interface
- PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// Waiting for the SGI from the primary core
ArmCallWFI();
// Acknowledge the interrupt and send End of Interrupt signal.
- PL390GicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), ARM_PRIMARY_CORE);
+ ArmGicAcknowledgeSgiFrom (PcdGet32(PcdGicInterruptInterfaceBase), PRIMARY_CORE_ID);
}
// Transfer the interrupt to Non-secure World
- PL390GicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicSetupNonSecure (PcdGet32(PcdGicDistributorBase),PcdGet32(PcdGicInterruptInterfaceBase));
// Write to CP15 Non-secure Access Control Register :
// - Enable CP10 and CP11 accesses in NS World
// Trustzone is not enabled, just enable the Distributor and CPU interface
if (CoreId == ARM_PRIMARY_CORE) {
- PL390GicEnableDistributor (PcdGet32(PcdGicDistributorBase));
+ ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));
}
- PL390GicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
+ ArmGicEnableInterruptInterface (PcdGet32(PcdGicInterruptInterfaceBase));
// With Trustzone support the transition from Sec to Normal world is done by return_from_exception().
// If we want to keep this function call we need to ensure the SVC's SPSR point to the same Program
DebugLib
DebugAgentLib
IoLib
- PL390GicSecLib
+ ArmGicSecLib
PrintLib
SerialPortLib
projects / mirror_edk2.git / commitdiff