UINT32 Length;\r
} EFI_ACPI_COMMON_HEADER;\r
\r
-//\r
-// Common ACPI description table header. This structure prefaces most ACPI tables.\r
-//\r
-#pragma pack(1)\r
-\r
+///\r
+/// Common ACPI description table header. This structure prefaces most ACPI tables.\r
+///\r
typedef struct {\r
UINT32 Signature;\r
UINT32 Length;\r
UINT32 CreatorRevision;\r
} EFI_ACPI_DESCRIPTION_HEADER;\r
\r
-#pragma pack()\r
//\r
// Define for Desriptor\r
//\r
// Ensure proper structure formats\r
//\r
#pragma pack(1)\r
-//\r
-// The commond definition of QWORD, DWORD, and WORD\r
-// Address Space Descriptors\r
-//\r
+\r
+///\r
+/// The commond definition of QWORD, DWORD, and WORD\r
+/// Address Space Descriptors\r
+///\r
typedef struct {\r
UINT8 Desc;\r
UINT16 Len;\r
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_TRANSLATION (1 << 5)\r
#define EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_TYPE_STATIC (0 << 5)\r
\r
-//\r
-// Ensure proper structure formats\r
-//\r
-#pragma pack(1)\r
//\r
// ACPI 1.0b table structures\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_1_0_WBINVD (1 << 0)\r
-#define EFI_ACPI_1_0_WBINVD_FLUSH (1 << 1)\r
-#define EFI_ACPI_1_0_PROC_C1 (1 << 2)\r
-#define EFI_ACPI_1_0_P_LVL2_UP (1 << 3)\r
-#define EFI_ACPI_1_0_PWR_BUTTON (1 << 4)\r
-#define EFI_ACPI_1_0_SLP_BUTTON (1 << 5)\r
-#define EFI_ACPI_1_0_FIX_RTC (1 << 6)\r
-#define EFI_ACPI_1_0_RTC_S4 (1 << 7)\r
-#define EFI_ACPI_1_0_TMR_VAL_EXT (1 << 8)\r
-#define EFI_ACPI_1_0_DCK_CAP (1 << 9)\r
+#define EFI_ACPI_1_0_WBINVD BIT0\r
+#define EFI_ACPI_1_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_1_0_PROC_C1 BIT2\r
+#define EFI_ACPI_1_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_1_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_1_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_1_0_FIX_RTC BIT6\r
+#define EFI_ACPI_1_0_RTC_S4 BIT7\r
+#define EFI_ACPI_1_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_1_0_DCK_CAP BIT9\r
\r
///\r
/// Firmware ACPI Control Structure\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_1_0_S4BIOS_F (1 << 0)\r
+#define EFI_ACPI_1_0_S4BIOS_F BIT0\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_1_0_PCAT_COMPAT (1 << 0)\r
+#define EFI_ACPI_1_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_1_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
UINT32 GlobalSystemInterruptVector;\r
} EFI_ACPI_1_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+\r
///\r
/// Local APIC NMI Structure\r
///\r
UINT8 LocalApicInti;\r
} EFI_ACPI_1_0_LOCAL_APIC_NMI_STRUCTURE;\r
\r
+#pragma pack()\r
+\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
///\r
#define EFI_ACPI_1_0_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32('S', 'S', 'D', 'T')\r
\r
-#pragma pack()\r
-\r
#endif\r
UINT64 Address;\r
} EFI_ACPI_2_0_GENERIC_ADDRESS_STRUCTURE;\r
\r
+#pragma pack()\r
+\r
//\r
// Generic Address Space Address IDs\r
//\r
///\r
#define EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION 0x03\r
\r
-///\r
-/// Fixed ACPI Description Table Boot Architecture Flags\r
-/// All other bits are reserved and must be set to 0.\r
-///\r
-#define EFI_ACPI_2_0_LEGACY_DEVICES (1 << 0)\r
-#define EFI_ACPI_2_0_8042 (1 << 1)\r
+//\r
+// Fixed ACPI Description Table Boot Architecture Flags\r
+// All other bits are reserved and must be set to 0.\r
+//\r
+#define EFI_ACPI_2_0_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_2_0_8042 BIT1\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_2_0_WBINVD (1 << 0)\r
-#define EFI_ACPI_2_0_WBINVD_FLUSH (1 << 1)\r
-#define EFI_ACPI_2_0_PROC_C1 (1 << 2)\r
-#define EFI_ACPI_2_0_P_LVL2_UP (1 << 3)\r
-#define EFI_ACPI_2_0_PWR_BUTTON (1 << 4)\r
-#define EFI_ACPI_2_0_SLP_BUTTON (1 << 5)\r
-#define EFI_ACPI_2_0_FIX_RTC (1 << 6)\r
-#define EFI_ACPI_2_0_RTC_S4 (1 << 7)\r
-#define EFI_ACPI_2_0_TMR_VAL_EXT (1 << 8)\r
-#define EFI_ACPI_2_0_DCK_CAP (1 << 9)\r
-#define EFI_ACPI_2_0_RESET_REG_SUP (1 << 10)\r
-#define EFI_ACPI_2_0_SEALED_CASE (1 << 11)\r
-#define EFI_ACPI_2_0_HEADLESS (1 << 12)\r
-#define EFI_ACPI_2_0_CPU_SW_SLP (1 << 13)\r
+#define EFI_ACPI_2_0_WBINVD BIT0\r
+#define EFI_ACPI_2_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_2_0_PROC_C1 BIT2\r
+#define EFI_ACPI_2_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_2_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_2_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_2_0_FIX_RTC BIT6\r
+#define EFI_ACPI_2_0_RTC_S4 BIT7\r
+#define EFI_ACPI_2_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_2_0_DCK_CAP BIT9\r
+#define EFI_ACPI_2_0_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_2_0_SEALED_CASE BIT11\r
+#define EFI_ACPI_2_0_HEADLESS BIT12\r
+#define EFI_ACPI_2_0_CPU_SW_SLP BIT13\r
\r
///\r
/// Firmware ACPI Control Structure\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_S4BIOS_F (1 << 0)\r
+#define EFI_ACPI_2_0_S4BIOS_F BIT0\r
\r
///\r
/// Multiple APIC Description Table header definition. The rest of the table\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_2_0_PCAT_COMPAT (1 << 0)\r
+#define EFI_ACPI_2_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_2_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_2_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
+\r
///\r
/// Local APIC NMI Structure\r
///\r
UINT64 LocalApicAddress;\r
} EFI_ACPI_2_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
+#pragma pack()\r
+\r
///\r
/// IO SAPIC Structure\r
///\r
///\r
#define EFI_ACPI_2_0_MEMORY_MAPPED_CONFIGURATION_BASE_ADDRESS_TABLE_SIGNATURE SIGNATURE_32('M', 'C', 'F', 'G')\r
\r
-#pragma pack()\r
-\r
#endif\r
/** @file \r
- ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006\r
+ ACPI 3.0 definitions from the ACPI Specification Revision 3.0b October 10, 2006.\r
\r
Copyright (c) 2006 - 2008, Intel Corporation\r
All rights reserved. This program and the accompanying materials \r
UINT8 AccessSize;\r
UINT64 Address;\r
} EFI_ACPI_3_0_GENERIC_ADDRESS_STRUCTURE;\r
+ \r
+#pragma pack()\r
\r
//\r
// Generic Address Space Address IDs\r
// Fixed ACPI Description Table Boot Architecture Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_3_0_LEGACY_DEVICES (1 << 0)\r
-#define EFI_ACPI_3_0_8042 (1 << 1)\r
-#define EFI_ACPI_3_0_VGA_NOT_PRESENT (1 << 2)\r
-#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED (1 << 3)\r
-#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS (1 << 4)\r
+#define EFI_ACPI_3_0_LEGACY_DEVICES BIT0\r
+#define EFI_ACPI_3_0_8042 BIT1\r
+#define EFI_ACPI_3_0_VGA_NOT_PRESENT BIT2\r
+#define EFI_ACPI_3_0_MSI_NOT_SUPPORTED BIT3\r
+#define EFI_ACPI_3_0_PCIE_ASPM_CONTROLS BIT4\r
\r
//\r
// Fixed ACPI Description Table Fixed Feature Flags\r
// All other bits are reserved and must be set to 0.\r
//\r
-#define EFI_ACPI_3_0_WBINVD (1 << 0)\r
-#define EFI_ACPI_3_0_WBINVD_FLUSH (1 << 1)\r
-#define EFI_ACPI_3_0_PROC_C1 (1 << 2)\r
-#define EFI_ACPI_3_0_P_LVL2_UP (1 << 3)\r
-#define EFI_ACPI_3_0_PWR_BUTTON (1 << 4)\r
-#define EFI_ACPI_3_0_SLP_BUTTON (1 << 5)\r
-#define EFI_ACPI_3_0_FIX_RTC (1 << 6)\r
-#define EFI_ACPI_3_0_RTC_S4 (1 << 7)\r
-#define EFI_ACPI_3_0_TMR_VAL_EXT (1 << 8)\r
-#define EFI_ACPI_3_0_DCK_CAP (1 << 9)\r
-#define EFI_ACPI_3_0_RESET_REG_SUP (1 << 10)\r
-#define EFI_ACPI_3_0_SEALED_CASE (1 << 11)\r
-#define EFI_ACPI_3_0_HEADLESS (1 << 12)\r
-#define EFI_ACPI_3_0_CPU_SW_SLP (1 << 13)\r
-#define EFI_ACPI_3_0_PCI_EXP_WAK (1 << 14)\r
-#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK (1 << 15)\r
-#define EFI_ACPI_3_0_S4_RTC_STS_VALID (1 << 16)\r
-#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE (1 << 17)\r
-#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL (1 << 18)\r
-#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE (1 << 19)\r
+#define EFI_ACPI_3_0_WBINVD BIT0\r
+#define EFI_ACPI_3_0_WBINVD_FLUSH BIT1\r
+#define EFI_ACPI_3_0_PROC_C1 BIT2\r
+#define EFI_ACPI_3_0_P_LVL2_UP BIT3\r
+#define EFI_ACPI_3_0_PWR_BUTTON BIT4\r
+#define EFI_ACPI_3_0_SLP_BUTTON BIT5\r
+#define EFI_ACPI_3_0_FIX_RTC BIT6\r
+#define EFI_ACPI_3_0_RTC_S4 BIT7\r
+#define EFI_ACPI_3_0_TMR_VAL_EXT BIT8\r
+#define EFI_ACPI_3_0_DCK_CAP BIT9\r
+#define EFI_ACPI_3_0_RESET_REG_SUP BIT10\r
+#define EFI_ACPI_3_0_SEALED_CASE BIT11\r
+#define EFI_ACPI_3_0_HEADLESS BIT12\r
+#define EFI_ACPI_3_0_CPU_SW_SLP BIT13\r
+#define EFI_ACPI_3_0_PCI_EXP_WAK BIT14\r
+#define EFI_ACPI_3_0_USE_PLATFORM_CLOCK BIT15\r
+#define EFI_ACPI_3_0_S4_RTC_STS_VALID BIT16\r
+#define EFI_ACPI_3_0_REMOTE_POWER_ON_CAPABLE BIT17\r
+#define EFI_ACPI_3_0_FORCE_APIC_CLUSTER_MODEL BIT18\r
+#define EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE BIT19\r
\r
///\r
/// Firmware ACPI Control Structure\r
/// Firmware Control Structure Feature Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_3_0_S4BIOS_F (1 << 0)\r
+#define EFI_ACPI_3_0_S4BIOS_F BIT0\r
\r
//\r
// Differentiated System Description Table,\r
/// Multiple APIC Flags\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_3_0_PCAT_COMPAT (1 << 0)\r
+#define EFI_ACPI_3_0_PCAT_COMPAT BIT0\r
\r
//\r
// Multiple APIC Description Table APIC structure types\r
///\r
/// Local APIC Flags. All other bits are reserved and must be 0.\r
///\r
-#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED (1 << 0)\r
+#define EFI_ACPI_3_0_LOCAL_APIC_ENABLED BIT0\r
\r
///\r
/// IO APIC Structure\r
UINT16 Flags;\r
UINT32 GlobalSystemInterrupt;\r
} EFI_ACPI_3_0_NON_MASKABLE_INTERRUPT_SOURCE_STRUCTURE;\r
+ \r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
\r
///\r
/// Local APIC NMI Structure\r
UINT64 LocalApicAddress;\r
} EFI_ACPI_3_0_LOCAL_APIC_ADDRESS_OVERRIDE_STRUCTURE;\r
\r
+#pragma pack()\r
+\r
///\r
/// IO SAPIC Structure\r
///\r
/// Platform Interrupt Source Flags.\r
/// All other bits are reserved and must be set to 0.\r
///\r
-#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE (1 << 0)\r
+#define EFI_ACPI_3_0_CPEI_PROCESSOR_OVERRIDE BIT0\r
\r
///\r
/// Smart Battery Description Table (SBST)\r
///\r
typedef struct {\r
EFI_ACPI_DESCRIPTION_HEADER Header;\r
- UINT32 Reserved1; // Must be set to 1\r
+ UINT32 Reserved1; ///< Must be set to 1\r
UINT64 Reserved2;\r
} EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER;\r
\r
///\r
#define EFI_ACPI_3_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION 0x02\r
\r
-///\r
-/// SRAT structure types.\r
-/// All other values between 0x02 an 0xFF are reserved and\r
-/// will be ignored by OSPM.\r
-///\r
+//\r
+// SRAT structure types.\r
+// All other values between 0x02 an 0xFF are reserved and\r
+// will be ignored by OSPM.\r
+//\r
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_AFFINITY 0x00\r
#define EFI_ACPI_3_0_MEMORY_AFFINITY 0x01\r
\r
///\r
#define EFI_ACPI_3_0_PROCESSOR_LOCAL_APIC_SAPIC_ENABLED (1 << 0)\r
\r
+//\r
+// Ensure proper structure formats\r
+//\r
+#pragma pack(1)\r
///\r
/// Memory Affinity Structure Definition\r
///\r
UINT64 Reserved3;\r
} EFI_ACPI_3_0_MEMORY_AFFINITY_STRUCTURE;\r
\r
+#pragma pack()\r
+\r
//\r
// Memory Flags. All other bits are reserved and must be 0.\r
//\r
///\r
#define EFI_ACPI_3_0_ISCSI_BOOT_FIRMWARE_TABLE_SIGNATURE SIGNATURE_32('i', 'B', 'F', 'T')\r
\r
-#pragma pack()\r
-\r
#endif\r
\r
#include <IndustryStandard/Acpi.h>\r
\r
-//\r
-// Ensure proper structure formats\r
-//\r
-#pragma pack (1)\r
-\r
///\r
/// Information Record header that appears at the beginning of each record\r
///\r
///\r
#define EFI_ACPI_ASF_DESCRIPTION_TABLE_SIGNATURE SIGNATURE_32 ('A', 'S', 'F', '!')\r
\r
-#pragma pack ()\r
-\r
-#endif // _ALERT_STANDARD_FORMAT_TABLE_H\r
+#endif \r
#ifndef _ATAPI_H_\r
#define _ATAPI_H_\r
\r
-#pragma pack(1)\r
-\r
///\r
/// ATAPI_IDENTIFY_DATA is defined in ATA-6\r
///\r
UINT8 additional_sense_bytes_18_253[253 - 18 + 1];\r
} ATAPI_REQUEST_SENSE_DATA;\r
\r
-///\r
-/// The followings are defined in SFF-8070i(ATAPI Removable Rewritable Specification)\r
-///\r
+//\r
+// The followings are defined in SFF-8070i(ATAPI Removable Rewritable Specification)\r
+//\r
\r
///\r
/// READ CAPACITY Data \r
ATAPI_READ_FORMAT_CAP_CMD ReadFormatCapacity;\r
} ATAPI_PACKET_COMMAND;\r
\r
-#pragma pack()\r
-\r
\r
#define ATAPI_MAX_DMA_EXT_CMD_SECTORS 0x10000\r
#define ATAPI_MAX_DMA_CMD_SECTORS 0x100\r
#define ATA_CMD_READ_LONG_WITH_RETRY 0x23 ///< defined in ATA-5\r
#define ATA_CMD_READ_SECTORS_EXT 0x24 ///< defined in ATA-6\r
\r
-\r
//\r
// Class 2: PIO Data-Out Commands\r
//\r
#define ATA_SMART_ENABLE_OPERATION 0xd8\r
#define ATA_SMART_RETURN_STATUS 0xda\r
\r
-\r
///\r
/// Class 4: DMA Command\r
///\r
#define ATA_CMD_WRITE_DMA 0xca ///< defined in ATA-6\r
#define ATA_CMD_WRITE_DMA_WITH_RETRY 0xcb ///< defined in ATA-4\r
#define ATA_CMD_WRITE_DMA_EXT 0x35 ///< defined in ATA-6\r
-\r
-\r
-\r
+ \r
///\r
/// default content of device control register, disable INT,\r
/// Bit3 is set to 1 according ATA-1\r
\r
#define ATA_REQUEST_SENSE_ERROR (0x70) ///< defined in SFF-8070i\r
\r
-///\r
-/// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier\r
-/// defined in MultiMedia Commands (MMC, MMC-2) \r
-///\r
-/// Sense Key \r
-///\r
+//\r
+// Sense Key, Additional Sense Codes and Additional Sense Code Qualifier\r
+// defined in MultiMedia Commands (MMC, MMC-2) \r
+//\r
+// Sense Key \r
+//\r
#define ATA_SK_NO_SENSE (0x0)\r
#define ATA_SK_RECOVERY_ERROR (0x1)\r
#define ATA_SK_NOT_READY (0x2)\r
#define ATA_SK_MISCOMPARE (0xE)\r
#define ATA_SK_RESERVED_F (0xF)\r
\r
-///\r
-/// Additional Sense Codes\r
-///\r
+//\r
+// Additional Sense Codes\r
+//\r
#define ATA_ASC_NOT_READY (0x04)\r
#define ATA_ASC_MEDIA_ERR1 (0x10)\r
#define ATA_ASC_MEDIA_ERR2 (0x11)\r
//\r
#define ATA_ASCQ_IN_PROGRESS (0x01)\r
\r
-///\r
-/// Error Register\r
-///\r
+//\r
+// Error Register\r
+//\r
#define ATA_ERRREG_BBK BIT7 ///< Bad block detected defined in ATA-1\r
#define ATA_ERRREG_UNC BIT6 ///< Uncorrectable Data defined in ATA-3\r
#define ATA_ERRREG_MC BIT5 ///< Media Change defined in ATA-3\r
#define ATA_ERRREG_TK0NF BIT1 ///< Track 0 Not Found defined in ATA-3\r
#define ATA_ERRREG_AMNF BIT0 ///< Address Mark Not Found defined in ATA-3\r
\r
-///\r
-/// Status Register\r
-///\r
+//\r
+// Status Register\r
+//\r
#define ATA_STSREG_BSY BIT7 ///< Controller Busy defined in ATA-6\r
#define ATA_STSREG_DRDY BIT6 ///< Drive Ready defined in ATA-6\r
#define ATA_STSREG_DWF BIT5 ///< Drive Write Fault defined in ATA-6\r
#define ATA_STSREG_IDX BIT1 ///< Index defined in ATA-3\r
#define ATA_STSREG_ERR BIT0 ///< Error defined in ATA-6\r
\r
-///\r
-/// Device Control Register\r
-///\r
+//\r
+// Device Control Register\r
+//\r
#define ATA_CTLREG_SRST BIT2 ///< Software Reset\r
#define ATA_CTLREG_IEN_L BIT1 ///< Interrupt Enable #\r
\r
#ifndef _ELTORITO_H_\r
#define _ELTORITO_H_\r
\r
-///\r
-/// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660\r
-///\r
+//\r
+// CDROM_VOLUME_DESCRIPTOR.Types, defined in ISO 9660\r
+//\r
#define CDVOL_TYPE_STANDARD 0x0\r
#define CDVOL_TYPE_CODED 0x1\r
#define CDVOL_TYPE_END 0xFF\r
#define ELTORITO_HARD_DISK 0x04\r
\r
\r
-#pragma pack(1)\r
-\r
/// \r
/// CD-ROM Volume Descriptor\r
/// \r
\r
} ELTORITO_CATALOG;\r
\r
-#pragma pack()\r
-\r
#endif\r
UINT8 PageProtectionAndOemAttribute;\r
} EFI_ACPI_HIGH_PRECISION_EVENT_TIMER_TABLE_HEADER;\r
\r
+#pragma pack()\r
+\r
///\r
/// HPET Revision (defined in spec)\r
///\r
#define EFI_ACPI_4KB_PAGE_PROTECTION 1\r
#define EFI_ACPI_64KB_PAGE_PROTECTION 2\r
\r
-#pragma pack()\r
-\r
#endif\r