\r
**/\r
\r
-#include <Base.h>\r
+#include <Uefi.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/TimerLib.h>\r
\r
#include <Omap3530/Omap3530.h>\r
\r
+RETURN_STATUS\r
+EFIAPI\r
+TimerConstructor (\r
+ VOID\r
+ )\r
+{\r
+ UINTN Timer = PcdGet32(PcdOmap35xxFreeTimer);\r
+ UINT32 TimerBaseAddress = TimerBase(Timer);\r
+\r
+ if ((MmioRead32 (TimerBaseAddress + GPTIMER_TCLR) & TCLR_ST_ON) == 0) {\r
+ // Set source clock for GPT3 & GPT4 to SYS_CLK\r
+ MmioOr32 (CM_CLKSEL_PER, CM_CLKSEL_PER_CLKSEL_GPT3_SYS | CM_CLKSEL_PER_CLKSEL_GPT4_SYS);\r
+\r
+ // Set count & reload registers\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCRR, 0x00000000);\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TLDR, 0x00000000);\r
+\r
+ // Disable interrupts\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_DISABLE | TIER_MAT_IT_DISABLE);\r
+\r
+ // Start Timer\r
+ MmioWrite32 (TimerBaseAddress + GPTIMER_TCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r
+\r
+ // Disable OMAP Watchdog timer (WDT2)\r
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0xAAAA);\r
+ DEBUG ((EFI_D_ERROR, "Magic delay to disable watchdog timers properly.\n"));\r
+ MmioWrite32 (WDTIMER2_BASE + WSPR, 0x5555);\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
UINTN\r
EFIAPI\r
MicroSecondDelay (\r