80 A8 B0 B8 C0
+----------WB--------+-UC-+-WT-+-WB-+
For above memory settings, current code caused the final MTRR
settings miss [A8, B0, UC] when default memory type is UC.
The root cause is the code only checks the mandatory weight
between A8 to B0, but skips to check the optional weight.
The patch fixes this issue.
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
UINT64 Address;\r
UINT64 Alignment;\r
UINT64 Length;\r
UINT64 Address;\r
UINT64 Alignment;\r
UINT64 Length;\r
+ MTRR_MEMORY_CACHE_TYPE Type : 7;\r
\r
//\r
// Temprary use for calculating the best MTRR settings.\r
\r
//\r
// Temprary use for calculating the best MTRR settings.\r
while (SubStart != SubStop) {\r
Status = MtrrLibAppendVariableMtrr (\r
Mtrrs, MtrrCapacity, MtrrCount,\r
while (SubStart != SubStop) {\r
Status = MtrrLibAppendVariableMtrr (\r
Mtrrs, MtrrCapacity, MtrrCount,\r
- Vertices[SubStart].Address, Vertices[SubStart].Length, (MTRR_MEMORY_CACHE_TYPE) Vertices[SubStart].Type\r
+ Vertices[SubStart].Address, Vertices[SubStart].Length, Vertices[SubStart].Type\r
);\r
if (RETURN_ERROR (Status)) {\r
return Status;\r
);\r
if (RETURN_ERROR (Status)) {\r
return Status;\r
Pre = Vertices[Cur].Previous;\r
SubStop = Pre;\r
\r
Pre = Vertices[Cur].Previous;\r
SubStop = Pre;\r
\r
- if (Weight[M (Pre, Cur)] != 0) {\r
+ if (Weight[M (Pre, Cur)] + Weight[O (Pre, Cur)] != 0) {\r
Status = MtrrLibAppendVariableMtrr (\r
Mtrrs, MtrrCapacity, MtrrCount,\r
Status = MtrrLibAppendVariableMtrr (\r
Mtrrs, MtrrCapacity, MtrrCount,\r
- Vertices[Pre].Address, Vertices[Cur].Address - Vertices[Pre].Address, LowestPrecedentType\r
+ Vertices[Pre].Address, Vertices[Cur].Address - Vertices[Pre].Address,\r
+ (Pre != Cur - 1) ? LowestPrecedentType : Vertices[Pre].Type\r
);\r
if (RETURN_ERROR (Status)) {\r
return Status;\r
);\r
if (RETURN_ERROR (Status)) {\r
return Status;\r