/** @file\r
-CPUID Definitions.\r
+ CPUID leaf definitions.\r
\r
-CPUID definitions based on contents of the Intel(R) 64 and IA-32 Architectures\r
-Software Developer's Manual, Volume 2A, CPUID instruction.\r
+ Provides defines for CPUID leaf indexes. Data structures are provided for\r
+ registers returned by a CPUID leaf that contain one or more bit fields.\r
+ If a register returned is a single 32-bit value, then a data structure is\r
+ not provided for that register.\r
\r
-Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
-This program and the accompanying materials\r
-are licensed and made available under the terms and conditions of the BSD License\r
-which accompanies this distribution. The full text of the license may be found at\r
-http://opensource.org/licenses/bsd-license.php\r
+ Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials are licensed and made available under\r
+ the terms and conditions of the BSD License which accompanies this distribution.\r
+ The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
\r
-THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
-WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 2A,\r
+ December 2015, CPUID instruction.\r
\r
**/\r
\r
#ifndef __CPUID_H__\r
#define __CPUID_H__\r
\r
-//\r
-// Definitions for CPUID instruction\r
-//\r
-#define CPUID_SIGNATURE 0x0\r
+/**\r
+ CPUID Signature Information\r
+\r
+ @param EAX CPUID_SIGNATURE (0x00)\r
+\r
+ @retval EAX Returns the highest value the CPUID instruction recognizes for\r
+ returning basic processor information. The value is returned is\r
+ processor specific.\r
+ @retval EBX First 4 characters of a vendor identification string.\r
+ @retval ECX Last 4 characters of a vendor identification string.\r
+ @retval EDX Middle 4 characters of a vendor identification string.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuid (CPUID_SIGNATURE, &Eax, &Ebx, &Ecx, &Edx);\r
+ @endcode\r
+**/\r
+#define CPUID_SIGNATURE 0x00\r
+\r
+///\r
+/// @{ CPUID signature values returned by Intel processors\r
+///\r
+#define CPUID_SIGNATURE_GENUINE_INTEL_EBX SIGNATURE_32 ('G', 'e', 'n', 'u')\r
+#define CPUID_SIGNATURE_GENUINE_INTEL_EDX SIGNATURE_32 ('i', 'n', 'e', 'I')\r
+#define CPUID_SIGNATURE_GENUINE_INTEL_ECX SIGNATURE_32 ('n', 't', 'e', 'l')\r
+///\r
+/// @}\r
+///\r
+\r
+\r
+/**\r
+ CPUID Version Information\r
+\r
+ @param EAX CPUID_VERSION_INFO (0x01)\r
+\r
+ @retval EAX Returns Model, Family, Stepping Information described by the\r
+ type CPUID_VERSION_INFO_EAX.\r
+ @retval EBX Returns Brand, Cache Line Size, and Initial APIC ID described by\r
+ the type CPUID_VERSION_INFO_EBX.\r
+ @retval ECX CPU Feature Information described by the type\r
+ CPUID_VERSION_INFO_ECX.\r
+ @retval EDX CPU Feature Information described by the type\r
+ CPUID_VERSION_INFO_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_VERSION_INFO_EAX Eax;\r
+ CPUID_VERSION_INFO_EBX Ebx;\r
+ CPUID_VERSION_INFO_ECX Ecx;\r
+ CPUID_VERSION_INFO_EDX Edx;\r
+\r
+ AsmCpuid (CPUID_VERSION_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
+ @endcode\r
+**/\r
+#define CPUID_VERSION_INFO 0x01\r
+\r
+/**\r
+ CPUID Version Information returned in EAX for CPUID leaf\r
+ #CPUID_VERSION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 SteppingId:4; ///< [Bits 3:0] Stepping ID\r
+ UINT32 Model:4; ///< [Bits 7:4] Model\r
+ UINT32 FamilyId:4; ///< [Bits 11:8] Family\r
+ UINT32 ProcessorType:2; ///< [Bits 13:12] Processor Type\r
+ UINT32 Reserved1:2; ///< [Bits 15:14] Reserved\r
+ UINT32 ExtendedModelId:4; ///< [Bits 19:16] Extended Model ID\r
+ UINT32 ExtendedFamilyId:8; ///< [Bits 27:20] Extended Family ID\r
+ UINT32 Reserved2:4; ///< Reserved\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_VERSION_INFO_EAX;\r
+\r
+///\r
+/// @{ Define value for bit field CPUID_VERSION_INFO_EAX.ProcessorType\r
+///\r
+#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_ORIGINAL_OEM_PROCESSOR 0x00\r
+#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_INTEL_OVERDRIVE_PROCESSOR 0x01\r
+#define CPUID_VERSION_INFO_EAX_PROCESSOR_TYPE_DUAL_PROCESSOR 0x02\r
+///\r
+/// @}\r
+///\r
+\r
+/**\r
+ CPUID Version Information returned in EBX for CPUID leaf\r
+ #CPUID_VERSION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Provides an entry into a brand string table that contains\r
+ /// brand strings for IA-32 processors.\r
+ ///\r
+ UINT32 BrandIndex:8;\r
+ ///\r
+ /// [Bits 15:8] Indicates the size of the cache line flushed by the CLFLUSH\r
+ /// and CLFLUSHOPT instructions in 8-byte increments. This field was\r
+ /// introduced in the Pentium 4 processor.\r
+ ///\r
+ UINT32 CacheLineSize:8;\r
+ ///\r
+ /// [Bits 23:16] Maximum number of addressable IDs for logical processors\r
+ /// in this physical package.\r
+ ///\r
+ /// @note\r
+ /// The nearest power-of-2 integer that is not smaller than EBX[23:16] is\r
+ /// the number of unique initial APICIDs reserved for addressing different\r
+ /// logical processors in a physical package. This field is only valid if\r
+ /// CPUID.1.EDX.HTT[bit 28]= 1.\r
+ ///\r
+ UINT32 MaximumAddressableIdsForLogicalProcessors:8;\r
+ ///\r
+ /// [Bits 31:24] The 8-bit ID that is assigned to the local APIC on the\r
+ /// processor during power up. This field was introduced in the Pentium 4\r
+ /// processor.\r
+ ///\r
+ UINT32 InitialLocalApicId:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_VERSION_INFO_EBX;\r
+\r
+/**\r
+ CPUID Version Information returned in ECX for CPUID leaf\r
+ #CPUID_VERSION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Streaming SIMD Extensions 3 (SSE3). A value of 1 indicates the\r
+ /// processor supports this technology\r
+ ///\r
+ UINT32 SSE3:1;\r
+ ///\r
+ /// [Bit 1] A value of 1 indicates the processor supports the PCLMULQDQ\r
+ /// instruction. Carryless Multiplication\r
+ ///\r
+ UINT32 PCLMULQDQ:1;\r
+ ///\r
+ /// [Bit 2] 64-bit DS Area. A value of 1 indicates the processor supports\r
+ /// DS area using 64-bit layout.\r
+ ///\r
+ UINT32 DTES64:1;\r
+ ///\r
+ /// [Bit 3] MONITOR/MWAIT. A value of 1 indicates the processor supports\r
+ /// this feature.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ ///\r
+ /// [Bit 4] CPL Qualified Debug Store. A value of 1 indicates the processor\r
+ /// supports the extensions to the Debug Store feature to allow for branch\r
+ /// message storage qualified by CPL\r
+ ///\r
+ UINT32 DS_CPL:1;\r
+ ///\r
+ /// [Bit 5] Virtual Machine Extensions. A value of 1 indicates that the\r
+ /// processor supports this technology.\r
+ ///\r
+ UINT32 VMX:1;\r
+ ///\r
+ /// [Bit 6] Safer Mode Extensions. A value of 1 indicates that the processor\r
+ /// supports this technology\r
+ ///\r
+ UINT32 SMX:1;\r
+ ///\r
+ /// [Bit 7] Enhanced Intel SpeedStep(R) technology. A value of 1 indicates\r
+ /// that the processor supports this technology\r
+ ///\r
+ UINT32 EIST:1;\r
+ ///\r
+ /// [Bit 8] Thermal Monitor 2. A value of 1 indicates whether the processor\r
+ /// supports this technology\r
+ ///\r
+ UINT32 TM2:1;\r
+ ///\r
+ /// [Bit 9] A value of 1 indicates the presence of the Supplemental Streaming\r
+ /// SIMD Extensions 3 (SSSE3). A value of 0 indicates the instruction\r
+ /// extensions are not present in the processor.\r
+ ///\r
+ UINT32 SSSE3:1;\r
+ ///\r
+ /// [Bit 10] L1 Context ID. A value of 1 indicates the L1 data cache mode\r
+ /// can be set to either adaptive mode or shared mode. A value of 0 indicates\r
+ /// this feature is not supported. See definition of the IA32_MISC_ENABLE MSR\r
+ /// Bit 24 (L1 Data Cache Context Mode) for details\r
+ ///\r
+ UINT32 CNXT_ID:1;\r
+ ///\r
+ /// [Bit 11] A value of 1 indicates the processor supports IA32_DEBUG_INTERFACE\r
+ /// MSR for silicon debug\r
+ ///\r
+ UINT32 SDBG:1;\r
+ ///\r
+ /// [Bit 12] A value of 1 indicates the processor supports FMA (Fused Multiple\r
+ /// Add) extensions using YMM state.\r
+ ///\r
+ UINT32 FMA:1;\r
+ ///\r
+ /// [Bit 13] CMPXCHG16B Available. A value of 1 indicates that the feature\r
+ /// is available.\r
+ ///\r
+ UINT32 CMPXCHG16B:1;\r
+ ///\r
+ /// [Bit 14] xTPR Update Control. A value of 1 indicates that the processor\r
+ /// supports changing IA32_MISC_ENABLE[Bit 23].\r
+ ///\r
+ UINT32 xTPR_Update_Control:1;\r
+ ///\r
+ /// [Bit 15] Perfmon and Debug Capability: A value of 1 indicates the\r
+ /// processor supports the performance and debug feature indication MSR\r
+ /// IA32_PERF_CAPABILITIES.\r
+ ///\r
+ UINT32 PDCM:1;\r
+ UINT32 Reserved:1;\r
+ ///\r
+ /// [Bit 17] Process-context identifiers. A value of 1 indicates that the\r
+ /// processor supports PCIDs and that software may set CR4.PCIDE to 1.\r
+ ///\r
+ UINT32 PCID:1;\r
+ ///\r
+ /// [Bit 18] A value of 1 indicates the processor supports the ability to\r
+ /// prefetch data from a memory mapped device. Direct Cache Access.\r
+ ///\r
+ UINT32 DCA:1;\r
+ ///\r
+ /// [Bit 19] A value of 1 indicates that the processor supports SSE4.1.\r
+ ///\r
+ UINT32 SSE4_1:1;\r
+ ///\r
+ /// [Bit 20] A value of 1 indicates that the processor supports SSE4.2.\r
+ ///\r
+ UINT32 SSE4_2:1;\r
+ ///\r
+ /// [Bit 21] A value of 1 indicates that the processor supports x2APIC\r
+ /// feature.\r
+ ///\r
+ UINT32 x2APIC:1;\r
+ ///\r
+ /// [Bit 22] A value of 1 indicates that the processor supports MOVBE\r
+ /// instruction.\r
+ ///\r
+ UINT32 MOVBE:1;\r
+ ///\r
+ /// [Bit 23] A value of 1 indicates that the processor supports the POPCNT\r
+ /// instruction.\r
+ ///\r
+ UINT32 POPCNT:1;\r
+ ///\r
+ /// [Bit 24] A value of 1 indicates that the processor's local APIC timer\r
+ /// supports one-shot operation using a TSC deadline value.\r
+ ///\r
+ UINT32 TSC_Deadline:1;\r
+ ///\r
+ /// [Bit 25] A value of 1 indicates that the processor supports the AESNI\r
+ /// instruction extensions.\r
+ ///\r
+ UINT32 AESNI:1;\r
+ ///\r
+ /// [Bit 26] A value of 1 indicates that the processor supports the\r
+ /// XSAVE/XRSTOR processor extended states feature, the XSETBV/XGETBV\r
+ /// instructions, and XCR0.\r
+ ///\r
+ UINT32 XSAVE:1;\r
+ ///\r
+ /// [Bit 27] A value of 1 indicates that the OS has set CR4.OSXSAVE[Bit 18]\r
+ /// to enable XSETBV/XGETBV instructions to access XCR0 and to support\r
+ /// processor extended state management using XSAVE/XRSTOR.\r
+ ///\r
+ UINT32 OSXSAVE:1;\r
+ ///\r
+ /// [Bit 28] A value of 1 indicates the processor supports the AVX instruction\r
+ /// extensions.\r
+ ///\r
+ UINT32 AVX:1;\r
+ ///\r
+ /// [Bit 29] A value of 1 indicates that processor supports 16-bit\r
+ /// floating-point conversion instructions.\r
+ ///\r
+ UINT32 F16C:1;\r
+ ///\r
+ /// [Bit 30] A value of 1 indicates that processor supports RDRAND instruction.\r
+ ///\r
+ UINT32 RDRAND:1;\r
+ ///\r
+ /// [Bit 31] Always returns 0.\r
+ ///\r
+ UINT32 NotUsed:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_VERSION_INFO_ECX;\r
+\r
+/**\r
+ CPUID Version Information returned in EDX for CPUID leaf\r
+ #CPUID_VERSION_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Floating Point Unit On-Chip. The processor contains an x87 FPU.\r
+ ///\r
+ UINT32 FPU:1;\r
+ ///\r
+ /// [Bit 1] Virtual 8086 Mode Enhancements. Virtual 8086 mode enhancements,\r
+ /// including CR4.VME for controlling the feature, CR4.PVI for protected\r
+ /// mode virtual interrupts, software interrupt indirection, expansion of\r
+ /// the TSS with the software indirection bitmap, and EFLAGS.VIF and\r
+ /// EFLAGS.VIP flags.\r
+ ///\r
+ UINT32 VME:1;\r
+ ///\r
+ /// [Bit 2] Debugging Extensions. Support for I/O breakpoints, including\r
+ /// CR4.DE for controlling the feature, and optional trapping of accesses to\r
+ /// DR4 and DR5.\r
+ ///\r
+ UINT32 DE:1;\r
+ ///\r
+ /// [Bit 3] Page Size Extension. Large pages of size 4 MByte are supported,\r
+ /// including CR4.PSE for controlling the feature, the defined dirty bit in\r
+ /// PDE (Page Directory Entries), optional reserved bit trapping in CR3,\r
+ /// PDEs, and PTEs.\r
+ ///\r
+ UINT32 PSE:1;\r
+ ///\r
+ /// [Bit 4] Time Stamp Counter. The RDTSC instruction is supported,\r
+ /// including CR4.TSD for controlling privilege.\r
+ ///\r
+ UINT32 TSC:1;\r
+ ///\r
+ /// [Bit 5] Model Specific Registers RDMSR and WRMSR Instructions. The\r
+ /// RDMSR and WRMSR instructions are supported. Some of the MSRs are\r
+ /// implementation dependent.\r
+ ///\r
+ UINT32 MSR:1;\r
+ ///\r
+ /// [Bit 6] Physical Address Extension. Physical addresses greater than 32\r
+ /// bits are supported: extended page table entry formats, an extra level in\r
+ /// the page translation tables is defined, 2-MByte pages are supported\r
+ /// instead of 4 Mbyte pages if PAE bit is 1.\r
+ ///\r
+ UINT32 PAE:1;\r
+ ///\r
+ /// [Bit 7] Machine Check Exception. Exception 18 is defined for Machine\r
+ /// Checks, including CR4.MCE for controlling the feature. This feature does\r
+ /// not define the model-specific implementations of machine-check error\r
+ /// logging, reporting, and processor shutdowns. Machine Check exception\r
+ /// handlers may have to depend on processor version to do model specific\r
+ /// processing of the exception, or test for the presence of the Machine\r
+ /// Check feature.\r
+ ///\r
+ UINT32 MCE:1;\r
+ ///\r
+ /// [Bit 8] CMPXCHG8B Instruction. The compare-and-exchange 8 bytes(64 bits)\r
+ /// instruction is supported (implicitly locked and atomic).\r
+ ///\r
+ UINT32 CX8:1;\r
+ ///\r
+ /// [Bit 9] APIC On-Chip. The processor contains an Advanced Programmable\r
+ /// Interrupt Controller (APIC), responding to memory mapped commands in the\r
+ /// physical address range FFFE0000H to FFFE0FFFH (by default - some\r
+ /// processors permit the APIC to be relocated).\r
+ ///\r
+ UINT32 APIC:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 11] SYSENTER and SYSEXIT Instructions. The SYSENTER and SYSEXIT\r
+ /// and associated MSRs are supported.\r
+ ///\r
+ UINT32 SEP:1;\r
+ ///\r
+ /// [Bit 12] Memory Type Range Registers. MTRRs are supported. The MTRRcap\r
+ /// MSR contains feature bits that describe what memory types are supported,\r
+ /// how many variable MTRRs are supported, and whether fixed MTRRs are\r
+ /// supported.\r
+ ///\r
+ UINT32 MTRR:1;\r
+ ///\r
+ /// [Bit 13] Page Global Bit. The global bit is supported in paging-structure\r
+ /// entries that map a page, indicating TLB entries that are common to\r
+ /// different processes and need not be flushed. The CR4.PGE bit controls\r
+ /// this feature.\r
+ ///\r
+ UINT32 PGE:1;\r
+ ///\r
+ /// [Bit 14] Machine Check Architecture. The Machine Check Architecture,\r
+ /// which provides a compatible mechanism for error reporting in P6 family,\r
+ /// Pentium 4, Intel Xeon processors, and future processors, is supported.\r
+ /// The MCG_CAP MSR contains feature bits describing how many banks of error\r
+ /// reporting MSRs are supported.\r
+ ///\r
+ UINT32 MCA:1;\r
+ ///\r
+ /// [Bit 15] Conditional Move Instructions. The conditional move instruction\r
+ /// CMOV is supported. In addition, if x87 FPU is present as indicated by the\r
+ /// CPUID.FPU feature bit, then the FCOMI and FCMOV instructions are supported.\r
+ ///\r
+ UINT32 CMOV:1;\r
+ ///\r
+ /// [Bit 16] Page Attribute Table. Page Attribute Table is supported. This\r
+ /// feature augments the Memory Type Range Registers (MTRRs), allowing an\r
+ /// operating system to specify attributes of memory accessed through a\r
+ /// linear address on a 4KB granularity.\r
+ ///\r
+ UINT32 PAT:1;\r
+ ///\r
+ /// [Bit 17] 36-Bit Page Size Extension. 4-MByte pages addressing physical\r
+ /// memory beyond 4 GBytes are supported with 32-bit paging. This feature\r
+ /// indicates that upper bits of the physical address of a 4-MByte page are\r
+ /// encoded in bits 20:13 of the page-directory entry. Such physical\r
+ /// addresses are limited by MAXPHYADDR and may be up to 40 bits in size.\r
+ ///\r
+ UINT32 PSE_36:1;\r
+ ///\r
+ /// [Bit 18] Processor Serial Number. The processor supports the 96-bit\r
+ /// processor identification number feature and the feature is enabled.\r
+ ///\r
+ UINT32 PSN:1;\r
+ ///\r
+ /// [Bit 19] CLFLUSH Instruction. CLFLUSH Instruction is supported.\r
+ ///\r
+ UINT32 CLFSH:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 21] Debug Store. The processor supports the ability to write debug\r
+ /// information into a memory resident buffer. This feature is used by the\r
+ /// branch trace store (BTS) and precise event-based sampling (PEBS)\r
+ /// facilities.\r
+ ///\r
+ UINT32 DS:1;\r
+ ///\r
+ /// [Bit 22] Thermal Monitor and Software Controlled Clock Facilities. The\r
+ /// processor implements internal MSRs that allow processor temperature to\r
+ /// be monitored and processor performance to be modulated in predefined\r
+ /// duty cycles under software control.\r
+ ///\r
+ UINT32 ACPI:1;\r
+ ///\r
+ /// [Bit 23] Intel MMX Technology. The processor supports the Intel MMX\r
+ /// technology.\r
+ ///\r
+ UINT32 MMX:1;\r
+ ///\r
+ /// [Bit 24] FXSAVE and FXRSTOR Instructions. The FXSAVE and FXRSTOR\r
+ /// instructions are supported for fast save and restore of the floating\r
+ /// point context. Presence of this bit also indicates that CR4.OSFXSR is\r
+ /// available for an operating system to indicate that it supports the\r
+ /// FXSAVE and FXRSTOR instructions.\r
+ ///\r
+ UINT32 FXSR:1;\r
+ ///\r
+ /// [Bit 25] SSE. The processor supports the SSE extensions.\r
+ ///\r
+ UINT32 SSE:1;\r
+ ///\r
+ /// [Bit 26] SSE2. The processor supports the SSE2 extensions.\r
+ ///\r
+ UINT32 SSE2:1;\r
+ ///\r
+ /// [Bit 27] Self Snoop. The processor supports the management of\r
+ /// conflicting memory types by performing a snoop of its own cache\r
+ /// structure for transactions issued to the bus.\r
+ ///\r
+ UINT32 SS:1;\r
+ ///\r
+ /// [Bit 28] Max APIC IDs reserved field is Valid. A value of 0 for HTT\r
+ /// indicates there is only a single logical processor in the package and\r
+ /// software should assume only a single APIC ID is reserved. A value of 1\r
+ /// for HTT indicates the value in CPUID.1.EBX[23:16] (the Maximum number of\r
+ /// addressable IDs for logical processors in this package) is valid for the\r
+ /// package.\r
+ ///\r
+ UINT32 HTT:1;\r
+ ///\r
+ /// [Bit 29] Thermal Monitor. The processor implements the thermal monitor\r
+ /// automatic thermal control circuitry (TCC).\r
+ ///\r
+ UINT32 TM:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 31] Pending Break Enable. The processor supports the use of the\r
+ /// FERR#/PBE# pin when the processor is in the stop-clock state (STPCLK# is\r
+ /// asserted) to signal the processor that an interrupt is pending and that\r
+ /// the processor should return to normal operation to handle the interrupt.\r
+ /// Bit 10 (PBE enable) in the IA32_MISC_ENABLE MSR enables this capability.\r
+ ///\r
+ UINT32 PBE:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_VERSION_INFO_EDX;\r
+\r
+\r
+/**\r
+ CPUID Cache and TLB Information\r
+\r
+ @param EAX CPUID_CACHE_INFO (0x02)\r
+\r
+ @retval EAX Cache and TLB Information described by the type\r
+ CPUID_CACHE_INFO_CACHE_TLB.\r
+ CPUID_CACHE_INFO_CACHE_TLB.CacheDescriptor[0] always returns\r
+ 0x01 and must be ignored. Only valid if\r
+ CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
+ @retval EBX Cache and TLB Information described by the type\r
+ CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r
+ CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
+ @retval ECX Cache and TLB Information described by the type\r
+ CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r
+ CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
+ @retval EDX Cache and TLB Information described by the type\r
+ CPUID_CACHE_INFO_CACHE_TLB. Only valid if\r
+ CPUID_CACHE_INFO_CACHE_TLB.Bits.NotValid is clear.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_CACHE_INFO_CACHE_TLB Eax;\r
+ CPUID_CACHE_INFO_CACHE_TLB Ebx;\r
+ CPUID_CACHE_INFO_CACHE_TLB Ecx;\r
+ CPUID_CACHE_INFO_CACHE_TLB Edx;\r
+\r
+ AsmCpuid (CPUID_CACHE_INFO, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
+ @endcode\r
+\r
+ <b>Cache Descriptor values</b>\r
+ <table>\r
+ <tr><th>Value </th><th> Type </th><th> Description </th></tr>\r
+ <tr><td> 0x00 </td><td> General </td><td> Null descriptor, this byte contains no information</td></tr>\r
+ <tr><td> 0x01 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 32 entries</td></tr>\r
+ <tr><td> 0x02 </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, fully associative, 2 entries</td></tr>\r
+ <tr><td> 0x03 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 64 entries</td></tr>\r
+ <tr><td> 0x04 </td><td> TLB </td><td> Data TLB: 4 MByte pages, 4-way set associative, 8 entries</td></tr>\r
+ <tr><td> 0x05 </td><td> TLB </td><td> Data TLB1: 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
+ <tr><td> 0x06 </td><td> Cache </td><td> 1st-level instruction cache: 8 KBytes, 4-way set associative,\r
+ 32 byte line size</td></tr>\r
+ <tr><td> 0x08 </td><td> Cache </td><td> 1st-level instruction cache: 16 KBytes, 4-way set associative,\r
+ 32 byte line size</td></tr>\r
+ <tr><td> 0x09 </td><td> Cache </td><td> 1st-level instruction cache: 32KBytes, 4-way set associative,\r
+ 64 byte line size</td></tr>\r
+ <tr><td> 0x0A </td><td> Cache </td><td> 1st-level data cache: 8 KBytes, 2-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x0B </td><td> TLB </td><td> Instruction TLB: 4 MByte pages, 4-way set associative, 4 entries</td></tr>\r
+ <tr><td> 0x0C </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x0D </td><td> Cache </td><td> 1st-level data cache: 16 KBytes, 4-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x0E </td><td> Cache </td><td> 1st-level data cache: 24 KBytes, 6-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x1D </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 2-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x21 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 8-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x22 </td><td> Cache </td><td> 3rd-level cache: 512 KBytes, 4-way set associative, 64 byte line size,\r
+ 2 lines per sector</td></tr>\r
+ <tr><td> 0x23 </td><td> Cache </td><td> 3rd-level cache: 1 MBytes, 8-way set associative, 64 byte line size,\r
+ 2 lines per sector</td></tr>\r
+ <tr><td> 0x24 </td><td> Cache </td><td> 2nd-level cache: 1 MBytes, 16-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x25 </td><td> Cache </td><td> 3rd-level cache: 2 MBytes, 8-way set associative, 64 byte line size,\r
+ 2 lines per sector</td></tr>\r
+ <tr><td> 0x29 </td><td> Cache </td><td> 3rd-level cache: 4 MBytes, 8-way set associative, 64 byte line size,\r
+ 2 lines per sector</td></tr>\r
+ <tr><td> 0x2C </td><td> Cache </td><td> 1st-level data cache: 32 KBytes, 8-way set associative,\r
+ 64 byte line size</td></tr>\r
+ <tr><td> 0x30 </td><td> Cache </td><td> 1st-level instruction cache: 32 KBytes, 8-way set associative,\r
+ 64 byte line size</td></tr>\r
+ <tr><td> 0x40 </td><td> Cache </td><td> No 2nd-level cache or, if processor contains a valid 2nd-level cache,\r
+ no 3rd-level cache</td></tr>\r
+ <tr><td> 0x41 </td><td> Cache </td><td> 2nd-level cache: 128 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x42 </td><td> Cache </td><td> 2nd-level cache: 256 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x43 </td><td> Cache </td><td> 2nd-level cache: 512 KBytes, 4-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x44 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x45 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 4-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x46 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 4-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x47 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 8-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x48 </td><td> Cache </td><td> 2nd-level cache: 3MByte, 12-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x49 </td><td> Cache </td><td> 3rd-level cache: 4MB, 16-way set associative, 64-byte line size\r
+ (Intel Xeon processor MP, Family 0FH, Model 06H)<BR>\r
+ 2nd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x4A </td><td> Cache </td><td> 3rd-level cache: 6MByte, 12-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x4B </td><td> Cache </td><td> 3rd-level cache: 8MByte, 16-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x4C </td><td> Cache </td><td> 3rd-level cache: 12MByte, 12-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x4D </td><td> Cache </td><td> 3rd-level cache: 16MByte, 16-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x4E </td><td> Cache </td><td> 2nd-level cache: 6MByte, 24-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x4F </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 32 entries</td></tr>\r
+ <tr><td> 0x50 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 64 entries</td></tr>\r
+ <tr><td> 0x51 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 128 entries</td></tr>\r
+ <tr><td> 0x52 </td><td> TLB </td><td> Instruction TLB: 4 KByte and 2-MByte or 4-MByte pages, 256 entries</td></tr>\r
+ <tr><td> 0x55 </td><td> TLB </td><td> Instruction TLB: 2-MByte or 4-MByte pages, fully associative, 7 entries</td></tr>\r
+ <tr><td> 0x56 </td><td> TLB </td><td> Data TLB0: 4 MByte pages, 4-way set associative, 16 entries</td></tr>\r
+ <tr><td> 0x57 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, 4-way associative, 16 entries</td></tr>\r
+ <tr><td> 0x59 </td><td> TLB </td><td> Data TLB0: 4 KByte pages, fully associative, 16 entries</td></tr>\r
+ <tr><td> 0x5A </td><td> TLB </td><td> Data TLB0: 2-MByte or 4 MByte pages, 4-way set associative, 32 entries</td></tr>\r
+ <tr><td> 0x5B </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 64 entries</td></tr>\r
+ <tr><td> 0x5C </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,128 entries</td></tr>\r
+ <tr><td> 0x5D </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages,256 entries</td></tr>\r
+ <tr><td> 0x60 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 8-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x61 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, fully associative, 48 entries</td></tr>\r
+ <tr><td> 0x63 </td><td> TLB </td><td> Data TLB: 1 GByte pages, 4-way set associative, 4 entries</td></tr>\r
+ <tr><td> 0x66 </td><td> Cache </td><td> 1st-level data cache: 8 KByte, 4-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x67 </td><td> Cache </td><td> 1st-level data cache: 16 KByte, 4-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x68 </td><td> Cache </td><td> 1st-level data cache: 32 KByte, 4-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x6A </td><td> Cache </td><td> uTLB: 4 KByte pages, 8-way set associative, 64 entries</td></tr>\r
+ <tr><td> 0x6B </td><td> Cache </td><td> DTLB: 4 KByte pages, 8-way set associative, 256 entries</td></tr>\r
+ <tr><td> 0x6C </td><td> Cache </td><td> DTLB: 2M/4M pages, 8-way set associative, 128 entries</td></tr>\r
+ <tr><td> 0x6D </td><td> Cache </td><td> DTLB: 1 GByte pages, fully associative, 16 entries</td></tr>\r
+ <tr><td> 0x70 </td><td> Cache </td><td> Trace cache: 12 K-uop, 8-way set associative</td></tr>\r
+ <tr><td> 0x71 </td><td> Cache </td><td> Trace cache: 16 K-uop, 8-way set associative</td></tr>\r
+ <tr><td> 0x72 </td><td> Cache </td><td> Trace cache: 32 K-uop, 8-way set associative</td></tr>\r
+ <tr><td> 0x76 </td><td> TLB </td><td> Instruction TLB: 2M/4M pages, fully associative, 8 entries</td></tr>\r
+ <tr><td> 0x78 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 4-way set associative, 64byte line size</td></tr>\r
+ <tr><td> 0x79 </td><td> Cache </td><td> 2nd-level cache: 128 KByte, 8-way set associative, 64 byte line size,\r
+ 2 lines per sector</td></tr>\r
+ <tr><td> 0x7A </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 64 byte line size,\r
+ 2 lines per sector</td></tr>\r
+ <tr><td> 0x7B </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64 byte line size,\r
+ 2 lines per sector</td></tr>\r
+ <tr><td> 0x7C </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size,\r
+ 2 lines per sector</td></tr>\r
+ <tr><td> 0x7D </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 64byte line size</td></tr>\r
+ <tr><td> 0x7F </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 2-way set associative, 64-byte line size</td></tr>\r
+ <tr><td> 0x80 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 64-byte line size</td></tr>\r
+ <tr><td> 0x82 </td><td> Cache </td><td> 2nd-level cache: 256 KByte, 8-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x83 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 8-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x84 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x85 </td><td> Cache </td><td> 2nd-level cache: 2 MByte, 8-way set associative, 32 byte line size</td></tr>\r
+ <tr><td> 0x86 </td><td> Cache </td><td> 2nd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0x87 </td><td> Cache </td><td> 2nd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xA0 </td><td> DTLB </td><td> DTLB: 4k pages, fully associative, 32 entries</td></tr>\r
+ <tr><td> 0xB0 </td><td> TLB </td><td> Instruction TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r
+ <tr><td> 0xB1 </td><td> TLB </td><td> Instruction TLB: 2M pages, 4-way, 8 entries or 4M pages, 4-way, 4 entries</td></tr>\r
+ <tr><td> 0xB2 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 4-way set associative, 64 entries</td></tr>\r
+ <tr><td> 0xB3 </td><td> TLB </td><td> Data TLB: 4 KByte pages, 4-way set associative, 128 entries</td></tr>\r
+ <tr><td> 0xB4 </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 256 entries</td></tr>\r
+ <tr><td> 0xB5 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative, 64 entries</td></tr>\r
+ <tr><td> 0xB6 </td><td> TLB </td><td> Instruction TLB: 4KByte pages, 8-way set associative,\r
+ 128 entries</td></tr>\r
+ <tr><td> 0xBA </td><td> TLB </td><td> Data TLB1: 4 KByte pages, 4-way associative, 64 entries</td></tr>\r
+ <tr><td> 0xC0 </td><td> TLB </td><td> Data TLB: 4 KByte and 4 MByte pages, 4-way associative, 8 entries</td></tr>\r
+ <tr><td> 0xC1 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte/2MByte pages, 8-way associative,\r
+ 1024 entries</td></tr>\r
+ <tr><td> 0xC2 </td><td> DTLB </td><td> DTLB: 4 KByte/2 MByte pages, 4-way associative, 16 entries</td></tr>\r
+ <tr><td> 0xC3 </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte /2 MByte pages, 6-way associative,\r
+ 1536 entries. Also 1GBbyte pages, 4-way, 16 entries.</td></tr>\r
+ <tr><td> 0xCA </td><td> STLB </td><td> Shared 2nd-Level TLB: 4 KByte pages, 4-way associative, 512 entries</td></tr>\r
+ <tr><td> 0xD0 </td><td> Cache </td><td> 3rd-level cache: 512 KByte, 4-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xD1 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 4-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xD2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 4-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xD6 </td><td> Cache </td><td> 3rd-level cache: 1 MByte, 8-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xD7 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 8-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xD8 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 8-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xDC </td><td> Cache </td><td> 3rd-level cache: 1.5 MByte, 12-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xDD </td><td> Cache </td><td> 3rd-level cache: 3 MByte, 12-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xDE </td><td> Cache </td><td> 3rd-level cache: 6 MByte, 12-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xE2 </td><td> Cache </td><td> 3rd-level cache: 2 MByte, 16-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xE3 </td><td> Cache </td><td> 3rd-level cache: 4 MByte, 16-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xE4 </td><td> Cache </td><td> 3rd-level cache: 8 MByte, 16-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xEA </td><td> Cache </td><td> 3rd-level cache: 12MByte, 24-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xEB </td><td> Cache </td><td> 3rd-level cache: 18MByte, 24-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xEC </td><td> Cache </td><td> 3rd-level cache: 24MByte, 24-way set associative, 64 byte line size</td></tr>\r
+ <tr><td> 0xF0 </td><td> Prefetch</td><td> 64-Byte prefetching</td></tr>\r
+ <tr><td> 0xF1 </td><td> Prefetch</td><td> 128-Byte prefetching</td></tr>\r
+ <tr><td> 0xFF </td><td> General </td><td> CPUID leaf 2 does not report cache descriptor information,\r
+ use CPUID leaf 4 to query cache parameters</td></tr>\r
+ </table>\r
+**/\r
+#define CPUID_CACHE_INFO 0x02\r
+\r
+/**\r
+ CPUID Cache and TLB Information returned in EAX, EBX, ECX, and EDX for CPUID\r
+ leaf #CPUID_CACHE_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved:31;\r
+ ///\r
+ /// [Bit 31] If 0, then the cache descriptor bytes in the register are valid.\r
+ /// if 1, then none of the cache descriptor bytes in the register are valid.\r
+ ///\r
+ UINT32 NotValid:1;\r
+ } Bits;\r
+ ///\r
+ /// Array of Cache and TLB descriptor bytes\r
+ ///\r
+ UINT8 CacheDescriptor[4];\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_CACHE_INFO_CACHE_TLB;\r
+\r
+\r
+/**\r
+ CPUID Processor Serial Number\r
+\r
+ Processor serial number (PSN) is not supported in the Pentium 4 processor\r
+ or later. On all models, use the PSN flag (returned using CPUID) to check\r
+ for PSN support before accessing the feature.\r
+\r
+ @param EAX CPUID_SERIAL_NUMBER (0x03)\r
+\r
+ @retval EAX Reserved.\r
+ @retval EBX Reserved.\r
+ @retval ECX Bits 31:0 of 96 bit processor serial number. (Available in\r
+ Pentium III processor only; otherwise, the value in this\r
+ register is reserved.)\r
+ @retval EDX Bits 63:32 of 96 bit processor serial number. (Available in\r
+ Pentium III processor only; otherwise, the value in this\r
+ register is reserved.)\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuid (CPUID_SERIAL_NUMBER, NULL, NULL, &Ecx, &Edx);\r
+ @endcode\r
+**/\r
+#define CPUID_SERIAL_NUMBER 0x03\r
+\r
+\r
+/**\r
+ CPUID Cache Parameters\r
+\r
+ @param EAX CPUID_CACHE_PARAMS (0x04)\r
+ @param ECX Cache Level. Valid values start at 0. Software can enumerate\r
+ the deterministic cache parameters for each level of the cache\r
+ hierarchy starting with an index value of 0, until the\r
+ parameters report the value associated with the CacheType\r
+ field in CPUID_CACHE_PARAMS_EAX is 0.\r
+\r
+ @retval EAX Returns cache type information described by the type\r
+ CPUID_CACHE_PARAMS_EAX.\r
+ @retval EBX Returns cache line and associativity information described by\r
+ the type CPUID_CACHE_PARAMS_EBX.\r
+ @retval ECX Returns the number of sets in the cache.\r
+ @retval EDX Returns cache WINVD/INVD behavior described by the type\r
+ CPUID_CACHE_PARAMS_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 CacheLevel;\r
+ CPUID_CACHE_PARAMS_EAX Eax;\r
+ CPUID_CACHE_PARAMS_EBX Ebx;\r
+ UINT32 Ecx;\r
+ CPUID_CACHE_PARAMS_EDX Edx;\r
+\r
+ CacheLevel = 0;\r
+ do {\r
+ AsmCpuidEx (\r
+ CPUID_CACHE_PARAMS, CacheLevel,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx, &Edx.Uint32\r
+ );\r
+ CacheLevel++;\r
+ } while (Eax.Bits.CacheType != CPUID_CACHE_PARAMS_CACHE_TYPE_NULL);\r
+ @endcode\r
+**/\r
+#define CPUID_CACHE_PARAMS 0x04\r
+\r
+/**\r
+ CPUID Cache Parameters Information returned in EAX for CPUID leaf\r
+ #CPUID_CACHE_PARAMS.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Cache type field. If #CPUID_CACHE_PARAMS_CACHE_TYPE_NULL,\r
+ /// then there is no information for the requested cache level.\r
+ ///\r
+ UINT32 CacheType:5;\r
+ ///\r
+ /// [Bits 7:5] Cache level (Starts at 1).\r
+ ///\r
+ UINT32 CacheLevel:3;\r
+ ///\r
+ /// [Bit 8] Self Initializing cache level (does not need SW initialization).\r
+ ///\r
+ UINT32 SelfInitializingCache:1;\r
+ ///\r
+ /// [Bit 9] Fully Associative cache.\r
+ ///\r
+ UINT32 FullyAssociativeCache:1;\r
+ ///\r
+ /// [Bits 13:10] Reserved.\r
+ ///\r
+ UINT32 Reserved:4;\r
+ ///\r
+ /// [Bits 25:14] Maximum number of addressable IDs for logical processors\r
+ /// sharing this cache.\r
+ ///\r
+ /// Add one to the return value to get the result.\r
+ /// The nearest power-of-2 integer that is not smaller than (1 + EAX[25:14])\r
+ /// is the number of unique initial APIC IDs reserved for addressing\r
+ /// different logical processors sharing this cache.\r
+ ///\r
+ UINT32 MaximumAddressableIdsForLogicalProcessors:12;\r
+ ///\r
+ /// [Bits 31:26] Maximum number of addressable IDs for processor cores in\r
+ /// the physical package.\r
+ ///\r
+ /// The nearest power-of-2 integer that is not smaller than (1 + EAX[31:26])\r
+ /// is the number of unique Core_IDs reserved for addressing different\r
+ /// processor cores in a physical package. Core ID is a subset of bits of\r
+ /// the initial APIC ID.\r
+ /// The returned value is constant for valid initial values in ECX. Valid\r
+ /// ECX values start from 0.\r
+ ///\r
+ UINT32 MaximumAddressableIdsForProcessorCores:6;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_CACHE_PARAMS_EAX;\r
+\r
+///\r
+/// @{ Define value for bit field CPUID_CACHE_PARAMS_EAX.CacheType\r
+///\r
+#define CPUID_CACHE_PARAMS_CACHE_TYPE_NULL 0x00\r
+#define CPUID_CACHE_PARAMS_CACHE_TYPE_DATA 0x01\r
+#define CPUID_CACHE_PARAMS_CACHE_TYPE_INSTRUCTION 0x02\r
+#define CPUID_CACHE_PARAMS_CACHE_TYPE_UNIFIED 0x03\r
+///\r
+/// @}\r
+///\r
+\r
+/**\r
+ CPUID Cache Parameters Information returned in EBX for CPUID leaf\r
+ #CPUID_CACHE_PARAMS.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 11:0] System Coherency Line Size. Add one to the return value to\r
+ /// get the result.\r
+ ///\r
+ UINT32 LineSize:12;\r
+ ///\r
+ /// [Bits 21:12] Physical Line Partitions. Add one to the return value to\r
+ /// get the result.\r
+ ///\r
+ UINT32 LinePartitions:10;\r
+ ///\r
+ /// [Bits 31:22] Ways of associativity. Add one to the return value to get\r
+ /// the result.\r
+ ///\r
+ UINT32 Ways:10;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_CACHE_PARAMS_EBX;\r
+\r
+/**\r
+ CPUID Cache Parameters Information returned in EDX for CPUID leaf\r
+ #CPUID_CACHE_PARAMS.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Write-Back Invalidate/Invalidate.\r
+ /// 0 = WBINVD/INVD from threads sharing this cache acts upon lower level\r
+ /// caches for threads sharing this cache.\r
+ /// 1 = WBINVD/INVD is not guaranteed to act upon lower level caches of\r
+ /// non-originating threads sharing this cache.\r
+ ///\r
+ UINT32 Invalidate:1;\r
+ ///\r
+ /// [Bit 1] Cache Inclusiveness.\r
+ /// 0 = Cache is not inclusive of lower cache levels.\r
+ /// 1 = Cache is inclusive of lower cache levels.\r
+ ///\r
+ UINT32 CacheInclusiveness:1;\r
+ ///\r
+ /// [Bit 2] Complex Cache Indexing.\r
+ /// 0 = Direct mapped cache.\r
+ /// 1 = A complex function is used to index the cache, potentially using all\r
+ /// address bits.\r
+ ///\r
+ UINT32 ComplexCacheIndexing:1;\r
+ UINT32 Reserved:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_CACHE_PARAMS_EDX;\r
+\r
+\r
+/**\r
+ CPUID MONITOR/MWAIT Information\r
+\r
+ @param EAX CPUID_MONITOR_MWAIT (0x05)\r
+\r
+ @retval EAX Smallest monitor-line size in bytes described by the type\r
+ CPUID_MONITOR_MWAIT_EAX.\r
+ @retval EBX Largest monitor-line size in bytes described by the type\r
+ CPUID_MONITOR_MWAIT_EBX.\r
+ @retval ECX Enumeration of Monitor-Mwait extensions support described by\r
+ the type CPUID_MONITOR_MWAIT_ECX.\r
+ @retval EDX Sub C-states supported described by the type\r
+ CPUID_MONITOR_MWAIT_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_MONITOR_MWAIT_EAX Eax;\r
+ CPUID_MONITOR_MWAIT_EBX Ebx;\r
+ CPUID_MONITOR_MWAIT_ECX Ecx;\r
+ CPUID_MONITOR_MWAIT_EDX Edx;\r
+\r
+ AsmCpuid (CPUID_MONITOR_MWAIT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
+ @endcode\r
+**/\r
+#define CPUID_MONITOR_MWAIT 0x05\r
+\r
+/**\r
+ CPUID MONITOR/MWAIT Information returned in EAX for CPUID leaf\r
+ #CPUID_MONITOR_MWAIT.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Smallest monitor-line size in bytes (default is processor's\r
+ /// monitor granularity).\r
+ ///\r
+ UINT32 SmallestMonitorLineSize:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MONITOR_MWAIT_EAX;\r
+\r
+/**\r
+ CPUID MONITOR/MWAIT Information returned in EBX for CPUID leaf\r
+ #CPUID_MONITOR_MWAIT.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Largest monitor-line size in bytes (default is processor's\r
+ /// monitor granularity).\r
+ ///\r
+ UINT32 LargestMonitorLineSize:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MONITOR_MWAIT_EBX;\r
+\r
+/**\r
+ CPUID MONITOR/MWAIT Information returned in ECX for CPUID leaf\r
+ #CPUID_MONITOR_MWAIT.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] If 0, then only EAX and EBX are valid. If 1, then EAX, EBX, ECX,\r
+ /// and EDX are valid.\r
+ ///\r
+ UINT32 ExtensionsSupported:1;\r
+ ///\r
+ /// [Bit 1] Supports treating interrupts as break-event for MWAIT, even when\r
+ /// interrupts disabled.\r
+ ///\r
+ UINT32 InterruptAsBreak:1;\r
+ UINT32 Reserved:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MONITOR_MWAIT_ECX;\r
+\r
+/**\r
+ CPUID MONITOR/MWAIT Information returned in EDX for CPUID leaf\r
+ #CPUID_MONITOR_MWAIT.\r
+\r
+ @note\r
+ The definition of C0 through C7 states for MWAIT extension are\r
+ processor-specific C-states, not ACPI C-states.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Number of C0 sub C-states supported using MWAIT.\r
+ ///\r
+ UINT32 C0States:4;\r
+ ///\r
+ /// [Bits 7:4] Number of C1 sub C-states supported using MWAIT.\r
+ ///\r
+ UINT32 C1States:4;\r
+ ///\r
+ /// [Bits 11:8] Number of C2 sub C-states supported using MWAIT.\r
+ ///\r
+ UINT32 C2States:4;\r
+ ///\r
+ /// [Bits 15:12] Number of C3 sub C-states supported using MWAIT.\r
+ ///\r
+ UINT32 C3States:4;\r
+ ///\r
+ /// [Bits 19:16] Number of C4 sub C-states supported using MWAIT.\r
+ ///\r
+ UINT32 C4States:4;\r
+ ///\r
+ /// [Bits 23:20] Number of C5 sub C-states supported using MWAIT.\r
+ ///\r
+ UINT32 C5States:4;\r
+ ///\r
+ /// [Bits 27:24] Number of C6 sub C-states supported using MWAIT.\r
+ ///\r
+ UINT32 C6States:4;\r
+ ///\r
+ /// [Bits 31:28] Number of C7 sub C-states supported using MWAIT.\r
+ ///\r
+ UINT32 C7States:4;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_MONITOR_MWAIT_EDX;\r
+\r
+\r
+/**\r
+ CPUID Thermal and Power Management\r
+\r
+ @param EAX CPUID_THERMAL_POWER_MANAGEMENT (0x06)\r
+\r
+ @retval EAX Thermal and power management features described by the type\r
+ CPUID_THERMAL_POWER_MANAGEMENT_EAX.\r
+ @retval EBX Number of Interrupt Thresholds in Digital Thermal Sensor\r
+ described by the type CPUID_THERMAL_POWER_MANAGEMENT_EBX.\r
+ @retval ECX Performance features described by the type\r
+ CPUID_THERMAL_POWER_MANAGEMENT_ECX.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_THERMAL_POWER_MANAGEMENT_EAX Eax;\r
+ CPUID_THERMAL_POWER_MANAGEMENT_EBX Ebx;\r
+ CPUID_THERMAL_POWER_MANAGEMENT_ECX Ecx;\r
+\r
+ AsmCpuid (CPUID_THERMAL_POWER_MANAGEMENT, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
+ @endcode\r
+**/\r
+#define CPUID_THERMAL_POWER_MANAGEMENT 0x06\r
+\r
+/**\r
+ CPUID Thermal and Power Management Information returned in EAX for CPUID leaf\r
+ #CPUID_THERMAL_POWER_MANAGEMENT.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Digital temperature sensor is supported if set.\r
+ ///\r
+ UINT32 DigitalTemperatureSensor:1;\r
+ ///\r
+ /// [Bit 1] Intel Turbo Boost Technology Available (see IA32_MISC_ENABLE[38]).\r
+ ///\r
+ UINT32 TurboBoostTechnology:1;\r
+ ///\r
+ /// [Bit 2] APIC-Timer-always-running feature is supported if set.\r
+ ///\r
+ UINT32 ARAT:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 4] Power limit notification controls are supported if set.\r
+ ///\r
+ UINT32 PLN:1;\r
+ ///\r
+ /// [Bit 5] Clock modulation duty cycle extension is supported if set.\r
+ ///\r
+ UINT32 ECMD:1;\r
+ ///\r
+ /// [Bit 6] Package thermal management is supported if set.\r
+ ///\r
+ UINT32 PTM:1;\r
+ ///\r
+ /// [Bit 7] HWP base registers (IA32_PM_ENABLE[Bit 0], IA32_HWP_CAPABILITIES,\r
+ /// IA32_HWP_REQUEST, IA32_HWP_STATUS) are supported if set.\r
+ ///\r
+ UINT32 HWP:1;\r
+ ///\r
+ /// [Bit 8] IA32_HWP_INTERRUPT MSR is supported if set.\r
+ ///\r
+ UINT32 HWP_Notification:1;\r
+ ///\r
+ /// [Bit 9] IA32_HWP_REQUEST[Bits 41:32] is supported if set.\r
+ ///\r
+ UINT32 HWP_Activity_Window:1;\r
+ ///\r
+ /// [Bit 10] IA32_HWP_REQUEST[Bits 31:24] is supported if set.\r
+ ///\r
+ UINT32 HWP_Energy_Performance_Preference:1;\r
+ ///\r
+ /// [Bit 11] IA32_HWP_REQUEST_PKG MSR is supported if set.\r
+ ///\r
+ UINT32 HWP_Package_Level_Request:1;\r
+ UINT32 Reserved2:1;\r
+ ///\r
+ /// [Bit 13] HDC base registers IA32_PKG_HDC_CTL, IA32_PM_CTL1,\r
+ /// IA32_THREAD_STALL MSRs are supported if set.\r
+ ///\r
+ UINT32 HDC:1;\r
+ UINT32 Reserved3:18;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_THERMAL_POWER_MANAGEMENT_EAX;\r
+\r
+/**\r
+ CPUID Thermal and Power Management Information returned in EBX for CPUID leaf\r
+ #CPUID_THERMAL_POWER_MANAGEMENT.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// {Bits 3:0] Number of Interrupt Thresholds in Digital Thermal Sensor.\r
+ ///\r
+ UINT32 InterruptThresholds:4;\r
+ UINT32 Reserved:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_THERMAL_POWER_MANAGEMENT_EBX;\r
+\r
+/**\r
+ CPUID Thermal and Power Management Information returned in ECX for CPUID leaf\r
+ #CPUID_THERMAL_POWER_MANAGEMENT.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Hardware Coordination Feedback Capability (Presence of IA32_MPERF\r
+ /// and IA32_APERF). The capability to provide a measure of delivered\r
+ /// processor performance (since last reset of the counters), as a percentage\r
+ /// of the expected processor performance when running at the TSC frequency.\r
+ ///\r
+ UINT32 HardwareCoordinationFeedback:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] If this bit is set, then the processor supports performance-energy\r
+ /// bias preference and the architectural MSR called IA32_ENERGY_PERF_BIAS\r
+ /// (1B0H).\r
+ ///\r
+ UINT32 PerformanceEnergyBias:1;\r
+ UINT32 Reserved2:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_THERMAL_POWER_MANAGEMENT_ECX;\r
+\r
+\r
+/**\r
+ CPUID Structured Extended Feature Flags Enumeration\r
+\r
+ @param EAX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS (0x07)\r
+ @param ECX CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO (0x00).\r
+\r
+ @note\r
+ If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r
+ index n is invalid if n exceeds the value that sub-leaf 0 returns in EAX.\r
+\r
+ @retval EAX The maximum input value for ECX to retrieve sub-leaf information.\r
+ @retval EBX Structured Extended Feature Flags described by the type\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX.\r
+ @retval EBX Structured Extended Feature Flags described by the type\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX Ebx;\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX Ecx;\r
+ UINT32 SubLeaf;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO,\r
+ &Eax, NULL, NULL, NULL\r
+ );\r
+ for (SubLeaf = 0; SubLeaf <= Eax; SubLeaf++) {\r
+ AsmCpuidEx (\r
+ CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS,\r
+ SubLeaf,\r
+ NULL, &Ebx.Uint32, &Ecx.Uint32, NULL\r
+ );\r
+ SubLeaf++;\r
+ } while (SubLeaf <= Eax);\r
+ @endcode\r
+**/\r
+#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS 0x07\r
+\r
+///\r
+/// CPUID Structured Extended Feature Flags Enumeration sub-leaf\r
+///\r
+#define CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO 0x00\r
+\r
+/**\r
+ CPUID Structured Extended Feature Flags Enumeration in EBX for CPUID leaf\r
+ #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r
+ #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Supports RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE if 1.\r
+ ///\r
+ UINT32 FSGSBASE:1;\r
+ ///\r
+ /// [Bit 1] IA32_TSC_ADJUST MSR is supported if 1.\r
+ ///\r
+ UINT32 IA32_TSC_ADJUST:1;\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 3] If 1 indicates the processor supports the first group of advanced\r
+ /// bit manipulation extensions (ANDN, BEXTR, BLSI, BLSMSK, BLSR, TZCNT)\r
+ ///\r
+ UINT32 BMI1:1;\r
+ ///\r
+ /// [Bit 4] Hardware Lock Elision\r
+ ///\r
+ UINT32 HLE:1;\r
+ ///\r
+ /// [Bit 5] If 1 indicates the processor supports AVX2 instruction extensions.\r
+ ///\r
+ UINT32 AVX2:1;\r
+ ///\r
+ /// [Bit 6] x87 FPU Data Pointer updated only on x87 exceptions if 1.\r
+ ///\r
+ UINT32 FDP_EXCPTN_ONLY:1;\r
+ ///\r
+ /// [Bit 7] Supports Supervisor-Mode Execution Prevention if 1.\r
+ ///\r
+ UINT32 SMEP:1;\r
+ ///\r
+ /// [Bit 8] If 1 indicates the processor supports the second group of\r
+ /// advanced bit manipulation extensions (BZHI, MULX, PDEP, PEXT, RORX,\r
+ /// SARX, SHLX, SHRX)\r
+ ///\r
+ UINT32 BMI2:1;\r
+ ///\r
+ /// [Bit 9] Supports Enhanced REP MOVSB/STOSB if 1.\r
+ ///\r
+ UINT32 EnhancedRepMovsbStosb:1;\r
+ ///\r
+ /// [Bit 10] If 1, supports INVPCID instruction for system software that\r
+ /// manages process-context identifiers.\r
+ ///\r
+ UINT32 INVPCID:1;\r
+ ///\r
+ /// [Bit 11] Restricted Transactional Memory\r
+ ///\r
+ UINT32 RTM:1;\r
+ ///\r
+ /// [Bit 12] Supports Platform Quality of Service Monitoring (PQM)\r
+ /// capability if 1.\r
+ ///\r
+ UINT32 PQM:1;\r
+ ///\r
+ /// [Bit 13] Deprecates FPU CS and FPU DS values if 1.\r
+ ///\r
+ UINT32 DeprecateFpuCsDs:1;\r
+ ///\r
+ /// [Bit 14] Supports Intel(R) Memory Protection Extensions if 1.\r
+ ///\r
+ UINT32 MPX:1;\r
+ ///\r
+ /// [Bit 15] Supports Platform Quality of Service Enforcement (PQE)\r
+ /// capability if 1.\r
+ ///\r
+ UINT32 PQE:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 18] If 1 indicates the processor supports the RDSEED instruction.\r
+ ///\r
+ UINT32 RDSEED:1;\r
+ ///\r
+ /// [Bit 19] If 1 indicates the processor supports the ADCX and ADOX\r
+ /// instructions.\r
+ ///\r
+ UINT32 ADX:1;\r
+ ///\r
+ /// [Bit 20] Supports Supervisor-Mode Access Prevention (and the CLAC/STAC\r
+ /// instructions) if 1.\r
+ ///\r
+ UINT32 SMAP:1;\r
+ UINT32 Reserved3:2;\r
+ ///\r
+ /// [Bit 23] If 1 indicates the processor supports the CLFLUSHOPT instruction.\r
+ ///\r
+ UINT32 CLFLUSHOPT:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 25] If 1 indicates the processor supports the Intel Processor Trace\r
+ /// extensions.\r
+ ///\r
+ UINT32 IntelProcessorTrace:1;\r
+ UINT32 Reserved5:6;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_EBX;\r
+\r
+/**\r
+ CPUID Structured Extended Feature Flags Enumeration in ECX for CPUID leaf\r
+ #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS sub leaf\r
+ #CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_SUB_LEAF_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] If 1 indicates the processor supports the PREFETCHWT1 instruction.\r
+ ///\r
+ UINT32 PREFETCHWT1:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Supports protection keys for user-mode pages if 1.\r
+ ///\r
+ UINT32 PKU:1;\r
+ ///\r
+ /// [Bit 4] If 1, OS has set CR4.PKE to enable protection keys (and the\r
+ /// RDPKRU/WRPKRU instructions).\r
+ ///\r
+ UINT32 OSPKE:1;\r
+ UINT32 Reserved2:27;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_STRUCTURED_EXTENDED_FEATURE_FLAGS_ECX;\r
+\r
+\r
+/**\r
+ CPUID Direct Cache Access Information\r
+\r
+ @param EAX CPUID_DIRECT_CACHE_ACCESS_INFO (0x09)\r
+\r
+ @retval EAX Value of bits [31:0] of IA32_PLATFORM_DCA_CAP MSR (address 1F8H).\r
+ @retval EBX Reserved.\r
+ @retval ECX Reserved.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+\r
+ AsmCpuid (CPUID_DIRECT_CACHE_ACCESS_INFO, &Eax, NULL, NULL, NULL);\r
+ @endcode\r
+**/\r
+#define CPUID_DIRECT_CACHE_ACCESS_INFO 0x09\r
+\r
+\r
+/**\r
+ CPUID Architectural Performance Monitoring\r
+\r
+ @param EAX CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING (0x0A)\r
+\r
+ @retval EAX Architectural Performance Monitoring information described by\r
+ the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX.\r
+ @retval EBX Architectural Performance Monitoring information described by\r
+ the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX.\r
+ @retval ECX Reserved.\r
+ @retval EDX Architectural Performance Monitoring information described by\r
+ the type CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX Eax;\r
+ CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX Ebx;\r
+ CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX Edx;\r
+\r
+ AsmCpuid (CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING, &Eax.Uint32, &Ebx.Uint32, NULL, &Edx.Uint32);\r
+ @endcode\r
+**/\r
+#define CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING 0x0A\r
+\r
+/**\r
+ CPUID Architectural Performance Monitoring EAX for CPUID leaf\r
+ #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 7:0] Version ID of architectural performance monitoring.\r
+ ///\r
+ UINT32 ArchPerfMonVerID:8;\r
+ ///\r
+ /// [Bits 15:8] Number of general-purpose performance monitoring counter\r
+ /// per logical processor.\r
+ ///\r
+ /// IA32_PERFEVTSELx MSRs start at address 186H and occupy a contiguous\r
+ /// block of MSR address space. Each performance event select register is\r
+ /// paired with a corresponding performance counter in the 0C1H address\r
+ /// block.\r
+ ///\r
+ UINT32 PerformanceMonitorCounters:8;\r
+ ///\r
+ /// [Bits 23:16] Bit width of general-purpose, performance monitoring counter.\r
+ ///\r
+ /// The bit width of an IA32_PMCx MSR. This the number of valid bits for\r
+ /// read operation. On write operations, the lower-order 32 bits of the MSR\r
+ /// may be written with any value, and the high-order bits are sign-extended\r
+ /// from the value of bit 31.\r
+ ///\r
+ UINT32 PerformanceMonitorCounterWidth:8;\r
+ ///\r
+ /// [Bits 31:24] Length of EBX bit vector to enumerate architectural\r
+ /// performance monitoring events.\r
+ ///\r
+ UINT32 EbxBitVectorLength:8;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EAX;\r
+\r
+/**\r
+ CPUID Architectural Performance Monitoring EBX for CPUID leaf\r
+ #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Core cycle event not available if 1.\r
+ ///\r
+ UINT32 UnhaltedCoreCycles:1;\r
+ ///\r
+ /// [Bit 1] Instruction retired event not available if 1.\r
+ ///\r
+ UINT32 InstructionsRetired:1;\r
+ ///\r
+ /// [Bit 2] Reference cycles event not available if 1.\r
+ ///\r
+ UINT32 UnhaltedReferenceCycles:1;\r
+ ///\r
+ /// [Bit 3] Last-level cache reference event not available if 1.\r
+ ///\r
+ UINT32 LastLevelCacheReferences:1;\r
+ ///\r
+ /// [Bit 4] Last-level cache misses event not available if 1.\r
+ ///\r
+ UINT32 LastLevelCacheMisses:1;\r
+ ///\r
+ /// [Bit 5] Branch instruction retired event not available if 1.\r
+ ///\r
+ UINT32 BranchInstructionsRetired:1;\r
+ ///\r
+ /// [Bit 6] Branch mispredict retired event not available if 1.\r
+ ///\r
+ UINT32 AllBranchMispredictRetired:1;\r
+ UINT32 Reserved:25;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EBX;\r
+\r
+/**\r
+ CPUID Architectural Performance Monitoring EDX for CPUID leaf\r
+ #CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Number of fixed-function performance counters\r
+ /// (if Version ID > 1).\r
+ ///\r
+ UINT32 FixedFunctionPerformanceCounters:5;\r
+ ///\r
+ /// [Bits 12:5] Bit width of fixed-function performance counters\r
+ /// (if Version ID > 1).\r
+ ///\r
+ UINT32 FixedFunctionPerformanceCounterWidth:8;\r
+ UINT32 Reserved:19;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_ARCHITECTURAL_PERFORMANCE_MONITORING_EDX;\r
+\r
+\r
+/**\r
+ CPUID Extended Topology Information\r
+\r
+ @note\r
+ Most of Leaf 0BH output depends on the initial value in ECX. The EDX output\r
+ of leaf 0BH is always valid and does not vary with input value in ECX. Output\r
+ value in ECX[7:0] always equals input value in ECX[7:0]. For sub-leaves that\r
+ return an invalid level-type of 0 in ECX[15:8]; EAX and EBX will return 0. If\r
+ an input value n in ECX returns the invalid level-type of 0 in ECX[15:8],\r
+ other input values with ECX > n also return 0 in ECX[15:8].\r
+\r
+ @param EAX CPUID_EXTENDED_TOPOLOGY (0x0B)\r
+ @param ECX Level number\r
+\r
+ @retval EAX Extended topology information described by the type\r
+ CPUID_EXTENDED_TOPOLOGY_EAX.\r
+ @retval EBX Extended topology information described by the type\r
+ CPUID_EXTENDED_TOPOLOGY_EBX.\r
+ @retval ECX Extended topology information described by the type\r
+ CPUID_EXTENDED_TOPOLOGY_ECX.\r
+ @retval EDX x2APIC ID the current logical processor.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_EXTENDED_TOPOLOGY_EAX Eax;\r
+ CPUID_EXTENDED_TOPOLOGY_EBX Ebx;\r
+ CPUID_EXTENDED_TOPOLOGY_ECX Ecx;\r
+ UINT32 Edx;\r
+ UINT32 LevelNumber;\r
+\r
+ LevelNumber = 0;\r
+ do {\r
+ AsmCpuidEx (\r
+ CPUID_EXTENDED_TOPOLOGY, LevelNumber,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx\r
+ );\r
+ LevelNumber++;\r
+ } while (Eax.Bits.ApicIdShift != 0);\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_TOPOLOGY 0x0B\r
+\r
+/**\r
+ CPUID Extended Topology Information EAX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 4:0] Number of bits to shift right on x2APIC ID to get a unique\r
+ /// topology ID of the next level type. All logical processors with the\r
+ /// same next level ID share current level.\r
+ ///\r
+ /// @note\r
+ /// Software should use this field (EAX[4:0]) to enumerate processor\r
+ /// topology of the system.\r
+ ///\r
+ UINT32 ApicIdShift:5;\r
+ UINT32 Reserved:27;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_TOPOLOGY_EAX;\r
+\r
+/**\r
+ CPUID Extended Topology Information EBX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Number of logical processors at this level type. The number\r
+ /// reflects configuration as shipped by Intel.\r
+ ///\r
+ /// @note\r
+ /// Software must not use EBX[15:0] to enumerate processor topology of the\r
+ /// system. This value in this field (EBX[15:0]) is only intended for\r
+ /// display/diagnostic purposes. The actual number of logical processors\r
+ /// available to BIOS/OS/Applications may be different from the value of\r
+ /// EBX[15:0], depending on software and platform hardware configurations.\r
+ ///\r
+ UINT32 LogicalProcessors:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_TOPOLOGY_EBX;\r
+\r
+/**\r
+ CPUID Extended Topology Information ECX for CPUID leaf #CPUID_EXTENDED_TOPOLOGY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Level number. Same value in ECX input.\r
+ ///\r
+ UINT32 LevelNumber:8;\r
+ ///\r
+ /// [Bits 15:8] Level type.\r
+ ///\r
+ /// @note\r
+ /// The value of the "level type" field is not related to level numbers in\r
+ /// any way, higher "level type" values do not mean higher levels.\r
+ ///\r
+ UINT32 LevelType:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_TOPOLOGY_ECX;\r
+\r
+///\r
+/// @{ Define value for CPUID_EXTENDED_TOPOLOGY_ECX.LevelType\r
+///\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x00\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x01\r
+#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x02\r
+///\r
+/// @}\r
+///\r
+\r
+\r
+/**\r
+ CPUID Extended State Information\r
+\r
+ @param EAX CPUID_EXTENDED_STATE (0x0D)\r
+ @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00).\r
+ CPUID_EXTENDED_STATE_SUB_LEAF (0x01).\r
+ CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02).\r
+ Sub leafs 2..n based on supported bits in XCR0 or IA32_XSS_MSR.\r
+**/\r
+#define CPUID_EXTENDED_STATE 0x0D\r
+\r
+/**\r
+ CPUID Extended State Information Main Leaf\r
+\r
+ @param EAX CPUID_EXTENDED_STATE (0x0D)\r
+ @param ECX CPUID_EXTENDED_STATE_MAIN_LEAF (0x00)\r
+\r
+ @retval EAX Reports the supported bits of the lower 32 bits of XCR0. XCR0[n]\r
+ can be set to 1 only if EAX[n] is 1. The format of the extended\r
+ state main leaf is described by the type\r
+ CPUID_EXTENDED_STATE_MAIN_LEAF_EAX.\r
+ @retval EBX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
+ area) required by enabled features in XCR0. May be different than\r
+ ECX if some features at the end of the XSAVE save area are not\r
+ enabled.\r
+ @retval ECX Maximum size (bytes, from the beginning of the XSAVE/XRSTOR save\r
+ area) of the XSAVE/XRSTOR save area required by all supported\r
+ features in the processor, i.e all the valid bit fields in XCR0.\r
+ @retval EDX Reports the supported bits of the upper 32 bits of XCR0.\r
+ XCR0[n+32] can be set to 1 only if EDX[n] is 1.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_EXTENDED_STATE_MAIN_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_MAIN_LEAF,\r
+ &Eax.Uint32, &Ebx, &Ecx, &Edx\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_STATE_MAIN_LEAF 0x00\r
+\r
+/**\r
+ CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
+ sub-leaf #CPUID_EXTENDED_STATE_MAIN_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] x87 state.\r
+ ///\r
+ UINT32 x87:1;\r
+ ///\r
+ /// [Bit 1] SSE state.\r
+ ///\r
+ UINT32 SSE:1;\r
+ ///\r
+ /// [Bit 2] AVX state.\r
+ ///\r
+ UINT32 AVX:1;\r
+ ///\r
+ /// [Bits 4:3] MPX state.\r
+ ///\r
+ UINT32 MPX:2;\r
+ ///\r
+ /// [Bits 7:5] AVX-512 state.\r
+ ///\r
+ UINT32 AVX_512:3;\r
+ ///\r
+ /// [Bit 8] Used for IA32_XSS.\r
+ ///\r
+ UINT32 IA32_XSS:1;\r
+ ///\r
+ /// [Bit 9] PKRU state.\r
+ ///\r
+ UINT32 PKRU:1;\r
+ UINT32 Reserved:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_STATE_MAIN_LEAF_EAX;\r
+\r
+/**\r
+ CPUID Extended State Information Sub Leaf\r
+\r
+ @param EAX CPUID_EXTENDED_STATE (0x0D)\r
+ @param ECX CPUID_EXTENDED_STATE_SUB_LEAF (0x01)\r
+\r
+ @retval EAX The format of the extended state sub-leaf is described by the\r
+ type CPUID_EXTENDED_STATE_SUB_LEAF_EAX.\r
+ @retval EBX The size in bytes of the XSAVE area containing all states\r
+ enabled by XCRO | IA32_XSS.\r
+ @retval ECX The format of the extended state sub-leaf is described by the\r
+ type CPUID_EXTENDED_STATE_SUB_LEAF_ECX.\r
+ @retval EDX Reports the supported bits of the upper 32 bits of the\r
+ IA32_XSS MSR. IA32_XSS[n+32] can be set to 1 only if EDX[n] is 1.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_EXTENDED_STATE_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_EXTENDED_STATE_SUB_LEAF_ECX Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_EXTENDED_STATE, CPUID_EXTENDED_STATE_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_STATE_SUB_LEAF 0x01\r
+\r
+/**\r
+ CPUID Extended State Information EAX for CPUID leaf #CPUID_EXTENDED_STATE,\r
+ sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] XSAVEOPT is available.\r
+ ///\r
+ UINT32 XSAVEOPT:1;\r
+ ///\r
+ /// [Bit 1] Supports XSAVEC and the compacted form of XRSTOR if set.\r
+ ///\r
+ UINT32 XSAVEC:1;\r
+ ///\r
+ /// [Bit 2] Supports XGETBV with ECX = 1 if set.\r
+ ///\r
+ UINT32 XGETBV:1;\r
+ ///\r
+ /// [Bit 3] Supports XSAVES/XRSTORS and IA32_XSS if set.\r
+ ///\r
+ UINT32 XSAVES:1;\r
+ UINT32 Reserved:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_STATE_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
+ sub-leaf #CPUID_EXTENDED_STATE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Used for XCR0.\r
+ ///\r
+ UINT32 XCR0:1;\r
+ ///\r
+ /// [Bit 8] PT STate.\r
+ ///\r
+ UINT32 PT:1;\r
+ ///\r
+ /// [Bit 9] Used for XCR0.\r
+ ///\r
+ UINT32 XCR0_1:1;\r
+ UINT32 Reserved:22;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_STATE_SUB_LEAF_ECX;\r
+\r
+/**\r
+ CPUID Extended State Information Size and Offset Sub Leaf\r
+\r
+ @note\r
+ Leaf 0DH output depends on the initial value in ECX.\r
+ Each sub-leaf index (starting at position 2) is supported if it corresponds to\r
+ a supported bit in either the XCR0 register or the IA32_XSS MSR.\r
+ If ECX contains an invalid sub-leaf index, EAX/EBX/ECX/EDX return 0. Sub-leaf\r
+ n (0 <= n <= 31) is invalid if sub-leaf 0 returns 0 in EAX[n] and sub-leaf 1\r
+ returns 0 in ECX[n]. Sub-leaf n (32 <= n <= 63) is invalid if sub-leaf 0\r
+ returns 0 in EDX[n-32] and sub-leaf 1 returns 0 in EDX[n-32].\r
+\r
+ @param EAX CPUID_EXTENDED_STATE (0x0D)\r
+ @param ECX CPUID_EXTENDED_STATE_SIZE_OFFSET (0x02). Sub leafs 2..n based\r
+ on supported bits in XCR0 or IA32_XSS_MSR.\r
+\r
+ @retval EAX The size in bytes (from the offset specified in EBX) of the save\r
+ area for an extended state feature associated with a valid\r
+ sub-leaf index, n.\r
+ @retval EBX The offset in bytes of this extended state component's save area\r
+ from the beginning of the XSAVE/XRSTOR area. This field reports\r
+ 0 if the sub-leaf index, n, does not map to a valid bit in the\r
+ XCR0 register.\r
+ @retval ECX The format of the extended state components's save area as\r
+ described by the type CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX.\r
+ This field reports 0 if the sub-leaf index, n, is invalid.\r
+ @retval EDX This field reports 0 if the sub-leaf index, n, is invalid;\r
+ otherwise it is reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+ CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX Ecx;\r
+ UINT32 Edx;\r
+ UINTN SubLeaf;\r
+\r
+ for (SubLeaf = CPUID_EXTENDED_STATE_SIZE_OFFSET; SubLeaf < 32; SubLeaf++) {\r
+ AsmCpuidEx (\r
+ CPUID_EXTENDED_STATE, SubLeaf,\r
+ &Eax, &Ebx, &Ecx.Uint32, &Edx\r
+ );\r
+ }\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_STATE_SIZE_OFFSET 0x02\r
+\r
+/**\r
+ CPUID Extended State Information ECX for CPUID leaf #CPUID_EXTENDED_STATE,\r
+ sub-leaf #CPUID_EXTENDED_STATE_SIZE_OFFSET.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Is set if the bit n (corresponding to the sub-leaf index) is\r
+ /// supported in the IA32_XSS MSR; it is clear if bit n is instead supported\r
+ /// in XCR0.\r
+ ///\r
+ UINT32 XSS:1;\r
+ ///\r
+ /// [Bit 1] is set if, when the compacted format of an XSAVE area is used,\r
+ /// this extended state component located on the next 64-byte boundary\r
+ /// following the preceding state component (otherwise, it is located\r
+ /// immediately following the preceding state component).\r
+ ///\r
+ UINT32 Compacted:1;\r
+ UINT32 Reserved:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_STATE_SIZE_OFFSET_ECX;\r
+\r
+\r
+/**\r
+ CPUID Platform QoS Monitoring Information\r
+\r
+ @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
+ @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00).\r
+ CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01).\r
+\r
+**/\r
+#define CPUID_PLATFORM_QOS_MONITORING 0x0F\r
+\r
+/**\r
+ CPUID Platform QoS Monitoring Information Enumeration Sub-leaf\r
+\r
+ @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
+ @param ECX CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF (0x00)\r
+\r
+ @retval EAX Reserved.\r
+ @retval EBX Maximum range (zero-based) of RMID within this physical\r
+ processor of all types.\r
+ @retval ECX Reserved.\r
+ @retval EDX L3 Cache QoS Monitoring Information Enumeration described by the\r
+ type CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Ebx;\r
+ CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF,\r
+ NULL, &Ebx, NULL, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF 0x00\r
+\r
+/**\r
+ CPUID Platform QoS Monitoring Information EDX for CPUID leaf\r
+ #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
+ #CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Supports L3 Cache QoS Monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheQosEnforcement:1;\r
+ UINT32 Reserved2:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PLATFORM_QOS_MONITORING_ENUMERATION_SUB_LEAF_EDX;\r
+\r
+/**\r
+ CPUID Platform QoS Monitoring Information Capability Sub-leaf\r
+\r
+ @param EAX CPUID_PLATFORM_QOS_MONITORING (0x0F)\r
+ @param ECX CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF (0x01)\r
+\r
+ @retval EAX Reserved.\r
+ @retval EBX Conversion factor from reported IA32_QM_CTR value to occupancy metric (bytes).\r
+ @retval ECX Maximum range (zero-based) of RMID of this resource type.\r
+ @retval EDX L3 Cache QoS Monitoring Capability information described by the\r
+ type CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Ebx;\r
+ UINT32 Ecx;\r
+ CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_PLATFORM_QOS_MONITORING, CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF,\r
+ NULL, &Ebx, &Ecx, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF 0x01\r
+\r
+/**\r
+ CPUID Platform QoS Monitoring Information Capability EDX for CPUID leaf\r
+ #CPUID_PLATFORM_QOS_MONITORING, sub-leaf\r
+ #CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Supports L3 occupancy monitoring if 1.\r
+ ///\r
+ UINT32 L3CacheOccupancyMonitoring:1;\r
+ UINT32 Reserved:31;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PLATFORM_QOS_MONITORING_CAPABILITY_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ CPUID Platform QoS Enforcement Information\r
+\r
+ @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10).\r
+ @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
+ CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x01).\r
+ Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
+**/\r
+#define CPUID_PLATFORM_QOS_ENFORCEMENT 0x10\r
+\r
+/**\r
+ CPUID Platform QoS Enforcement Information\r
+\r
+ @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
+ @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF (0x00).\r
+\r
+ @retval EAX Reserved.\r
+ @retval EBX L3 Cache QoS Enforcement information described by the\r
+ type CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX.\r
+ @retval ECX Reserved.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX Ebx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF,\r
+ NULL, &Ebx.Uint32, NULL, NULL\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF 0x00\r
+\r
+/**\r
+ CPUID Platform QoS Enforcement Information EBX for CPUID leaf\r
+ #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
+ #CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Supports L3 Cache QoS Enforcement if 1.\r
+ ///\r
+ UINT32 L3CacheQosEnforcement:1;\r
+ UINT32 Reserved2:30;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PLATFORM_QOS_ENFORCEMENT_MAIN_LEAF_EBX;\r
+\r
+\r
+/**\r
+ CPUID Platform QoS Enforcement Information\r
+\r
+ @param EAX CPUID_PLATFORM_QOS_ENFORCEMENT (0x10)\r
+ @param ECX CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF (0x00)\r
+ Additional sub leafs 1..n based in RESID from sub leaf 0x00.\r
+\r
+ @retval EAX RESID L3 Cache3 QoS Enforcement information described by the\r
+ type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX.\r
+ @retval EBX Bit-granular map of isolation/contention of allocation units.\r
+ @retval ECX RESID L3 Cache3 QoS Enforcement information described by the\r
+ type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX.\r
+ @retval EDX RESID L3 Cache3 QoS Enforcement information described by the\r
+ type CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX Eax;\r
+ UINT32 Ebx;\r
+ CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX Ecx;\r
+ CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_PLATFORM_QOS_ENFORCEMENT, CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF,\r
+ &Eax.Uint32, &Ebx, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF 0x01\r
+\r
+/**\r
+ CPUID Platform QoS Enforcement Information EAX for CPUID leaf\r
+ #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
+ #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 3:0] Length of the capacity bit mask for the corresponding ResID.\r
+ ///\r
+ UINT32 CapacityLength:4;\r
+ UINT32 Reserved:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID Platform QoS Enforcement Information ECX for CPUID leaf\r
+ #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
+ #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Updates of COS should be infrequent if 1.\r
+ ///\r
+ UINT32 CosUpdatesInfrequent:1;\r
+ ///\r
+ /// [Bit 2] Code and Data Prioritization Technology supported if 1.\r
+ ///\r
+ UINT32 CodeDataPrioritization:1;\r
+ UINT32 Reserved2:29;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_ECX;\r
+\r
+/**\r
+ CPUID Platform QoS Enforcement Information EDX for CPUID leaf\r
+ #CPUID_PLATFORM_QOS_ENFORCEMENT, sub-leaf\r
+ #CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Highest COS number supported for this ResID.\r
+ ///\r
+ UINT32 HighestCosNumber:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PLATFORM_QOS_ENFORCEMENT_RESID_SUB_LEAF_EDX;\r
+\r
+\r
+/**\r
+ CPUID Intel Processor Trace Information\r
+\r
+ @param EAX CPUID_INTEL_PROCESSOR_TRACE (0x14)\r
+ @param ECX CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF (0x00).\r
+ CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01).\r
+\r
+**/\r
+#define CPUID_INTEL_PROCESSOR_TRACE 0x14\r
+\r
+/**\r
+ CPUID Intel Processor Trace Information Main Leaf\r
+\r
+ @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r
+ @param ECX CPUID_INTEL_PROCEDSSOR_TRACE_MAIN_LEAF (0x00)\r
+\r
+ @retval EAX Reports the maximum sub-leaf supported in leaf 14H.\r
+ @retval EBX Returns Intel processor trace information described by the\r
+ type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX.\r
+ @retval ECX Returns Intel processor trace information described by the\r
+ type CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX Ebx;\r
+ CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX Ecx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
+ &Eax, &Ebx.Uint32, &Ecx.Uint32, NULL\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF 0x00\r
+\r
+/**\r
+ CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
+ sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] If 1, Indicates that IA32_RTIT_CTL.CR3Filter can be set to 1,\r
+ /// and that IA32_RTIT_CR3_MATCH MSR can be accessed.\r
+ ///\r
+ UINT32 Cr3Filter:1;\r
+ ///\r
+ /// [Bit 1] If 1, Indicates support of Configurable PSB and Cycle-Accurate\r
+ /// Mode.\r
+ ///\r
+ UINT32 ConfigurablePsb:1;\r
+ ///\r
+ /// [Bit 2] If 1, Indicates support of IP Filtering, TraceStop filtering,\r
+ /// and preservation of Intel PT MSRs across warm reset.\r
+ ///\r
+ UINT32 IpTraceStopFiltering:1;\r
+ ///\r
+ /// [Bit 3] If 1, Indicates support of MTC timing packet and suppression of\r
+ /// COFI-based packets.\r
+ ///\r
+ UINT32 Mtc:1;\r
+ UINT32 Reserved:28;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_EBX;\r
+\r
+/**\r
+ CPUID Intel Processor Trace ECX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
+ sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] If 1, Tracing can be enabled with IA32_RTIT_CTL.ToPA = 1, hence\r
+ /// utilizing the ToPA output scheme; IA32_RTIT_OUTPUT_BASE and\r
+ /// IA32_RTIT_OUTPUT_MASK_PTRS MSRs can be accessed.\r
+ ///\r
+ UINT32 RTIT:1;\r
+ ///\r
+ /// [Bit 1] If 1, ToPA tables can hold any number of output entries, up to\r
+ /// the maximum allowed by the MaskOrTableOffset field of\r
+ /// IA32_RTIT_OUTPUT_MASK_PTRS.\r
+ ///\r
+ UINT32 ToPA:1;\r
+ ///\r
+ /// [Bit 2] If 1, Indicates support of Single-Range Output scheme.\r
+ ///\r
+ UINT32 SingleRangeOutput:1;\r
+ ///\r
+ /// [Bit 3] If 1, Indicates support of output to Trace Transport subsystem.\r
+ ///\r
+ UINT32 TraceTransportSubsystem:1;\r
+ UINT32 Reserved:27;\r
+ ///\r
+ /// [Bit 31] If 1, Generated packets which contain IP payloads have LIP\r
+ /// values, which include the CS base component.\r
+ ///\r
+ UINT32 LIP:1;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF_ECX;\r
+\r
+\r
+/**\r
+ CPUID Intel Processor Trace Information Sub-leaf\r
+\r
+ @param EAX CPUID_INTEL_PROCEDSSOR_TRACE (0x14)\r
+ @param ECX CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF (0x01)\r
+\r
+ @retval EAX Returns Intel processor trace information described by the\r
+ type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX.\r
+ @retval EBX Returns Intel processor trace information described by the\r
+ type CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX.\r
+ @retval ECX Reserved.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 MaximumSubLeaf;\r
+ UINT32 SubLeaf;\r
+ CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX Eax;\r
+ CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX Ebx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_PROCESSOR_TRACE, CPUID_INTEL_PROCESSOR_TRACE_MAIN_LEAF,\r
+ &MaximumSubLeaf, NULL, NULL, NULL\r
+ );\r
+\r
+ for (SubLeaf = CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF; SubLeaf <= MaximumSubLeaf; SubLeaf++) {\r
+ AsmCpuidEx (\r
+ CPUID_INTEL_PROCESSOR_TRACE, SubLeaf,\r
+ &Eax.Uint32, &Ebx.Uint32, NULL, NULL\r
+ );\r
+ }\r
+ @endcode\r
+**/\r
+#define CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF 0x01\r
+\r
+/**\r
+ CPUID Intel Processor Trace EAX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
+ sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] Number of configurable Address Ranges for filtering.\r
+ ///\r
+ UINT32 ConfigurableAddressRanges:3;\r
+ UINT32 Reserved:13;\r
+ ///\r
+ /// [Bits 31:16] Bitmap of supported MTC period encodings\r
+ ///\r
+ UINT32 MtcPeriodEncodings:16;\r
+\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EAX;\r
+\r
+/**\r
+ CPUID Intel Processor Trace EBX for CPUID leaf #CPUID_INTEL_PROCESSOR_TRACE,\r
+ sub-leaf #CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Bitmap of supported Cycle Threshold value encodings.\r
+ ///\r
+ UINT32 CycleThresholdEncodings:16;\r
+ ///\r
+ /// [Bits 31:16] Bitmap of supported Configurable PSB frequency encodings.\r
+ ///\r
+ UINT32 PsbFrequencyEncodings:16;\r
+\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_INTEL_PROCESSOR_TRACE_SUB_LEAF_EBX;\r
+\r
+\r
+/**\r
+ CPUID Time Stamp Counter Information\r
+\r
+ @note\r
+ If EBX[31:0] is 0, the TSC/"core crystal clock" ratio is not enumerated.\r
+ EBX[31:0]/EAX[31:0] indicates the ratio of the TSC frequency and the core\r
+ crystal clock frequency.\r
+ "TSC frequency" = "core crystal clock frequency" * EBX/EAX.\r
+ The core crystal clock may differ from the reference clock, bus clock, or core\r
+ clock frequencies.\r
+\r
+ @param EAX CPUID_TIME_STAMP_COUNTER (0x15)\r
+\r
+ @retval EAX An unsigned integer which is the denominator of the\r
+ TSC/"core crystal clock" ratio\r
+ @retval EBX An unsigned integer which is the numerator of the\r
+ TSC/"core crystal clock" ratio.\r
+ @retval ECX Reserved.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ UINT32 Ebx;\r
+\r
+ AsmCpuid (CPUID_TIME_STAMP_COUNTER, &Eax, &Ebx, NULL, NULL);\r
+ @endcode\r
+**/\r
+#define CPUID_TIME_STAMP_COUNTER 0x15\r
+\r
+\r
+/**\r
+ CPUID Processor Frequency Information\r
+\r
+ @note\r
+ Data is returned from this interface in accordance with the processor's\r
+ specification and does not reflect actual values. Suitable use of this data\r
+ includes the display of processor information in like manner to the processor\r
+ brand string and for determining the appropriate range to use when displaying\r
+ processor information e.g. frequency history graphs. The returned information\r
+ should not be used for any other purpose as the returned information does not\r
+ accurately correlate to information / counters returned by other processor\r
+ interfaces. While a processor may support the Processor Frequency Information\r
+ leaf, fields that return a value of zero are not supported.\r
+\r
+ @param EAX CPUID_TIME_STAMP_COUNTER (0x16)\r
+\r
+ @retval EAX Returns processor base frequency information described by the\r
+ type CPUID_PROCESSOR_FREQUENCY_EAX.\r
+ @retval EBX Returns maximum frequency information described by the type\r
+ CPUID_PROCESSOR_FREQUENCY_EBX.\r
+ @retval ECX Returns bus frequency information described by the type\r
+ CPUID_PROCESSOR_FREQUENCY_ECX.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_PROCESSOR_FREQUENCY_EAX Eax;\r
+ CPUID_PROCESSOR_FREQUENCY_EBX Ebx;\r
+ CPUID_PROCESSOR_FREQUENCY_ECX Ecx;\r
+\r
+ AsmCpuid (CPUID_PROCESSOR_FREQUENCY, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, NULL);\r
+ @endcode\r
+**/\r
+#define CPUID_PROCESSOR_FREQUENCY 0x16\r
+\r
+/**\r
+ CPUID Processor Frequency Information EAX for CPUID leaf\r
+ #CPUID_PROCESSOR_FREQUENCY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Processor Base Frequency (in MHz).\r
+ ///\r
+ UINT32 ProcessorBaseFrequency:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PROCESSOR_FREQUENCY_EAX;\r
+\r
+/**\r
+ CPUID Processor Frequency Information EBX for CPUID leaf\r
+ #CPUID_PROCESSOR_FREQUENCY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Maximum Frequency (in MHz).\r
+ ///\r
+ UINT32 MaximumFrequency:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PROCESSOR_FREQUENCY_EBX;\r
+\r
+/**\r
+ CPUID Processor Frequency Information ECX for CPUID leaf\r
+ #CPUID_PROCESSOR_FREQUENCY.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Bus (Reference) Frequency (in MHz).\r
+ ///\r
+ UINT32 BusFrequency:16;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_PROCESSOR_FREQUENCY_ECX;\r
+\r
\r
-#define CPUID_VERSION_INFO 0x1\r
+/**\r
+ CPUID SoC Vendor Information\r
\r
-#define CPUID_CACHE_INFO 0x2\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r
+ CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r
+ CPUID_SOC_VENDOR_BRAND_STRING1 (0x02)\r
+ CPUID_SOC_VENDOR_BRAND_STRING1 (0x03)\r
\r
-#define CPUID_SERIAL_NUMBER 0x3\r
+ @note\r
+ Leaf 17H output depends on the initial value in ECX. SOC Vendor Brand String\r
+ is a UTF-8 encoded string padded with trailing bytes of 00H. The complete SOC\r
+ Vendor Brand String is constructed by concatenating in ascending order of\r
+ EAX:EBX:ECX:EDX and from the sub-leaf 1 fragment towards sub-leaf 3.\r
\r
-#define CPUID_CACHE_PARAMS 0x4\r
+**/\r
+#define CPUID_SOC_VENDOR 0x17\r
+\r
+/**\r
+ CPUID SoC Vendor Information\r
+\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_MAIN_LEAF (0x00)\r
+\r
+ @retval EAX MaxSOCID_Index. Reports the maximum input value of supported\r
+ sub-leaf in leaf 17H.\r
+ @retval EBX Returns SoC Vendor information described by the type\r
+ CPUID_SOC_VENDOR_MAIN_LEAF_EBX.\r
+ @retval ECX Project ID. A unique number an SOC vendor assigns to its SOC\r
+ projects.\r
+ @retval EDX Stepping ID. A unique number within an SOC project that an SOC\r
+ vendor assigns.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ CPUID_SOC_VENDOR_MAIN_LEAF_EBX Ebx;\r
+ UINT32 Ecx;\r
+ UINT32 Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_MAIN_LEAF,\r
+ &Eax, &Ebx.Uint32, &Ecx, &Edx\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_SOC_VENDOR_MAIN_LEAF 0x00\r
+\r
+/**\r
+ CPUID SoC Vendor Information EBX for CPUID leaf #CPUID_SOC_VENDOR sub-leaf\r
+ #CPUID_SOC_VENDOR_MAIN_LEAF.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] SOC Vendor ID.\r
+ ///\r
+ UINT32 SocVendorId:16;\r
+ ///\r
+ /// [Bit 16] If 1, the SOC Vendor ID field is assigned via an industry\r
+ /// standard enumeration scheme. Otherwise, the SOC Vendor ID field is\r
+ /// assigned by Intel.\r
+ ///\r
+ UINT32 IsVendorScheme:1;\r
+ UINT32 Reserved:15;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_SOC_VENDOR_MAIN_LEAF_EBX;\r
+\r
+/**\r
+ CPUID SoC Vendor Information\r
+\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_BRAND_STRING1 (0x01)\r
+\r
+ @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING1,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_SOC_VENDOR_BRAND_STRING1 0x01\r
+\r
+/**\r
+ CPUID SoC Vendor Brand String for CPUID leafs #CPUID_SOC_VENDOR_BRAND_STRING1,\r
+ #CPUID_SOC_VENDOR_BRAND_STRING2, and #CPUID_SOC_VENDOR_BRAND_STRING3.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// 4 UTF-8 characters of Soc Vendor Brand String\r
+ ///\r
+ CHAR8 BrandString[4];\r
+ ///\r
+ /// All fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_SOC_VENDOR_BRAND_STRING_DATA;\r
+\r
+/**\r
+ CPUID SoC Vendor Information\r
+\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_BRAND_STRING2 (0x02)\r
+\r
+ @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING2,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_SOC_VENDOR_BRAND_STRING2 0x02\r
+\r
+/**\r
+ CPUID SoC Vendor Information\r
+\r
+ @param EAX CPUID_SOC_VENDOR (0x17)\r
+ @param ECX CPUID_SOC_VENDOR_BRAND_STRING3 (0x03)\r
\r
-#define CPUID_MONITOR_MWAIT 0x5\r
+ @retval EAX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EBX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval ECX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+ @retval EDX SOC Vendor Brand String. UTF-8 encoded string of type\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Eax;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ebx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Ecx;\r
+ CPUID_SOC_VENDOR_BRAND_STRING_DATA Edx;\r
+\r
+ AsmCpuidEx (\r
+ CPUID_SOC_VENDOR, CPUID_SOC_VENDOR_BRAND_STRING3,\r
+ &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32\r
+ );\r
+ @endcode\r
+**/\r
+#define CPUID_SOC_VENDOR_BRAND_STRING3 0x03\r
\r
-#define CPUID_EXTENDED_TOPOLOGY 0xB\r
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_INVALID 0x0\r
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_SMT 0x1\r
-#define CPUID_EXTENDED_TOPOLOGY_LEVEL_TYPE_CORE 0x2\r
\r
+/**\r
+ CPUID Extended Function\r
+\r
+ @param EAX CPUID_EXTENDED_FUNCTION (0x80000000)\r
+\r
+ @retval EAX Maximum Input Value for Extended Function CPUID Information.\r
+ @retval EBX Reserved.\r
+ @retval ECX Reserved.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+\r
+ AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);\r
+ @endcode\r
+**/\r
#define CPUID_EXTENDED_FUNCTION 0x80000000\r
\r
+\r
+/**\r
+ CPUID Extended Processor Signature and Feature Bits\r
+\r
+ @param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)\r
+\r
+ @retval EAX CPUID_EXTENDED_CPU_SIG.\r
+ @retval EBX Reserved.\r
+ @retval ECX Extended Processor Signature and Feature Bits information\r
+ described by the type CPUID_EXTENDED_CPU_SIG_ECX.\r
+ @retval EDX Extended Processor Signature and Feature Bits information\r
+ described by the type CPUID_EXTENDED_CPU_SIG_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT32 Eax;\r
+ CPUID_EXTENDED_CPU_SIG_ECX Ecx;\r
+ CPUID_EXTENDED_CPU_SIG_EDX Edx;\r
+\r
+ AsmCpuid (CPUID_EXTENDED_CPU_SIG, &Eax, NULL, &Ecx.Uint32, &Edx.Uint32);\r
+ @endcode\r
+**/\r
#define CPUID_EXTENDED_CPU_SIG 0x80000001\r
\r
+/**\r
+ CPUID Extended Processor Signature and Feature Bits ECX for CPUID leaf\r
+ #CPUID_EXTENDED_CPU_SIG.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] LAHF/SAHF available in 64-bit mode.\r
+ ///\r
+ UINT32 LAHF_SAHF:1;\r
+ UINT32 Reserved1:4;\r
+ ///\r
+ /// [Bit 5] LZCNT.\r
+ ///\r
+ UINT32 LZCNT:1;\r
+ UINT32 Reserved2:2;\r
+ ///\r
+ /// [Bit 8] PREFETCHW.\r
+ ///\r
+ UINT32 PREFETCHW:1;\r
+ UINT32 Reserved3:23;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_CPU_SIG_ECX;\r
+\r
+/**\r
+ CPUID Extended Processor Signature and Feature Bits EDX for CPUID leaf\r
+ #CPUID_EXTENDED_CPU_SIG.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:11;\r
+ ///\r
+ /// [Bit 11] SYSCALL/SYSRET available in 64-bit mode.\r
+ ///\r
+ UINT32 SYSCALL_SYSRET:1;\r
+ UINT32 Reserved2:8;\r
+ ///\r
+ /// [Bit 20] Execute Disable Bit available.\r
+ ///\r
+ UINT32 NX:1;\r
+ UINT32 Reserved3:5;\r
+ ///\r
+ /// [Bit 26] 1-GByte pages are available if 1.\r
+ ///\r
+ UINT32 Page1GB:1;\r
+ ///\r
+ /// [Bit 27] RDTSCP and IA32_TSC_AUX are available if 1.\r
+ ///\r
+ UINT32 RDTSCP:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 29] Intel(R) 64 Architecture available if 1.\r
+ ///\r
+ UINT32 LM:1;\r
+ UINT32 Reserved5:2;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_CPU_SIG_EDX;\r
+\r
+\r
+/**\r
+ CPUID Processor Brand String\r
+\r
+ @param EAX CPUID_BRAND_STRING1 (0x80000002)\r
+\r
+ @retval EAX Processor Brand String in type CPUID_BRAND_STRING_DATA.\r
+ @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+ @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+ @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_BRAND_STRING_DATA Eax;\r
+ CPUID_BRAND_STRING_DATA Ebx;\r
+ CPUID_BRAND_STRING_DATA Ecx;\r
+ CPUID_BRAND_STRING_DATA Edx;\r
+\r
+ AsmCpuid (CPUID_BRAND_STRING1, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
+ @endcode\r
+**/\r
#define CPUID_BRAND_STRING1 0x80000002\r
\r
+/**\r
+ CPUID Processor Brand String for CPUID leafs #CPUID_BRAND_STRING1,\r
+ #CPUID_BRAND_STRING2, and #CPUID_BRAND_STRING3.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// 4 ASCII characters of Processor Brand String\r
+ ///\r
+ CHAR8 BrandString[4];\r
+ ///\r
+ /// All fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_BRAND_STRING_DATA;\r
+\r
+/**\r
+ CPUID Processor Brand String\r
+\r
+ @param EAX CPUID_BRAND_STRING2 (0x80000003)\r
+\r
+ @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+ @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+ @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+ @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_BRAND_STRING_DATA Eax;\r
+ CPUID_BRAND_STRING_DATA Ebx;\r
+ CPUID_BRAND_STRING_DATA Ecx;\r
+ CPUID_BRAND_STRING_DATA Edx;\r
+\r
+ AsmCpuid (CPUID_BRAND_STRING2, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
+ @endcode\r
+**/\r
#define CPUID_BRAND_STRING2 0x80000003\r
\r
+/**\r
+ CPUID Processor Brand String\r
+\r
+ @param EAX CPUID_BRAND_STRING3 (0x80000004)\r
+\r
+ @retval EAX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+ @retval EBX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+ @retval ECX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+ @retval EDX Processor Brand String Continued in type CPUID_BRAND_STRING_DATA.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_BRAND_STRING_DATA Eax;\r
+ CPUID_BRAND_STRING_DATA Ebx;\r
+ CPUID_BRAND_STRING_DATA Ecx;\r
+ CPUID_BRAND_STRING_DATA Edx;\r
+\r
+ AsmCpuid (CPUID_BRAND_STRING3, &Eax.Uint32, &Ebx.Uint32, &Ecx.Uint32, &Edx.Uint32);\r
+ @endcode\r
+**/\r
#define CPUID_BRAND_STRING3 0x80000004\r
\r
+\r
+/**\r
+ CPUID Extended Cache information\r
+\r
+ @param EAX CPUID_EXTENDED_CACHE_INFO (0x80000006)\r
+\r
+ @retval EAX Reserved.\r
+ @retval EBX Reserved.\r
+ @retval ECX Extended cache information described by the type\r
+ CPUID_EXTENDED_CACHE_INFO_ECX.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_EXTENDED_CACHE_INFO_ECX Ecx;\r
+\r
+ AsmCpuid (CPUID_EXTENDED_CACHE_INFO, NULL, NULL, &Ecx.Uint32, NULL);\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_CACHE_INFO 0x80000006\r
+\r
+/**\r
+ CPUID Extended Cache information ECX for CPUID leaf #CPUID_EXTENDED_CACHE_INFO.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Cache line size in bytes.\r
+ ///\r
+ UINT32 CacheLineSize:8;\r
+ UINT32 Reserved:4;\r
+ ///\r
+ /// [Bits 15:12] L2 Associativity field. Supported values are in the range\r
+ /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED to\r
+ /// #CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL\r
+ ///\r
+ UINT32 L2Associativity:4;\r
+ ///\r
+ /// [Bits 31:16] Cache size in 1K units.\r
+ ///\r
+ UINT32 CacheSize:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_CACHE_INFO_ECX;\r
+\r
+///\r
+/// @{ Define value for bit field CPUID_EXTENDED_CACHE_INFO_ECX.L2Associativity\r
+///\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DISABLED 0x00\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_DIRECT_MAPPED 0x01\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_2_WAY 0x02\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_4_WAY 0x04\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_8_WAY 0x06\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_16_WAY 0x08\r
+#define CPUID_EXTENDED_CACHE_INFO_ECX_L2_ASSOCIATIVITY_FULL 0x0F\r
+///\r
+/// @}\r
+///\r
+\r
+/**\r
+ CPUID Extended Time Stamp Counter information\r
+\r
+ @param EAX CPUID_EXTENDED_TIME_STAMP_COUNTER (0x80000007)\r
+\r
+ @retval EAX Reserved.\r
+ @retval EBX Reserved.\r
+ @retval ECX Reserved.\r
+ @retval EDX Extended time stamp counter (TSC) information described by the\r
+ type CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX Edx;\r
+\r
+ AsmCpuid (CPUID_EXTENDED_TIME_STAMP_COUNTER, NULL, NULL, NULL, &Edx.Uint32);\r
+ @endcode\r
+**/\r
+#define CPUID_EXTENDED_TIME_STAMP_COUNTER 0x80000007\r
+\r
+/**\r
+ CPUID Extended Time Stamp Counter information EDX for CPUID leaf\r
+ #CPUID_EXTENDED_TIME_STAMP_COUNTER.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bit 8] Invariant TSC available if 1.\r
+ ///\r
+ UINT32 InvariantTsc:1;\r
+ UINT32 Reserved2:23;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_EXTENDED_TIME_STAMP_COUNTER_EDX;\r
+\r
+\r
+/**\r
+ CPUID Linear Physical Address Size\r
+\r
+ @param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)\r
+\r
+ @retval EAX Linear/Physical Address Size described by the type\r
+ CPUID_VIR_PHY_ADDRESS_SIZE_EAX.\r
+ @retval EBX Reserved.\r
+ @retval ECX Reserved.\r
+ @retval EDX Reserved.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ CPUID_VIR_PHY_ADDRESS_SIZE_EAX Eax;\r
+\r
+ AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Eax.Uint32, NULL, NULL, NULL);\r
+ @endcode\r
+**/\r
#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
\r
+/**\r
+ CPUID Linear Physical Address Size EAX for CPUID leaf\r
+ #CPUID_VIR_PHY_ADDRESS_SIZE.\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 7:0] Number of physical address bits.\r
+ ///\r
+ /// @note\r
+ /// If CPUID.80000008H:EAX[7:0] is supported, the maximum physical address\r
+ /// number supported should come from this field.\r
+ ///\r
+ UINT32 PhysicalAddressBits:8;\r
+ ///\r
+ /// [Bits 15:8] Number of linear address bits.\r
+ ///\r
+ UINT32 LinearAddressBits:8;\r
+ UINT32 Reserved:16;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+} CPUID_VIR_PHY_ADDRESS_SIZE_EAX;\r
+\r
#endif\r
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