UefiCpuPkg/PiSmmCpuDxeSmm: patch "gSmmInitStack" with PatchInstructionX86()

Rename the variable to "gPatchSmmInitStack" so that its association with
PatchInstructionX86() is clear from the declaration, change its type to
X86_ASSEMBLY_PATCH_LABEL, and patch it with PatchInstructionX86(). This
lets us remove the binary (DB) encoding of some instructions in
"SmmInit.nasm".

The size of the patched source operand is (sizeof (UINTN)).

Cc: Eric Dong <eric.dong@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=866
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Liming Gao <liming.gao@intel.com>

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
index f59413d9d4a3cce37a77fb2405b954f48b599793..5ff3cd2e731fb142fc2d1a5a5fdb13ef405c3e9c 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/Ia32/SmmInit.nasm
@@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 global ASM_PFX(gPatchSmmCr3)\r
 global ASM_PFX(gPatchSmmCr4)\r
 global ASM_PFX(gPatchSmmCr0)\r
-global ASM_PFX(gSmmInitStack)\r
+global ASM_PFX(gPatchSmmInitStack)\r
 global ASM_PFX(gcSmiInitGdtr)\r
 global ASM_PFX(gcSmmInitSize)\r
 global ASM_PFX(gcSmmInitTemplate)\r
@@ -72,8 +72,8 @@ BITS 32
     mov     fs, edi\r
     mov     gs, edi\r
     mov     ss, edi\r
-    DB      0xbc                        ; mov esp, imm32\r
-ASM_PFX(gSmmInitStack): DD 0\r
+    mov     esp, strict dword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmInitStack):\r
     call    ASM_PFX(SmmInitHandler)\r
     rsm\r
 \r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
index 0c8a4543d8651794fbeb7f38ff869b3670a71237..fbf74e8d90f953cea4cd69da3bccadd1c6dcc609 100755 (executable)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
@@ -848,7 +848,11 @@ PiCpuSmmEntry (
   //\r
   // Set SMI stack for SMM base relocation\r
   //\r
-  gSmmInitStack = (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN));\r
+  PatchInstructionX86 (\r
+    gPatchSmmInitStack,\r
+    (UINTN) (Stacks + mSmmStackSize - sizeof (UINTN)),\r
+    sizeof (UINTN)\r
+    );\r
 \r
   //\r
   // Initialize IDT\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
index d897d4353e104f4963fb2778dca23385b81535f8..1d016594e026365e0621dc5badd2291e085ea02a 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
@@ -302,7 +302,7 @@ extern UINT32                       mSmmCr0;
 X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr3;\r
 extern UINT32                       mSmmCr4;\r
 X86_ASSEMBLY_PATCH_LABEL            gPatchSmmCr4;\r
-extern UINTN                        gSmmInitStack;\r
+X86_ASSEMBLY_PATCH_LABEL            gPatchSmmInitStack;\r
 \r
 /**\r
   Semaphore operation for all processor relocate SMMBase.\r

diff --git a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
index 2460e1eb2dee91d2e0388ffe32044d7ebad0b471..eae14c0549f0d9a04a7d59bfe113845f62232ea2 100644 (file)
--- a/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
+++ b/UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmInit.nasm
@@ -25,7 +25,7 @@ extern ASM_PFX(mSmmRelocationOriginalAddress)
 global ASM_PFX(gPatchSmmCr3)\r
 global ASM_PFX(gPatchSmmCr4)\r
 global ASM_PFX(gPatchSmmCr0)\r
-global ASM_PFX(gSmmInitStack)\r
+global ASM_PFX(gPatchSmmInitStack)\r
 global ASM_PFX(gcSmiInitGdtr)\r
 global ASM_PFX(gcSmmInitSize)\r
 global ASM_PFX(gcSmmInitTemplate)\r
@@ -72,8 +72,8 @@ ASM_PFX(gPatchSmmCr0):
 \r
 BITS 64\r
 @LongMode:                              ; long-mode starts here\r
-    DB      0x48, 0xbc                   ; mov rsp, imm64\r
-ASM_PFX(gSmmInitStack): DQ 0\r
+    mov     rsp, strict qword 0         ; source operand will be patched\r
+ASM_PFX(gPatchSmmInitStack):\r
     and     sp, 0xfff0                  ; make sure RSP is 16-byte aligned\r
     ;\r
     ; Accoring to X64 calling convention, XMM0~5 are volatile, we need to save\r