MdeModulePkg/Core/DxeIplPeim: Add support for PCD PcdPteMemoryEncryptionAddressOrMask
authorLeo Duran <leo.duran@amd.com>
Sun, 26 Feb 2017 17:43:03 +0000 (01:43 +0800)
committerStar Zeng <star.zeng@intel.com>
Wed, 1 Mar 2017 04:51:01 +0000 (12:51 +0800)
This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when creating page tables.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
MdeModulePkg/Core/DxeIplPeim/Ia32/DxeLoadFunc.c
MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h

index 2bc41be..d62bd9b 100644 (file)
@@ -6,6 +6,8 @@
 #  needed to run the DXE Foundation.\r
 #\r
 #  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+#  Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+#\r
 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #  which accompanies this distribution.  The full text of the license may be found at\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSupportUefiDecompress ## CONSUMES\r
 \r
 [Pcd.IA32,Pcd.X64]\r
-  gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable              ## SOMETIMES_CONSUMES\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdUse1GPageTable                      ## SOMETIMES_CONSUMES\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask    ## CONSUMES\r
 \r
 [Pcd.IA32,Pcd.X64,Pcd.ARM,Pcd.AARCH64]\r
   gEfiMdeModulePkgTokenSpaceGuid.PcdSetNxForStack               ## SOMETIMES_CONSUMES\r
index 8f6a97a..1957326 100644 (file)
@@ -2,6 +2,8 @@
   Ia32-specific functionality for DxeLoad.\r
 \r
 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -82,6 +84,12 @@ Create4GPageTablesIa32Pae (
   PAGE_TABLE_ENTRY                              *PageDirectoryEntry;\r
   UINTN                                         TotalPagesNum;\r
   UINTN                                         PageAddress;\r
+  UINT64                                        AddressEncMask;\r
+\r
+  //\r
+  // Make sure AddressEncMask is contained to smallest supported address field\r
+  //\r
+  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
 \r
   PhysicalAddressBits = 32;\r
 \r
@@ -111,7 +119,7 @@ Create4GPageTablesIa32Pae (
     //\r
     // Fill in a Page Directory Pointer Entries\r
     //\r
-    PageDirectoryPointerEntry->Uint64 = (UINT64) (UINTN) PageDirectoryEntry;\r
+    PageDirectoryPointerEntry->Uint64 = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask;\r
     PageDirectoryPointerEntry->Bits.Present = 1;\r
 \r
     for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress += SIZE_2MB) {\r
@@ -124,7 +132,7 @@ Create4GPageTablesIa32Pae (
         //\r
         // Fill in the Page Directory entries\r
         //\r
-        PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress;\r
+        PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress | AddressEncMask;\r
         PageDirectoryEntry->Bits.ReadWrite = 1;\r
         PageDirectoryEntry->Bits.Present = 1;\r
         PageDirectoryEntry->Bits.MustBe1 = 1;\r
index 790f6ab..48150be 100644 (file)
@@ -16,6 +16,8 @@
     3) IA-32 Intel(R) Architecture Software Developer's Manual Volume 3:System Programmer's Guide, Intel\r
 \r
 Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -29,6 +31,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 #include "DxeIpl.h"\r
 #include "VirtualMemory.h"\r
 \r
+\r
 /**\r
   Enable Execute Disable Bit.\r
 \r
@@ -65,20 +68,27 @@ Split2MPageTo4K (
   EFI_PHYSICAL_ADDRESS                  PhysicalAddress4K;\r
   UINTN                                 IndexOfPageTableEntries;\r
   PAGE_TABLE_4K_ENTRY                   *PageTableEntry;\r
+  UINT64                                AddressEncMask;\r
+\r
+  //\r
+  // Make sure AddressEncMask is contained to smallest supported address field\r
+  //\r
+  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
 \r
   PageTableEntry = AllocatePages (1);\r
   ASSERT (PageTableEntry != NULL);\r
+\r
   //\r
   // Fill in 2M page entry.\r
   //\r
-  *PageEntry2M = (UINT64) (UINTN) PageTableEntry | IA32_PG_P | IA32_PG_RW;\r
+  *PageEntry2M = (UINT64) (UINTN) PageTableEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;\r
 \r
   PhysicalAddress4K = PhysicalAddress;\r
   for (IndexOfPageTableEntries = 0; IndexOfPageTableEntries < 512; IndexOfPageTableEntries++, PageTableEntry++, PhysicalAddress4K += SIZE_4KB) {\r
     //\r
     // Fill in the Page Table entries\r
     //\r
-    PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K;\r
+    PageTableEntry->Uint64 = (UINT64) PhysicalAddress4K | AddressEncMask;\r
     PageTableEntry->Bits.ReadWrite = 1;\r
     PageTableEntry->Bits.Present = 1;\r
     if ((PhysicalAddress4K >= StackBase) && (PhysicalAddress4K < StackBase + StackSize)) {\r
@@ -110,13 +120,20 @@ Split1GPageTo2M (
   EFI_PHYSICAL_ADDRESS                  PhysicalAddress2M;\r
   UINTN                                 IndexOfPageDirectoryEntries;\r
   PAGE_TABLE_ENTRY                      *PageDirectoryEntry;\r
+  UINT64                                AddressEncMask;\r
+\r
+  //\r
+  // Make sure AddressEncMask is contained to smallest supported address field\r
+  //\r
+  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
 \r
   PageDirectoryEntry = AllocatePages (1);\r
   ASSERT (PageDirectoryEntry != NULL);\r
+\r
   //\r
   // Fill in 1G page entry.\r
   //\r
-  *PageEntry1G = (UINT64) (UINTN) PageDirectoryEntry | IA32_PG_P | IA32_PG_RW;\r
+  *PageEntry1G = (UINT64) (UINTN) PageDirectoryEntry | AddressEncMask | IA32_PG_P | IA32_PG_RW;\r
 \r
   PhysicalAddress2M = PhysicalAddress;\r
   for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PhysicalAddress2M += SIZE_2MB) {\r
@@ -129,7 +146,7 @@ Split1GPageTo2M (
       //\r
       // Fill in the Page Directory entries\r
       //\r
-      PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress2M;\r
+      PageDirectoryEntry->Uint64 = (UINT64) PhysicalAddress2M | AddressEncMask;\r
       PageDirectoryEntry->Bits.ReadWrite = 1;\r
       PageDirectoryEntry->Bits.Present = 1;\r
       PageDirectoryEntry->Bits.MustBe1 = 1;\r
@@ -171,6 +188,12 @@ CreateIdentityMappingPageTables (
   VOID                                          *Hob;\r
   BOOLEAN                                       Page1GSupport;\r
   PAGE_TABLE_1G_ENTRY                           *PageDirectory1GEntry;\r
+  UINT64                                        AddressEncMask;\r
+\r
+  //\r
+  // Make sure AddressEncMask is contained to smallest supported address field\r
+  //\r
+  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
 \r
   Page1GSupport = FALSE;\r
   if (PcdGetBool(PcdUse1GPageTable)) {\r
@@ -248,7 +271,7 @@ CreateIdentityMappingPageTables (
     //\r
     // Make a PML4 Entry\r
     //\r
-    PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry;\r
+    PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;\r
     PageMapLevel4Entry->Bits.ReadWrite = 1;\r
     PageMapLevel4Entry->Bits.Present = 1;\r
 \r
@@ -262,7 +285,7 @@ CreateIdentityMappingPageTables (
           //\r
           // Fill in the Page Directory entries\r
           //\r
-          PageDirectory1GEntry->Uint64 = (UINT64)PageAddress;\r
+          PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r
           PageDirectory1GEntry->Bits.ReadWrite = 1;\r
           PageDirectory1GEntry->Bits.Present = 1;\r
           PageDirectory1GEntry->Bits.MustBe1 = 1;\r
@@ -280,7 +303,7 @@ CreateIdentityMappingPageTables (
         //\r
         // Fill in a Page Directory Pointer Entries\r
         //\r
-        PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry;\r
+        PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;\r
         PageDirectoryPointerEntry->Bits.ReadWrite = 1;\r
         PageDirectoryPointerEntry->Bits.Present = 1;\r
 \r
@@ -294,7 +317,7 @@ CreateIdentityMappingPageTables (
             //\r
             // Fill in the Page Directory entries\r
             //\r
-            PageDirectoryEntry->Uint64 = (UINT64)PageAddress;\r
+            PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;\r
             PageDirectoryEntry->Bits.ReadWrite = 1;\r
             PageDirectoryEntry->Bits.Present = 1;\r
             PageDirectoryEntry->Bits.MustBe1 = 1;\r
index 20c31f5..7c9bb49 100644 (file)
@@ -8,6 +8,8 @@
     4) AMD64 Architecture Programmer's Manual Volume 2: System Programming\r
 \r
 Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r
+Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r
 This program and the accompanying materials\r
 are licensed and made available under the terms and conditions of the BSD License\r
 which accompanies this distribution.  The full text of the license may be found at\r
@@ -23,6 +25,7 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
 \r
 #define SYS_CODE64_SEL 0x38\r
 \r
+\r
 #pragma pack(1)\r
 \r
 typedef union {\r
@@ -148,6 +151,8 @@ typedef union {
 #define IA32_PG_P                   BIT0\r
 #define IA32_PG_RW                  BIT1\r
 \r
+#define PAGING_1G_ADDRESS_MASK_64   0x000FFFFFC0000000ull\r
+\r
 /**\r
   Enable Execute Disable Bit.\r
 \r