--- /dev/null
+/** @file\r
+* Main file supporting the SEC Phase on ARM PLatforms\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+*\r
+* This program and the accompanying materials\r
+* are licensed and made available under the terms and conditions of the BSD License\r
+* which accompanies this distribution. The full text of the license may be found at\r
+* http://opensource.org/licenses/bsd-license.php\r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+*\r
+**/\r
+\r
+#ifndef __SEC_H__\r
+#define __SEC_H__\r
+\r
+#include <Base.h>\r
+#include <Library/BaseLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#include <Chipset/ArmV7.h>\r
+\r
+#define IS_ALIGNED(Address, Align) (((UINTN)Address & (Align-1)) == 0)\r
+\r
+VOID\r
+ArmSetupGicNonSecure (\r
+ IN INTN GicDistributorBase,\r
+ IN INTN GicInterruptInterfaceBase\r
+);\r
+\r
+// Vector Table for Sec Phase\r
+VOID\r
+SecVectorTable (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+NonSecureWaitForFirmware (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+enter_monitor_mode (\r
+ IN VOID* Stack\r
+ );\r
+\r
+VOID\r
+return_from_exception (\r
+ IN UINTN NonSecureBase\r
+ );\r
+\r
+VOID\r
+copy_cpsr_into_spsr (\r
+ VOID\r
+ );\r
+\r
+VOID\r
+SecCommonExceptionEntry (\r
+ IN UINT32 Entry,\r
+ IN UINT32 LR\r
+ );\r
+\r
+#endif\r