// Flow through, same behavior as Host Controller Reset
//
case EFI_USB_HC_RESET_HOST_CONTROLLER:
+ if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {
+ Status = EFI_SUCCESS;
+ goto ON_EXIT;
+ }
//
// Host Controller must be Halt when Reset it
//
ExtCapReg = (UINT16) (Xhc->HcCParams.Data.ExtCapReg);
Xhc->ExtCapRegBase = ExtCapReg << 2;
- Xhc->UsbLegSupOffset = XhcGetLegSupCapAddr (Xhc);
+ Xhc->UsbLegSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_LEGACY);
+ Xhc->DebugCapSupOffset = XhcGetCapabilityAddr (Xhc, XHC_CAP_USB_DEBUG);
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: Capability length 0x%x\n", Xhc->CapLength));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: HcSParams1 0x%x\n", Xhc->HcSParams1));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DBOff 0x%x\n", Xhc->DBOff));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: RTSOff 0x%x\n", Xhc->RTSOff));
DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: UsbLegSupOffset 0x%x\n", Xhc->UsbLegSupOffset));
+ DEBUG ((EFI_D_INFO, "XhcCreateUsb3Hc: DebugCapSupOffset 0x%x\n", Xhc->DebugCapSupOffset));
//
// Create AsyncRequest Polling Timer
UINTN *ScratchEntryMap;\r
UINT32 ExtCapRegBase;\r
UINT32 UsbLegSupOffset;\r
+ UINT32 DebugCapSupOffset;\r
UINT64 *DCBAA;\r
VOID *DCBAAMap;\r
UINT32 MaxSlotsEn;\r
}\r
\r
/**\r
- Calculate the XHCI legacy support capability register offset.\r
+ Calculate the offset of the XHCI capability.\r
\r
@param Xhc The XHCI Instance.\r
+ @param CapId The XHCI Capability ID.\r
\r
@return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
-XhcGetLegSupCapAddr (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+XhcGetCapabilityAddr (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 CapId\r
)\r
{\r
UINT32 ExtCapOffset;\r
// Check if the extended capability register's capability id is USB Legacy Support.\r
//\r
Data = XhcReadExtCapReg (Xhc, ExtCapOffset);\r
- if ((Data & 0xFF) == 0x1) {\r
+ if ((Data & 0xFF) == CapId) {\r
return ExtCapOffset;\r
}\r
//\r
{\r
EFI_STATUS Status;\r
\r
+ Status = EFI_SUCCESS;\r
+\r
DEBUG ((EFI_D_INFO, "XhcResetHC!\n"));\r
//\r
// Host can only be reset when it is halt. If not so, halt it\r
}\r
}\r
\r
- XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
- Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+ if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||\r
+ ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {\r
+ XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r
+ Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r
+ }\r
+\r
return Status;\r
}\r
\r
#define USB_HUB_CLASS_CODE 0x09\r
#define USB_HUB_SUBCLASS_CODE 0x00\r
\r
+#define XHC_CAP_USB_LEGACY 0x01\r
+#define XHC_CAP_USB_DEBUG 0x0A\r
+\r
//============================================//\r
// XHCI register offset //\r
//============================================//\r
#define XHC_ERSTBA_OFFSET 0x30 // Event Ring Segment Table Base Address Register Offset\r
#define XHC_ERDP_OFFSET 0x38 // Event Ring Dequeue Pointer Register Offset\r
\r
+//\r
+// Debug registers offset\r
+//\r
+#define XHC_DC_DCCTRL 0x20\r
+\r
#define USBLEGSP_BIOS_SEMAPHORE BIT16 // HC BIOS Owned Semaphore\r
#define USBLEGSP_OS_SEMAPHORE BIT24 // HC OS Owned Semaphore\r
\r
IN UINT32 Bit\r
);\r
\r
+/**\r
+ Read XHCI extended capability register.\r
+\r
+ @param Xhc The XHCI Instance.\r
+ @param Offset The offset of the extended capability register.\r
+\r
+ @return The register content read\r
+\r
+**/\r
+UINT32\r
+XhcReadExtCapReg (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT32 Offset\r
+ );\r
+\r
/**\r
Whether the XHCI host controller is halted.\r
\r
);\r
\r
/**\r
- Calculate the XHCI legacy support capability register offset.\r
+ Calculate the offset of the XHCI capability.\r
\r
@param Xhc The XHCI Instance.\r
+ @param CapId The XHCI Capability ID.\r
\r
@return The offset of XHCI legacy support capability register.\r
\r
**/\r
UINT32\r
-XhcGetLegSupCapAddr (\r
- IN USB_XHCI_INSTANCE *Xhc\r
+XhcGetCapabilityAddr (\r
+ IN USB_XHCI_INSTANCE *Xhc,\r
+ IN UINT8 CapId\r
);\r
\r
#endif\r