Add dual FSP binaries support.

There are two FSP images at different locations in a flash (one factory version is read only and other in updatable version)
TempRamInit, FspMemoryInit and TempRamExit are executed from factory version and FspSiliconInit/NotifyPhase will be executed from updatable version.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: "Ma, Maurice" <maurice.ma@intel.com>
Reviewed-by: "Yao, Jiewen" <Jiewen.Yao@intel.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17249 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/IntelFspWrapperPkg/FspInitPei/FspInitPei.inf b/IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
index 97e88138bd504ad05c2428449ee02e76e7337445..cde101b907dd8174e82171fd22036761fe3289d9 100644 (file)
--- a/IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
+++ b/IntelFspWrapperPkg/FspInitPei/FspInitPei.inf
@@ -81,6 +81,7 @@
 [Pcd]\r
   gFspWrapperTokenSpaceGuid.PcdPeiTemporaryRamStackSize       ## CONSUMES\r
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase                 ## CONSUMES\r
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase           ## CONSUMES\r
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize                 ## CONSUMES\r
   gFspWrapperTokenSpaceGuid.PcdMaxUpdRegionSize               ## CONSUMES\r
   gFspWrapperTokenSpaceGuid.PcdFspApiVersion                  ## CONSUMES\r

diff --git a/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c b/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c
index f11015e993f6c2a7a67647f8ba6f88d6c978eaee..35a994e9608cc1b52cae9a03103f997405b2821b 100644 (file)
--- a/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c
+++ b/IntelFspWrapperPkg/FspInitPei/FspInitPeiV2.c
@@ -261,7 +261,11 @@ PeiMemoryDiscoveredNotify (
   VOID                      *FspHobList;\r
   EFI_HOB_GUID_TYPE         *GuidHob;\r
 \r
-  FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));\r
+  if (PcdGet32 (PcdFlashFvSecondFspBase) == 0) {\r
+    FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));\r
+  } else {\r
+    FspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvSecondFspBase));\r
+  }\r
   if (FspHeader == NULL) {\r
     return EFI_DEVICE_ERROR;\r
   }\r

diff --git a/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.c b/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.c
index 859b26728d7c51852363b66bfdc7794e139b8575..f8e8e826f135a3491b087cb7e97d53ba6b4a094a 100644 (file)
--- a/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.c
+++ b/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.c
@@ -120,7 +120,11 @@ FspDxeEntryPoint (
   VOID       *Registration;\r
   EFI_EVENT  ProtocolNotifyEvent;\r
 \r
-  mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));\r
+  if (PcdGet32 (PcdFlashFvSecondFspBase) == 0) {\r
+    mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvFspBase));\r
+  } else {\r
+    mFspHeader = FspFindFspHeader (PcdGet32 (PcdFlashFvSecondFspBase));\r
+  }\r
   DEBUG ((DEBUG_INFO, "FspHeader - 0x%x\n", mFspHeader));\r
   if (mFspHeader == NULL) {\r
     return EFI_DEVICE_ERROR;\r

diff --git a/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf b/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
index 3b819d9bb9d891e32c0101a7bada39789e3181ec..8175dbd3245ece440a4672f760248c663c25ac7a 100644 (file)
--- a/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
+++ b/IntelFspWrapperPkg/FspNotifyDxe/FspNotifyDxe.inf
@@ -49,6 +49,7 @@
 \r
 [Pcd]\r
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase       ## CONSUMES\r
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase ## CONSUMES\r
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize       ## CONSUMES\r
 \r
 [Depex]\r

diff --git a/IntelFspWrapperPkg/IntelFspWrapperPkg.dec b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec
index bfed1cc97aec8b9c67ccbbfbbb3453ba4983a895..1fc8e2c48426e4a53b043b736128e032352b2e53 100644 (file)
--- a/IntelFspWrapperPkg/IntelFspWrapperPkg.dec
+++ b/IntelFspWrapperPkg/IntelFspWrapperPkg.dec
@@ -59,10 +59,22 @@
   ## Provides the size of the BIOS Flash Device.\r
   gFspWrapperTokenSpaceGuid.PcdFlashCodeCacheSize|0x00200000|UINT32|0x10000002\r
 \r
-  ## Indicates the base address of the FSP binary.\r
+  ## Indicates the base address of the factory FSP binary.\r
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspBase|0xFFF80000|UINT32|0x10000003\r
-  ## Provides the size of the FSP binary.\r
+  ## Indicates the base address of the updatable FSP binary to support Dual FSP.\r
+  #  There could be two FSP images at different locations in a flash - \r
+  #  one factory version (default) and updatable version (updatable).\r
+  #  TempRamInit, FspMemoryInit and TempRamExit are always executed from factory version.\r
+  #  FspSiliconInit and NotifyPhase can be executed from updatable version if it is available,\r
+  #  FspSiliconInit and NotifyPhase are executed from factory version if there is no updateable version,\r
+  #  PcdFlashFvFspBase is base address of factory FSP, and PcdFlashFvSecondFspBase\r
+  #  is base address of updatable FSP. If PcdFlashFvSecondFspBase is 0, that means\r
+  #  there is no updatable FSP.\r
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspBase|0x00000000|UINT32|0x10000008\r
+  ## Provides the size of the factory FSP binary.\r
   gFspWrapperTokenSpaceGuid.PcdFlashFvFspSize|0x00048000|UINT32|0x10000004\r
+  ## Provides the size of the updatable FSP binary to support Dual FSP.\r
+  gFspWrapperTokenSpaceGuid.PcdFlashFvSecondFspSize|0x00000000|UINT32|0x10000009\r
 \r
   ## Indicates the base address of the first Microcode Patch in the Microcode Region\r
   gFspWrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress|0x0|UINT64|0x10000005\r