--- /dev/null
+/** @file\r
+ Provide common routines used by BasePciSegmentLibSegmentInfo and\r
+ DxeRuntimePciSegmentLibSegmentInfo libraries.\r
+\r
+ Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials are\r
+ licensed and made available under the terms and conditions of\r
+ the BSD License which accompanies this distribution. The full\r
+ text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php.\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include "PciSegmentLibCommon.h"\r
+\r
+typedef struct {\r
+ UINT64 Register : 12;\r
+ UINT64 Function : 3;\r
+ UINT64 Device : 5;\r
+ UINT64 Bus : 8;\r
+ UINT64 Reserved1 : 4;\r
+ UINT64 Segment : 16;\r
+ UINT64 Reserved2 : 16;\r
+} PCI_SEGMENT_LIB_ADDRESS_STRUCTURE;\r
+\r
+/**\r
+ Internal function that converts PciSegmentLib format address that encodes the PCI Bus, Device,\r
+ Function and Register to ECAM (Enhanced Configuration Access Mechanism) address.\r
+\r
+ @param Address The address that encodes the PCI Bus, Device, Function and\r
+ Register.\r
+ @param SegmentInfo An array of PCI_SEGMENT_INFO holding the segment information.\r
+ @param Count Number of segments.\r
+\r
+ @retval ECAM address.\r
+**/\r
+UINTN\r
+PciSegmentLibGetEcamAddress (\r
+ IN UINT64 Address,\r
+ IN CONST PCI_SEGMENT_INFO *SegmentInfo,\r
+ IN UINTN Count\r
+ )\r
+{\r
+ while (Count != 0) {\r
+ if (SegmentInfo->SegmentNumber == ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Segment) {\r
+ break;\r
+ }\r
+ SegmentInfo++;\r
+ Count--;\r
+ }\r
+ ASSERT (Count != 0);\r
+ ASSERT (\r
+ (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved1 == 0) &&\r
+ (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Reserved2 == 0)\r
+ );\r
+ ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus >= SegmentInfo->StartBusNumber);\r
+ ASSERT (((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus <= SegmentInfo->EndBusNumber);\r
+\r
+ Address = SegmentInfo->BaseAddress + PCI_ECAM_ADDRESS (\r
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Bus,\r
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Device,\r
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Function,\r
+ ((PCI_SEGMENT_LIB_ADDRESS_STRUCTURE *)&Address)->Register);\r
+\r
+ if (sizeof (UINTN) == sizeof (UINT32)) {\r
+ ASSERT (Address < BASE_4GB);\r
+ }\r
+\r
+ return PciSegmentLibVirtualAddress ((UINTN)Address);\r
+}\r
+\r
+/**\r
+ Reads an 8-bit PCI configuration register.\r
+\r
+ Reads and returns the 8-bit PCI configuration register specified by Address.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+\r
+ @return The 8-bit PCI configuration register specified by Address.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentRead8 (\r
+ IN UINT64 Address\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));\r
+}\r
+\r
+/**\r
+ Writes an 8-bit PCI configuration register.\r
+\r
+ Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Value The value to write.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentWrite8 (\r
+ IN UINT64 Address,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);\r
+}\r
+\r
+/**\r
+ Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
+ and writes the result to the 8-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentOr8 (\r
+ IN UINT64 Address,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ and writes the result to the 8-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+ If any reserved bits in Address are set, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentAnd8 (\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioAnd8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
+ followed a bitwise OR with another 8-bit value.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 8-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentAndThenOr8 (\r
+ IN UINT64 Address,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of a PCI configuration register.\r
+\r
+ Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+\r
+ @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentBitFieldRead8 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldRead8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a PCI configuration register.\r
+\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 8-bit register is returned.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentBitFieldWrite8 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 Value\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldWrite8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 8-bit port.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 8-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentBitFieldOr8 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 8-bit register.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 8-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentBitFieldAnd8 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the 8-bit port.\r
+\r
+ Reads the 8-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 8-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If StartBit is greater than 7, then ASSERT().\r
+ If EndBit is greater than 7, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..7.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..7.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT8\r
+EFIAPI\r
+PciSegmentBitFieldAndThenOr8 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT8 AndData,\r
+ IN UINT8 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldAndThenOr8 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a 16-bit PCI configuration register.\r
+\r
+ Reads and returns the 16-bit PCI configuration register specified by Address.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+\r
+ @return The 16-bit PCI configuration register specified by Address.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentRead16 (\r
+ IN UINT64 Address\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));\r
+}\r
+\r
+/**\r
+ Writes a 16-bit PCI configuration register.\r
+\r
+ Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Value The value to write.\r
+\r
+ @return The parameter of Value.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentWrite16 (\r
+ IN UINT64 Address,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);\r
+}\r
+\r
+/**\r
+ Performs a bitwise OR of a 16-bit PCI configuration register with\r
+ a 16-bit value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by OrData, and\r
+ writes the result to the 16-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned. This function\r
+ must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r
+ Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentOr16 (\r
+ IN UINT64 Address,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ and writes the result to the 16-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentAnd16 (\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioAnd16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
+ followed a bitwise OR with another 16-bit value.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 16-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentAndThenOr16 (\r
+ IN UINT64 Address,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of a PCI configuration register.\r
+\r
+ Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+\r
+ @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentBitFieldRead16 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldRead16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a PCI configuration register.\r
+\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 16-bit register is returned.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentBitFieldWrite16 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 Value\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldWrite16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r
+ the result back to the bit field in the 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 16-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentBitFieldOr16 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
+ AND, writes the result back to the bit field in the 16-bit register.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND between the read result and the value specified by AndData, and\r
+ writes the result to the 16-bit PCI configuration register specified by\r
+ Address. The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are\r
+ serialized. Extra left bits in AndData are stripped.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 16-bit boundary, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentBitFieldAnd16 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 16-bit port.\r
+\r
+ Reads the 16-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 16-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If StartBit is greater than 15, then ASSERT().\r
+ If EndBit is greater than 15, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..15.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..15.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT16\r
+EFIAPI\r
+PciSegmentBitFieldAndThenOr16 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT16 AndData,\r
+ IN UINT16 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldAndThenOr16 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a 32-bit PCI configuration register.\r
+\r
+ Reads and returns the 32-bit PCI configuration register specified by Address.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+\r
+ @return The 32-bit PCI configuration register specified by Address.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentRead32 (\r
+ IN UINT64 Address\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count));\r
+}\r
+\r
+/**\r
+ Writes a 32-bit PCI configuration register.\r
+\r
+ Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
+ Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param Value The value to write.\r
+\r
+ @return The parameter of Value.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentWrite32 (\r
+ IN UINT64 Address,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), Value);\r
+}\r
+\r
+/**\r
+ Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address,\r
+ performs a bitwise OR between the read result and the value specified by OrData,\r
+ and writes the result to the 32-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentOr32 (\r
+ IN UINT64 Address,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), OrData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ and writes the result to the 32-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentAnd32 (\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioAnd32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData);\r
+}\r
+\r
+/**\r
+ Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
+ followed a bitwise OR with another 32-bit value.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address,\r
+ performs a bitwise AND between the read result and the value specified by AndData,\r
+ performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
+ and writes the result to the 32-bit PCI configuration register specified by Address.\r
+ The value written to the PCI configuration register is returned.\r
+ This function must guarantee that all PCI read and write operations are serialized.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentAndThenOr32 (\r
+ IN UINT64 Address,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field of a PCI configuration register.\r
+\r
+ Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
+ specified by the StartBit and the EndBit. The value of the bit field is\r
+ returned.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to read.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+\r
+ @return The value of the bit field read from the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentBitFieldRead32 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldRead32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit);\r
+}\r
+\r
+/**\r
+ Writes a bit field to a PCI configuration register.\r
+\r
+ Writes Value to the bit field of the PCI configuration register. The bit\r
+ field is specified by the StartBit and the EndBit. All other bits in the\r
+ destination PCI configuration register are preserved. The new value of the\r
+ 32-bit register is returned.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param Value New value of the bit field.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentBitFieldWrite32 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 Value\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldWrite32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, Value);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
+ writes the result back to the bit field in the 32-bit port.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise OR between the read result and the value specified by\r
+ OrData, and writes the result to the 32-bit PCI configuration register\r
+ specified by Address. The value written to the PCI configuration register is\r
+ returned. This function must guarantee that all PCI read and write operations\r
+ are serialized. Extra left bits in OrData are stripped.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param OrData The value to OR with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentBitFieldOr32 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, OrData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
+ AND, and writes the result back to the bit field in the 32-bit register.\r
+\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r
+ AND between the read result and the value specified by AndData, and writes the result\r
+ to the 32-bit PCI configuration register specified by Address. The value written to\r
+ the PCI configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in AndData are stripped.\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If Address is not aligned on a 32-bit boundary, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentBitFieldAnd32 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData);\r
+}\r
+\r
+/**\r
+ Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
+ bitwise OR, and writes the result back to the bit field in the\r
+ 32-bit port.\r
+\r
+ Reads the 32-bit PCI configuration register specified by Address, performs a\r
+ bitwise AND followed by a bitwise OR between the read result and\r
+ the value specified by AndData, and writes the result to the 32-bit PCI\r
+ configuration register specified by Address. The value written to the PCI\r
+ configuration register is returned. This function must guarantee that all PCI\r
+ read and write operations are serialized. Extra left bits in both AndData and\r
+ OrData are stripped.\r
+\r
+ If any reserved bits in Address are set, then ASSERT().\r
+ If StartBit is greater than 31, then ASSERT().\r
+ If EndBit is greater than 31, then ASSERT().\r
+ If EndBit is less than StartBit, then ASSERT().\r
+ If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+ If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
+\r
+ @param Address PCI configuration register to write.\r
+ @param StartBit The ordinal of the least significant bit in the bit field.\r
+ Range 0..31.\r
+ @param EndBit The ordinal of the most significant bit in the bit field.\r
+ Range 0..31.\r
+ @param AndData The value to AND with the PCI configuration register.\r
+ @param OrData The value to OR with the result of the AND operation.\r
+\r
+ @return The value written back to the PCI configuration register.\r
+\r
+**/\r
+UINT32\r
+EFIAPI\r
+PciSegmentBitFieldAndThenOr32 (\r
+ IN UINT64 Address,\r
+ IN UINTN StartBit,\r
+ IN UINTN EndBit,\r
+ IN UINT32 AndData,\r
+ IN UINT32 OrData\r
+ )\r
+{\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ return MmioBitFieldAndThenOr32 (PciSegmentLibGetEcamAddress (Address, SegmentInfo, Count), StartBit, EndBit, AndData, OrData);\r
+}\r
+\r
+/**\r
+ Reads a range of PCI configuration registers into a caller supplied buffer.\r
+\r
+ Reads the range of PCI configuration registers specified by StartAddress and\r
+ Size into the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be read. Size is\r
+ returned. When possible 32-bit PCI configuration read cycles are used to read\r
+ from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
+ and 16-bit PCI configuration read cycles may be used at the beginning and the\r
+ end of the range.\r
+\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
+ If Size > 0 and Buffer is NULL, then ASSERT().\r
+\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
+ Function and Register.\r
+ @param Size Size in bytes of the transfer.\r
+ @param Buffer Pointer to a buffer receiving the data read.\r
+\r
+ @return Size\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PciSegmentReadBuffer (\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ OUT VOID *Buffer\r
+ )\r
+{\r
+ UINTN ReturnValue;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Address;\r
+\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);\r
+\r
+ if (Size == 0) {\r
+ return 0;\r
+ }\r
+\r
+ ASSERT (Buffer != NULL);\r
+\r
+ //\r
+ // Save Size for return\r
+ //\r
+ ReturnValue = Size;\r
+\r
+ if ((Address & BIT0) != 0) {\r
+ //\r
+ // Read a byte if StartAddress is byte aligned\r
+ //\r
+ *(volatile UINT8 *)Buffer = MmioRead8 (Address);\r
+ Address += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16) && (Address & BIT1) != 0) {\r
+ //\r
+ // Read a word if StartAddress is word aligned\r
+ //\r
+ WriteUnaligned16 (Buffer, MmioRead16 (Address));\r
+ Address += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16*)Buffer + 1;\r
+ }\r
+\r
+ while (Size >= sizeof (UINT32)) {\r
+ //\r
+ // Read as many double words as possible\r
+ //\r
+ WriteUnaligned32 (Buffer, MmioRead32 (Address));\r
+ Address += sizeof (UINT32);\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16)) {\r
+ //\r
+ // Read the last remaining word if exist\r
+ //\r
+ WriteUnaligned16 (Buffer, MmioRead16 (Address));\r
+ Address += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT8)) {\r
+ //\r
+ // Read the last remaining byte if exist\r
+ //\r
+ *(volatile UINT8 *)Buffer = MmioRead8 (Address);\r
+ }\r
+\r
+ return ReturnValue;\r
+}\r
+\r
+/**\r
+ Copies the data in a caller supplied buffer to a specified range of PCI\r
+ configuration space.\r
+\r
+ Writes the range of PCI configuration registers specified by StartAddress and\r
+ Size from the buffer specified by Buffer. This function only allows the PCI\r
+ configuration registers from a single PCI function to be written. Size is\r
+ returned. When possible 32-bit PCI configuration write cycles are used to\r
+ write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
+ 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
+ and the end of the range.\r
+\r
+ If any reserved bits in StartAddress are set, then ASSERT().\r
+ If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
+ If Size > 0 and Buffer is NULL, then ASSERT().\r
+\r
+ @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r
+ Function and Register.\r
+ @param Size Size in bytes of the transfer.\r
+ @param Buffer Pointer to a buffer containing the data to write.\r
+\r
+ @return The parameter of Size.\r
+\r
+**/\r
+UINTN\r
+EFIAPI\r
+PciSegmentWriteBuffer (\r
+ IN UINT64 StartAddress,\r
+ IN UINTN Size,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ UINTN ReturnValue;\r
+ UINTN Count;\r
+ PCI_SEGMENT_INFO *SegmentInfo;\r
+ UINTN Address;\r
+\r
+ ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
+\r
+ SegmentInfo = GetPciSegmentInfo (&Count);\r
+ Address = PciSegmentLibGetEcamAddress (StartAddress, SegmentInfo, Count);\r
+\r
+ if (Size == 0) {\r
+ return 0;\r
+ }\r
+\r
+ ASSERT (Buffer != NULL);\r
+\r
+ //\r
+ // Save Size for return\r
+ //\r
+ ReturnValue = Size;\r
+\r
+ if ((Address & BIT0) != 0) {\r
+ //\r
+ // Write a byte if StartAddress is byte aligned\r
+ //\r
+ MmioWrite8 (Address, *(UINT8*)Buffer);\r
+ Address += sizeof (UINT8);\r
+ Size -= sizeof (UINT8);\r
+ Buffer = (UINT8*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16) && (Address & BIT1) != 0) {\r
+ //\r
+ // Write a word if StartAddress is word aligned\r
+ //\r
+ MmioWrite16 (Address, ReadUnaligned16 (Buffer));\r
+ Address += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16*)Buffer + 1;\r
+ }\r
+\r
+ while (Size >= sizeof (UINT32)) {\r
+ //\r
+ // Write as many double words as possible\r
+ //\r
+ MmioWrite32 (Address, ReadUnaligned32 (Buffer));\r
+ Address += sizeof (UINT32);\r
+ Size -= sizeof (UINT32);\r
+ Buffer = (UINT32*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT16)) {\r
+ //\r
+ // Write the last remaining word if exist\r
+ //\r
+ MmioWrite16 (Address, ReadUnaligned16 (Buffer));\r
+ Address += sizeof (UINT16);\r
+ Size -= sizeof (UINT16);\r
+ Buffer = (UINT16*)Buffer + 1;\r
+ }\r
+\r
+ if (Size >= sizeof (UINT8)) {\r
+ //\r
+ // Write the last remaining byte if exist\r
+ //\r
+ MmioWrite8 (Address, *(UINT8*)Buffer);\r
+ }\r
+\r
+ return ReturnValue;\r
+}\r
projects / mirror_edk2.git / commitdiff