Add generic HPET Timer DXE Driver and support libraries

Signed-off-by: mdkinney
Reviewed-by: li-elvin
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12259 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/UefiCpuPkg/Include/Library/LocalApicLib.h b/UefiCpuPkg/Include/Library/LocalApicLib.h
index d68e0e48b97f8769eaca42ac6d3c6bf339aae13d..52914fa9bdf97b7907b77f6b44870f3747b620f8 100644 (file)
--- a/UefiCpuPkg/Include/Library/LocalApicLib.h
+++ b/UefiCpuPkg/Include/Library/LocalApicLib.h
@@ -4,7 +4,7 @@
   Local APIC library assumes local APIC is enabled. It does not\r
   handles cases where local APIC is disabled.\r
 \r
-  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -319,5 +319,54 @@ SendApicEoi (
   VOID\r
   );\r
 \r
+/**\r
+  Get the 32-bit address that a device should use to send a Message Signaled \r
+  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+  @return 32-bit address used to send an MSI to the Local APIC.\r
+**/\r
+UINT32\r
+EFIAPI    \r
+GetApicMsiAddress (\r
+  VOID\r
+  );\r
+    \r
+/**\r
+  Get the 64-bit data value that a device should use to send a Message Signaled \r
+  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+  If Vector is not in range 0x10..0xFE, then ASSERT().\r
+  If DeliveryMode is not supported, then ASSERT().\r
+  \r
+  @param  Vector          The 8-bit interrupt vector associated with the MSI.  \r
+                          Must be in the range 0x10..0xFE\r
+  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI \r
+                          is handled.  The only supported values are:\r
+                            0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
+                            1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
+                            2: LOCAL_APIC_DELIVERY_MODE_SMI\r
+                            4: LOCAL_APIC_DELIVERY_MODE_NMI\r
+                            5: LOCAL_APIC_DELIVERY_MODE_INIT\r
+                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
+                          \r
+  @param  LevelTriggered  TRUE specifies a level triggered interrupt.  \r
+                          FALSE specifies an edge triggered interrupt.\r
+  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.\r
+                          TRUE specifies a level triggered interrupt that active \r
+                          when the interrupt line is asserted.\r
+                          FALSE specifies a level triggered interrupt that active \r
+                          when the interrupt line is deasserted.\r
+\r
+  @return 64-bit data value used to send an MSI to the Local APIC.\r
+**/\r
+UINT64\r
+EFIAPI    \r
+GetApicMsiValue (\r
+  IN UINT8    Vector,\r
+  IN UINTN    DeliveryMode,\r
+  IN BOOLEAN  LevelTriggered,\r
+  IN BOOLEAN  AssertionLevel\r
+  );\r
+  \r
 #endif\r
 \r

diff --git a/UefiCpuPkg/Include/Register/LocalApic.h b/UefiCpuPkg/Include/Register/LocalApic.h
index 9f8f1bb8bb7de0c195087bcef931d1cf08d47206..bb0e211dc7e1b106ee00a544108cf039fcb788c2 100644 (file)
--- a/UefiCpuPkg/Include/Register/LocalApic.h
+++ b/UefiCpuPkg/Include/Register/LocalApic.h
@@ -1,7 +1,7 @@
 /** @file\r
   IA32 Local APIC Definitions.\r
 \r
-  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -179,5 +179,36 @@ typedef union {
   UINT32    Uint32;\r
 } LOCAL_APIC_LVT_LINT;\r
 \r
+//\r
+// MSI Address Register\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT32  Reserved0:2;         ///< Reserved\r
+    UINT32  DestinationMode:1;   ///< Specifies the Destination Mode.\r
+    UINT32  RedirectionHint:1;   ///< Specifies the Redirection Hint.\r
+    UINT32  Reserved1:8;         ///< Reserved.\r
+    UINT32  DestinationId:8;     ///< Specifies the Destination ID.\r
+    UINT32  BaseAddress:12;      ///< Must be 0FEEH\r
+  } Bits;\r
+  UINT32    Uint32;\r
+} LOCAL_APIC_MSI_ADDRESS;\r
+\r
+//\r
+// MSI Address Register\r
+//\r
+typedef union {\r
+  struct {\r
+    UINT32  Vector:8;            ///< Interrupt vector in range 010h..0FEH\r
+    UINT32  DeliveryMode:3;      ///< Specifies the type of interrupt to be sent.\r
+    UINT32  Reserved0:3;         ///< Reserved.\r
+    UINT32  Level:1;             ///< 0:Deassert, 1:Assert.  Ignored for Edge triggered interrupts.\r
+    UINT32  TriggerMode:1;       ///< 0:Edge,     1:Level.\r
+    UINT32  Reserved1:16;        ///< Reserved.\r
+    UINT32  Reserved2:32;        ///< Reserved.\r
+  } Bits;\r
+  UINT64    Uint64;\r
+} LOCAL_APIC_MSI_DATA;\r
+\r
 #endif\r
 \r

diff --git a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
index 79a0fcd413332c3a17dd97c98beec768c86c47ba..77c24deed0b3096b941bea0d3c62bac96ae8d757 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.c
@@ -3,7 +3,7 @@
 \r
   This local APIC library instance supports xAPIC mode only.\r
 \r
-  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -675,3 +675,80 @@ SendApicEoi (
   WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r
 }\r
 \r
+/**\r
+  Get the 32-bit address that a device should use to send a Message Signaled \r
+  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+  @return 32-bit address used to send an MSI to the Local APIC.\r
+**/\r
+UINT32\r
+EFIAPI    \r
+GetApicMsiAddress (\r
+  VOID\r
+  )\r
+{\r
+  LOCAL_APIC_MSI_ADDRESS  MsiAddress;\r
+\r
+  //\r
+  // Return address for an MSI interrupt to be delivered only to the APIC ID \r
+  // of the currently executing processor.\r
+  //\r
+  MsiAddress.Uint32             = 0;\r
+  MsiAddress.Bits.BaseAddress   = 0xFEE;\r
+  MsiAddress.Bits.DestinationId = GetApicId ();\r
+  return MsiAddress.Uint32;\r
+}\r
+    \r
+/**\r
+  Get the 64-bit data value that a device should use to send a Message Signaled \r
+  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+  If Vector is not in range 0x10..0xFE, then ASSERT().\r
+  If DeliveryMode is not supported, then ASSERT().\r
+  \r
+  @param  Vector          The 8-bit interrupt vector associated with the MSI.  \r
+                          Must be in the range 0x10..0xFE\r
+  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI \r
+                          is handled.  The only supported values are:\r
+                            0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
+                            1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
+                            2: LOCAL_APIC_DELIVERY_MODE_SMI\r
+                            4: LOCAL_APIC_DELIVERY_MODE_NMI\r
+                            5: LOCAL_APIC_DELIVERY_MODE_INIT\r
+                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
+                          \r
+  @param  LevelTriggered  TRUE specifies a level triggered interrupt.  \r
+                          FALSE specifies an edge triggered interrupt.\r
+  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.\r
+                          TRUE specifies a level triggered interrupt that active \r
+                          when the interrupt line is asserted.\r
+                          FALSE specifies a level triggered interrupt that active \r
+                          when the interrupt line is deasserted.\r
+\r
+  @return 64-bit data value used to send an MSI to the Local APIC.\r
+**/\r
+UINT64\r
+EFIAPI    \r
+GetApicMsiValue (\r
+  IN UINT8    Vector,\r
+  IN UINTN    DeliveryMode,\r
+  IN BOOLEAN  LevelTriggered,\r
+  IN BOOLEAN  AssertionLevel\r
+  )\r
+{\r
+  LOCAL_APIC_MSI_DATA  MsiData;\r
+\r
+  ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
+  ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
+  \r
+  MsiData.Uint64            = 0;\r
+  MsiData.Bits.Vector       = Vector;\r
+  MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
+  if (LevelTriggered) {\r
+    MsiData.Bits.TriggerMode = 1;\r
+    if (AssertionLevel) {\r
+      MsiData.Bits.Level = 1;\r
+    }\r
+  }\r
+  return MsiData.Uint64;\r
+}\r

diff --git a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
index 9f08f5d188c14d9ec5313275b0ce0b67aa16c9e0..62201cd2404128dab76adc968e430a3af7650617 100644 (file)
--- a/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
+++ b/UefiCpuPkg/Library/BaseXApicX2ApicLib/BaseXApicX2ApicLib.c
@@ -4,7 +4,7 @@
   This local APIC library instance supports x2APIC capable processors\r
   which have xAPIC and x2APIC modes.\r
 \r
-  Copyright (c) 2010, Intel Corporation. All rights reserved.<BR>\r
+  Copyright (c) 2010 - 2011, Intel Corporation. All rights reserved.<BR>\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
@@ -758,3 +758,80 @@ SendApicEoi (
   WriteLocalApicReg (XAPIC_EOI_OFFSET, 0);\r
 }\r
 \r
+/**\r
+  Get the 32-bit address that a device should use to send a Message Signaled \r
+  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+  @return 32-bit address used to send an MSI to the Local APIC.\r
+**/\r
+UINT32\r
+EFIAPI    \r
+GetApicMsiAddress (\r
+  VOID\r
+  )\r
+{\r
+  LOCAL_APIC_MSI_ADDRESS  MsiAddress;\r
+\r
+  //\r
+  // Return address for an MSI interrupt to be delivered only to the APIC ID \r
+  // of the currently executing processor.\r
+  //\r
+  MsiAddress.Uint32             = 0;\r
+  MsiAddress.Bits.BaseAddress   = 0xFEE;\r
+  MsiAddress.Bits.DestinationId = GetApicId ();\r
+  return MsiAddress.Uint32;\r
+}\r
+    \r
+/**\r
+  Get the 64-bit data value that a device should use to send a Message Signaled \r
+  Interrupt (MSI) to the Local APIC of the currently executing processor.\r
+\r
+  If Vector is not in range 0x10..0xFE, then ASSERT().\r
+  If DeliveryMode is not supported, then ASSERT().\r
+  \r
+  @param  Vector          The 8-bit interrupt vector associated with the MSI.  \r
+                          Must be in the range 0x10..0xFE\r
+  @param  DeliveryMode    A 3-bit value that specifies how the recept of the MSI \r
+                          is handled.  The only supported values are:\r
+                            0: LOCAL_APIC_DELIVERY_MODE_FIXED\r
+                            1: LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY\r
+                            2: LOCAL_APIC_DELIVERY_MODE_SMI\r
+                            4: LOCAL_APIC_DELIVERY_MODE_NMI\r
+                            5: LOCAL_APIC_DELIVERY_MODE_INIT\r
+                            7: LOCAL_APIC_DELIVERY_MODE_EXTINT\r
+                          \r
+  @param  LevelTriggered  TRUE specifies a level triggered interrupt.  \r
+                          FALSE specifies an edge triggered interrupt.\r
+  @param  AssertionLevel  Ignored if LevelTriggered is FALSE.\r
+                          TRUE specifies a level triggered interrupt that active \r
+                          when the interrupt line is asserted.\r
+                          FALSE specifies a level triggered interrupt that active \r
+                          when the interrupt line is deasserted.\r
+\r
+  @return 64-bit data value used to send an MSI to the Local APIC.\r
+**/\r
+UINT64\r
+EFIAPI    \r
+GetApicMsiValue (\r
+  IN UINT8    Vector,\r
+  IN UINTN    DeliveryMode,\r
+  IN BOOLEAN  LevelTriggered,\r
+  IN BOOLEAN  AssertionLevel\r
+  )\r
+{\r
+  LOCAL_APIC_MSI_DATA  MsiData;\r
+\r
+  ASSERT (Vector >= 0x10 && Vector <= 0xFE);\r
+  ASSERT (DeliveryMode < 8 && DeliveryMode != 6 && DeliveryMode != 3);\r
+  \r
+  MsiData.Uint64            = 0;\r
+  MsiData.Bits.Vector       = Vector;\r
+  MsiData.Bits.DeliveryMode = (UINT32)DeliveryMode;\r
+  if (LevelTriggered) {\r
+    MsiData.Bits.TriggerMode = 1;\r
+    if (AssertionLevel) {\r
+      MsiData.Bits.Level = 1;\r
+    }\r
+  }\r
+  return MsiData.Uint64;\r
+}\r