ArmPkg/AArch64Mmu.h: Fix 'Shift is >= width of type'

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>
git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14956 6f19259b-4bc3-4df7-8a09-765794883524

diff --git a/ArmPkg/Include/Chipset/AArch64Mmu.h b/ArmPkg/Include/Chipset/AArch64Mmu.h
index 7c9890331feb88eb28d035bcc6864e63ac61e77d..77a96ec637310c0d8de6e5a908141074f9fb38f4 100644 (file)
--- a/ArmPkg/Include/Chipset/AArch64Mmu.h
+++ b/ArmPkg/Include/Chipset/AArch64Mmu.h
@@ -102,12 +102,12 @@
 \r
 #define TCR_TG0_4KB                             (0 << 14)\r
 \r
-#define TCR_IPS_4GB                             (0UL << 32)\r
-#define TCR_IPS_64GB                            (1UL << 32)\r
-#define TCR_IPS_1TB                             (2UL << 32)\r
-#define TCR_IPS_4TB                             (3UL << 32)\r
-#define TCR_IPS_16TB                            (4UL << 32)\r
-#define TCR_IPS_256TB                           (5UL << 32)\r
+#define TCR_IPS_4GB                             (0ULL << 32)\r
+#define TCR_IPS_64GB                            (1ULL << 32)\r
+#define TCR_IPS_1TB                             (2ULL << 32)\r
+#define TCR_IPS_4TB                             (3ULL << 32)\r
+#define TCR_IPS_16TB                            (4ULL << 32)\r
+#define TCR_IPS_256TB                           (5ULL << 32)\r
 \r
 \r
 #define TTBR_ASID_FIELD                      (48)\r