--- /dev/null
+/** @file\r
+ Header file for eMMC support.\r
+\r
+ This header file contains some definitions defined in EMMC4.5/EMMC5.0 spec.\r
+\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __EMMC_H__\r
+#define __EMMC_H__\r
+\r
+//\r
+// EMMC command index\r
+//\r
+#define EMMC_GO_IDLE_STATE 0\r
+#define EMMC_SEND_OP_COND 1\r
+#define EMMC_ALL_SEND_CID 2\r
+#define EMMC_SET_RELATIVE_ADDR 3\r
+#define EMMC_SET_DSR 4\r
+#define EMMC_SLEEP_AWAKE 5\r
+#define EMMC_SWITCH 6\r
+#define EMMC_SELECT_DESELECT_CARD 7\r
+#define EMMC_SEND_EXT_CSD 8\r
+#define EMMC_SEND_CSD 9\r
+#define EMMC_SEND_CID 10\r
+#define EMMC_STOP_TRANSMISSION 12\r
+#define EMMC_SEND_STATUS 13\r
+#define EMMC_BUSTEST_R 14\r
+#define EMMC_GO_INACTIVE_STATE 15\r
+#define EMMC_SET_BLOCKLEN 16\r
+#define EMMC_READ_SINGLE_BLOCK 17\r
+#define EMMC_READ_MULTIPLE_BLOCK 18\r
+#define EMMC_BUSTEST_W 19\r
+#define EMMC_SEND_TUNING_BLOCK 21\r
+#define EMMC_SET_BLOCK_COUNT 23\r
+#define EMMC_WRITE_BLOCK 24\r
+#define EMMC_WRITE_MULTIPLE_BLOCK 25\r
+#define EMMC_PROGRAM_CID 26\r
+#define EMMC_PROGRAM_CSD 27\r
+#define EMMC_SET_WRITE_PROT 28\r
+#define EMMC_CLR_WRITE_PROT 29\r
+#define EMMC_SEND_WRITE_PROT 30\r
+#define EMMC_SEND_WRITE_PROT_TYPE 31\r
+#define EMMC_ERASE_GROUP_START 35\r
+#define EMMC_ERASE_GROUP_END 36\r
+#define EMMC_ERASE 38\r
+#define EMMC_FAST_IO 39\r
+#define EMMC_GO_IRQ_STATE 40\r
+#define EMMC_LOCK_UNLOCK 42\r
+#define EMMC_SET_TIME 49\r
+#define EMMC_PROTOCOL_RD 53\r
+#define EMMC_PROTOCOL_WR 54\r
+#define EMMC_APP_CMD 55\r
+#define EMMC_GEN_CMD 56\r
+\r
+typedef enum {\r
+ EmmcPartitionUserData = 0,\r
+ EmmcPartitionBoot1 = 1,\r
+ EmmcPartitionBoot2 = 2,\r
+ EmmcPartitionRPMB = 3,\r
+ EmmcPartitionGP1 = 4,\r
+ EmmcPartitionGP2 = 5,\r
+ EmmcPartitionGP3 = 6,\r
+ EmmcPartitionGP4 = 7,\r
+ EmmcPartitionUnknown\r
+} EMMC_PARTITION_TYPE;\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT8 NotUsed:1; // Not used [0:0]\r
+ UINT8 Crc:7; // CRC [7:1]\r
+ UINT8 ManufacturingDate; // Manufacturing date [15:8]\r
+ UINT8 ProductSerialNumber[4]; // Product serial number [47:16]\r
+ UINT8 ProductRevision; // Product revision [55:48]\r
+ UINT8 ProductName[6]; // Product name [103:56]\r
+ UINT8 OemId; // OEM/Application ID [111:104]\r
+ UINT8 DeviceType:2; // Device/BGA [113:112]\r
+ UINT8 Reserved:6; // Reserved [119:114]\r
+ UINT8 ManufacturerId; // Manufacturer ID [127:120]\r
+} EMMC_CID;\r
+\r
+typedef struct {\r
+ UINT32 NotUsed:1; // Not used [0:0]\r
+ UINT32 Crc:7; // CRC [7:1]\r
+ UINT32 Ecc:2; // ECC code [9:8]\r
+ UINT32 FileFormat:2; // File format [11:10]\r
+ UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]\r
+ UINT32 PermWriteProtect:1; // Permanent write protection [13:13]\r
+ UINT32 Copy:1; // Copy flag (OTP) [14:14]\r
+ UINT32 FileFormatGrp:1; // File format group [15:15]\r
+ UINT32 ContentProtApp:1; // Content protection application [16:16]\r
+ UINT32 Reserved:4; // Reserved [20:17]\r
+ UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]\r
+ UINT32 WriteBlLen:4; // Max. write data block length [25:22]\r
+ UINT32 R2WFactor:3; // Write speed factor [28:26]\r
+ UINT32 DefaultEcc:2; // Manufacturer default ECC [30:29]\r
+ UINT32 WpGrpEnable:1; // Write protect group enable [31:31]\r
+\r
+ UINT32 WpGrpSize:5; // Write protect group size [36:32]\r
+ UINT32 EraseGrpMult:5; // Erase group size multiplier [41:37]\r
+ UINT32 EraseGrpSize:5; // Erase group size [46:42]\r
+ UINT32 CSizeMult:3; // Device size multiplier [49:47]\r
+ UINT32 VddWCurrMax:3; // Max. write current @ VDD max [52:50]\r
+ UINT32 VddWCurrMin:3; // Max. write current @ VDD min [55:53]\r
+ UINT32 VddRCurrMax:3; // Max. read current @ VDD max [58:56]\r
+ UINT32 VddRCurrMin:3; // Max. read current @ VDD min [61:59]\r
+ UINT32 CSizeLow:2; // Device size low two bits [63:62]\r
+\r
+ UINT32 CSizeHigh:10; // Device size high eight bits [73:64]\r
+ UINT32 Reserved1:2; // Reserved [75:74]\r
+ UINT32 DsrImp:1; // DSR implemented [76:76]\r
+ UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]\r
+ UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]\r
+ UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]\r
+ UINT32 ReadBlLen:4; // Max. read data block length [83:80]\r
+ UINT32 Ccc:12; // Device command classes [95:84]\r
+\r
+ UINT32 TranSpeed:8; // Max. bus clock frequency [103:96]\r
+ UINT32 Nsac:8; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]\r
+ UINT32 Taac:8; // Data read access-time 1 [119:112]\r
+ UINT32 Reserved2:2; // Reserved [121:120]\r
+ UINT32 SpecVers:4; // System specification version [125:122]\r
+ UINT32 CsdStructure:2; // CSD structure [127:126]\r
+} EMMC_CSD;\r
+\r
+typedef struct {\r
+ //\r
+ // Modes Segment\r
+ //\r
+ UINT8 Reserved[16]; // Reserved [15:0]\r
+ UINT8 SecureRemovalType; // Secure Removal Type R/W & R [16]\r
+ UINT8 ProductStateAwarenessEnablement; // Product state awareness enablement R/W/E & R [17]\r
+ UINT8 MaxPreLoadingDataSize[4]; // Max pre loading data size R [21:18]\r
+ UINT8 PreLoadingDataSize[4]; // Pre loading data size R/W/EP [25:22]\r
+ UINT8 FfuStatus; // FFU status R [26]\r
+ UINT8 Reserved1[2]; // Reserved [28:27]\r
+ UINT8 ModeOperationCodes; // Mode operation codes W/EP [29]\r
+ UINT8 ModeConfig; // Mode config R/W/EP [30]\r
+ UINT8 Reserved2; // Reserved [31]\r
+ UINT8 FlushCache; // Flushing of the cache W/EP [32]\r
+ UINT8 CacheCtrl; // Control to turn the Cache ON/OFF R/W/EP [33]\r
+ UINT8 PowerOffNotification; // Power Off Notification R/W/EP [34]\r
+ UINT8 PackedFailureIndex; // Packed command failure index R [35]\r
+ UINT8 PackedCommandStatus; // Packed command status R [36]\r
+ UINT8 ContextConf[15]; // Context configuration R/W/EP [51:37]\r
+ UINT8 ExtPartitionsAttribute[2]; // Extended Partitions Attribute R/W [53:52]\r
+ UINT8 ExceptionEventsStatus[2]; // Exception events status R [55:54]\r
+ UINT8 ExceptionEventsCtrl[2]; // Exception events control R/W/EP [57:56]\r
+ UINT8 DyncapNeeded; // Number of addressed group to be Released R [58]\r
+ UINT8 Class6Ctrl; // Class 6 commands control R/W/EP [59]\r
+ UINT8 IniTimeoutEmu; // 1st initialization after disabling sector size emulation R [60]\r
+ UINT8 DataSectorSize; // Sector size R [61]\r
+ UINT8 UseNativeSector; // Sector size emulation R/W [62]\r
+ UINT8 NativeSectorSize; // Native sector size R [63]\r
+ UINT8 VendorSpecificField[64]; // Vendor Specific Fields <vendor specific> [127:64]\r
+ UINT8 Reserved3[2]; // Reserved [129:128]\r
+ UINT8 ProgramCidCsdDdrSupport; // Program CID/CSD in DDR mode support R [130]\r
+ UINT8 PeriodicWakeup; // Periodic Wake-up R/W/E [131]\r
+ UINT8 TcaseSupport; // Package Case Temperature is controlled W/EP [132]\r
+ UINT8 ProductionStateAwareness; // Production state awareness R/W/E [133]\r
+ UINT8 SecBadBlkMgmnt; // Bad Block Management mode R/W [134]\r
+ UINT8 Reserved4; // Reserved [135]\r
+ UINT8 EnhStartAddr[4]; // Enhanced User Data Start Address R/W [139:136]\r
+ UINT8 EnhSizeMult[3]; // Enhanced User Data Area Size R/W [142:140]\r
+ UINT8 GpSizeMult[12]; // General Purpose Partition Size R/W [154:143]\r
+ UINT8 PartitionSettingCompleted; // Partitioning Setting R/W [155]\r
+ UINT8 PartitionsAttribute; // Partitions attribute R/W [156]\r
+ UINT8 MaxEnhSizeMult[3]; // Max Enhanced Area Size R [159:157]\r
+ UINT8 PartitioningSupport; // Partitioning Support R [160]\r
+ UINT8 HpiMgmt; // HPI management R/W/EP [161]\r
+ UINT8 RstFunction; // H/W reset function R/W [162]\r
+ UINT8 BkopsEn; // Enable background operations handshake R/W [163]\r
+ UINT8 BkopsStart; // Manually start background operations W/EP [164]\r
+ UINT8 SanitizeStart; // Start Sanitize operation W/EP [165]\r
+ UINT8 WrRelParam; // Write reliability parameter register R [166]\r
+ UINT8 WrRelSet; // Write reliability setting register R/W [167]\r
+ UINT8 RpmbSizeMult; // RPMB Size R [168]\r
+ UINT8 FwConfig; // FW configuration R/W [169]\r
+ UINT8 Reserved5; // Reserved [170]\r
+ UINT8 UserWp; // User area write protection register R/W,R/W/CP&R/W/EP [171]\r
+ UINT8 Reserved6; // Reserved [172]\r
+ UINT8 BootWp; // Boot area write protection register R/W&R/W/CP[173]\r
+ UINT8 BootWpStatus; // Boot write protection status registers R [174]\r
+ UINT8 EraseGroupDef; // High-density erase group definition R/W/EP [175]\r
+ UINT8 Reserved7; // Reserved [176]\r
+ UINT8 BootBusConditions; // Boot bus Conditions R/W/E [177]\r
+ UINT8 BootConfigProt; // Boot config protection R/W&R/W/CP[178]\r
+ UINT8 PartitionConfig; // Partition configuration R/W/E&R/W/EP[179]\r
+ UINT8 Reserved8; // Reserved [180]\r
+ UINT8 ErasedMemCont; // Erased memory content R [181]\r
+ UINT8 Reserved9; // Reserved [182]\r
+ UINT8 BusWidth; // Bus width mode W/EP [183]\r
+ UINT8 Reserved10; // Reserved [184]\r
+ UINT8 HsTiming; // High-speed interface timing R/W/EP [185]\r
+ UINT8 Reserved11; // Reserved [186]\r
+ UINT8 PowerClass; // Power class R/W/EP [187]\r
+ UINT8 Reserved12; // Reserved [188]\r
+ UINT8 CmdSetRev; // Command set revision R [189]\r
+ UINT8 Reserved13; // Reserved [190]\r
+ UINT8 CmdSet; // Command set R/W/EP [191]\r
+ //\r
+ // Properties Segment\r
+ //\r
+ UINT8 ExtCsdRev; // Extended CSD revision [192]\r
+ UINT8 Reserved14; // Reserved [193]\r
+ UINT8 CsdStructure; // CSD STRUCTURE [194]\r
+ UINT8 Reserved15; // Reserved [195]\r
+ UINT8 DeviceType; // Device type [196]\r
+ UINT8 DriverStrength; // I/O Driver Strength [197]\r
+ UINT8 OutOfInterruptTime; // Out-of-interrupt busy timing[198]\r
+ UINT8 PartitionSwitchTime; // Partition switching timing [199]\r
+ UINT8 PwrCl52M195V; // Power class for 52MHz at 1.95V [200]\r
+ UINT8 PwrCl26M195V; // Power class for 26MHz at 1.95V [201]\r
+ UINT8 PwrCl52M360V; // Power class for 52MHz at 3.6V [202]\r
+ UINT8 PwrCl26M360V; // Power class for 26MHz at 3.6V [203]\r
+ UINT8 Reserved16; // Reserved [204]\r
+ UINT8 MinPerfR4B26M; // Minimum Read Performance for 4bit at 26MHz [205]\r
+ UINT8 MinPerfW4B26M; // Minimum Write Performance for 4bit at 26MHz [206]\r
+ UINT8 MinPerfR8B26M4B52M; // Minimum Read Performance for 8bit at 26MHz, for 4bit at 52MHz [207]\r
+ UINT8 MinPerfW8B26M4B52M; // Minimum Write Performance for 8bit at 26MHz, for 4bit at 52MHz [208]\r
+ UINT8 MinPerfR8B52M; // Minimum Read Performance for 8bit at 52MHz [209]\r
+ UINT8 MinPerfW8B52M; // Minimum Write Performance for 8bit at 52MHz [210]\r
+ UINT8 Reserved17; // Reserved [211]\r
+ UINT8 SecCount[4]; // Sector Count [215:212]\r
+ UINT8 SleepNotificationTime; // Sleep Notification Timout [216]\r
+ UINT8 SATimeout; // Sleep/awake timeout [217]\r
+ UINT8 ProductionStateAwarenessTimeout; // Production state awareness timeout [218]\r
+ UINT8 SCVccq; // Sleep current (VCCQ) [219]\r
+ UINT8 SCVcc; // Sleep current (VCC) [220]\r
+ UINT8 HcWpGrpSize; // High-capacity write protect group size [221]\r
+ UINT8 RelWrSecC; // Reliable write sector count [222]\r
+ UINT8 EraseTimeoutMult; // High-capacity erase timeout [223]\r
+ UINT8 HcEraseGrpSize; // High-capacity erase unit size [224]\r
+ UINT8 AccSize; // Access size [225]\r
+ UINT8 BootSizeMult; // Boot partition size [226]\r
+ UINT8 Reserved18; // Reserved [227]\r
+ UINT8 BootInfo; // Boot information [228]\r
+ UINT8 SecTrimMult; // Secure TRIM Multiplier [229]\r
+ UINT8 SecEraseMult; // Secure Erase Multiplier [230]\r
+ UINT8 SecFeatureSupport; // Secure Feature support [231]\r
+ UINT8 TrimMult; // TRIM Multiplier [232]\r
+ UINT8 Reserved19; // Reserved [233]\r
+ UINT8 MinPerfDdrR8b52M; // Minimum Read Performance for 8bit at 52MHz in DDR mode [234]\r
+ UINT8 MinPerfDdrW8b52M; // Minimum Write Performance for 8bit at 52MHz in DDR mode [235]\r
+ UINT8 PwrCl200M130V; // Power class for 200MHz, at VCCQ=1.3V, VCC = 3.6V [236]\r
+ UINT8 PwrCl200M195V; // Power class for 200MHz at VCCQ=1.95V, VCC = 3.6V [237]\r
+ UINT8 PwrClDdr52M195V; // Power class for 52MHz, DDR at VCC= 1.95V [238]\r
+ UINT8 PwrClDdr52M360V; // Power class for 52MHz, DDR at VCC= 3.6V [239]\r
+ UINT8 Reserved20; // Reserved [240]\r
+ UINT8 IniTimeoutAp; // 1st initialization time after partitioning [241]\r
+ UINT8 CorrectlyPrgSectorsNum[4]; // Number of correctly programmed sectors [245:242]\r
+ UINT8 BkopsStatus; // Background operations status [246]\r
+ UINT8 PowerOffLongTime; // Power off notification(long) timeout [247]\r
+ UINT8 GenericCmd6Time; // Generic CMD6 timeout [248]\r
+ UINT8 CacheSize[4]; // Cache size [252:249]\r
+ UINT8 PwrClDdr200M360V; // Power class for 200MHz, DDR at VCC= 3.6V [253]\r
+ UINT8 FirmwareVersion[8]; // Firmware version [261:254]\r
+ UINT8 DeviceVersion[2]; // Device version [263:262]\r
+ UINT8 OptimalTrimUnitSize; // Optimal trim unit size[264]\r
+ UINT8 OptimalWriteSize; // Optimal write size [265]\r
+ UINT8 OptimalReadSize; // Optimal read size [266]\r
+ UINT8 PreEolInfo; // Pre EOL information [267]\r
+ UINT8 DeviceLifeTimeEstTypA; // Device life time estimation type A [268]\r
+ UINT8 DeviceLifeTimeEstTypB; // Device life time estimation type B [269]\r
+ UINT8 VendorProprietaryHealthReport[32]; // Vendor proprietary health report [301:270]\r
+ UINT8 NumOfFwSectorsProgrammed[4]; // Number of FW sectors correctly programmed [305:302]\r
+ UINT8 Reserved21[181]; // Reserved [486:306]\r
+ UINT8 FfuArg[4]; // FFU Argument [490:487]\r
+ UINT8 OperationCodeTimeout; // Operation codes timeout [491]\r
+ UINT8 FfuFeatures; // FFU features [492]\r
+ UINT8 SupportedModes; // Supported modes [493]\r
+ UINT8 ExtSupport; // Extended partitions attribute support [494]\r
+ UINT8 LargeUnitSizeM1; // Large Unit size [495]\r
+ UINT8 ContextCapabilities; // Context management capabilities [496]\r
+ UINT8 TagResSize; // Tag Resources Size [497]\r
+ UINT8 TagUnitSize; // Tag Unit Size [498]\r
+ UINT8 DataTagSupport; // Data Tag Support [499]\r
+ UINT8 MaxPackedWrites; // Max packed write commands [500]\r
+ UINT8 MaxPackedReads; // Max packed read commands[501]\r
+ UINT8 BkOpsSupport; // Background operations support [502]\r
+ UINT8 HpiFeatures; // HPI features [503]\r
+ UINT8 SupportedCmdSet; // Supported Command Sets [504]\r
+ UINT8 ExtSecurityErr; // Extended Security Commands Error [505]\r
+ UINT8 Reserved22[6]; // Reserved [511:506]\r
+} EMMC_EXT_CSD;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
--- /dev/null
+/** @file\r
+ Header file for SD memory card support.\r
+\r
+ This header file contains some definitions defined in SD Physical Layer Simplified\r
+ Specification Version 4.10 spec.\r
+\r
+ Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef __SD_H__\r
+#define __SD_H__\r
+\r
+//\r
+// SD command index\r
+//\r
+#define SD_GO_IDLE_STATE 0\r
+#define SD_ALL_SEND_CID 2\r
+#define SD_SET_RELATIVE_ADDR 3\r
+#define SD_SET_DSR 4\r
+#define SDIO_SEND_OP_COND 5\r
+#define SD_SWITCH_FUNC 6\r
+#define SD_SELECT_DESELECT_CARD 7\r
+#define SD_SEND_IF_COND 8\r
+#define SD_SEND_CSD 9\r
+#define SD_SEND_CID 10\r
+#define SD_VOLTAGE_SWITCH 11\r
+#define SD_STOP_TRANSMISSION 12\r
+#define SD_SEND_STATUS 13\r
+#define SD_GO_INACTIVE_STATE 15\r
+#define SD_SET_BLOCKLEN 16\r
+#define SD_READ_SINGLE_BLOCK 17\r
+#define SD_READ_MULTIPLE_BLOCK 18\r
+#define SD_SEND_TUNING_BLOCK 19\r
+#define SD_SPEED_CLASS_CONTROL 20\r
+#define SD_SET_BLOCK_COUNT 23\r
+#define SD_WRITE_SINGLE_BLOCK 24\r
+#define SD_WRITE_MULTIPLE_BLOCK 25\r
+#define SD_PROGRAM_CSD 27\r
+#define SD_SET_WRITE_PROT 28\r
+#define SD_CLR_WRITE_PROT 29\r
+#define SD_SEND_WRITE_PROT 30\r
+#define SD_ERASE_WR_BLK_START 32\r
+#define SD_ERASE_WR_BLK_END 33\r
+#define SD_ERASE 38\r
+#define SD_LOCK_UNLOCK 42\r
+#define SD_READ_EXTR_SINGLE 48\r
+#define SD_WRITE_EXTR_SINGLE 49\r
+#define SDIO_RW_DIRECT 52\r
+#define SDIO_RW_EXTENDED 53\r
+#define SD_APP_CMD 55\r
+#define SD_GEN_CMD 56\r
+#define SD_READ_EXTR_MULTI 58\r
+#define SD_WRITE_EXTR_MULTI 59\r
+\r
+#define SD_SET_BUS_WIDTH 6 // ACMD6\r
+#define SD_STATUS 13 // ACMD13\r
+#define SD_SEND_NUM_WR_BLOCKS 22 // ACMD22\r
+#define SD_SET_WR_BLK_ERASE_COUNT 23 // ACMD23\r
+#define SD_SEND_OP_COND 41 // ACMD41\r
+#define SD_SET_CLR_CARD_DETECT 42 // ACMD42\r
+#define SD_SEND_SCR 51 // ACMD51\r
+\r
+#pragma pack(1)\r
+typedef struct {\r
+ UINT8 NotUsed:1; // Not used [0:0]\r
+ UINT8 Crc:7; // CRC [7:1]\r
+ UINT16 ManufacturingDate:12; // Manufacturing date [19:8]\r
+ UINT16 Reserved:4; // Reserved [23:20]\r
+ UINT8 ProductSerialNumber[4]; // Product serial number [55:24]\r
+ UINT8 ProductRevision; // Product revision [63:56]\r
+ UINT8 ProductName[5]; // Product name [103:64]\r
+ UINT8 OemId[2]; // OEM/Application ID [119:104]\r
+ UINT8 ManufacturerId; // Manufacturer ID [127:120]\r
+} SD_CID;\r
+\r
+typedef struct {\r
+ UINT32 NotUsed:1; // Not used [0:0]\r
+ UINT32 Crc:7; // CRC [7:1]\r
+ UINT32 Reserved:2; // Reserved [9:8]\r
+ UINT32 FileFormat:2; // File format [11:10]\r
+ UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]\r
+ UINT32 PermWriteProtect:1; // Permanent write protection [13:13]\r
+ UINT32 Copy:1; // Copy flag (OTP) [14:14]\r
+ UINT32 FileFormatGrp:1; // File format group [15:15]\r
+ UINT32 Reserved1:5; // Reserved [20:16]\r
+ UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]\r
+ UINT32 WriteBlLen:4; // Max. write data block length [25:22]\r
+ UINT32 R2WFactor:3; // Write speed factor [28:26]\r
+ UINT32 Reserved2:2; // Manufacturer default ECC [30:29]\r
+ UINT32 WpGrpEnable:1; // Write protect group enable [31:31]\r
+\r
+ UINT32 WpGrpSize:7; // Write protect group size [38:32]\r
+ UINT32 SectorSize:7; // Erase sector size [45:39]\r
+ UINT32 EraseBlkEn:1; // Erase single block enable [46:46]\r
+ UINT32 CSizeMul:3; // device size multiplier [49:47]\r
+ UINT32 VddWCurrMax:3; // max. write current @VDD max [52:50]\r
+ UINT32 VddWCurrMin:3; // max. write current @VDD min [55:53]\r
+ UINT32 VddRCurrMax:3; // max. read current @VDD max [58:56]\r
+ UINT32 VddRCurrMin:3; // max. read current @VDD min [61:59]\r
+ UINT32 CSizeLow:2; // Device size low 2 bits [63:62]\r
+\r
+ UINT32 CSizeHigh:10; // Device size high 10 bits [73:64]\r
+ UINT32 Reserved4:2; // Reserved [75:74]\r
+ UINT32 DsrImp:1; // DSR implemented [76:76]\r
+ UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]\r
+ UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]\r
+ UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]\r
+ UINT32 ReadBlLen:4; // Max. read data block length [83:80]\r
+ UINT32 Ccc:12; // Card command classes [95:84]\r
+\r
+ UINT32 TranSpeed:8; // Max. data transfer rate [103:96]\r
+ UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]\r
+ UINT32 Taac:8; // Data read access-time [119:112]\r
+ UINT32 Reserved5:6; // Reserved [125:120]\r
+ UINT32 CsdStructure:2; // CSD structure [127:126]\r
+} SD_CSD;\r
+\r
+typedef struct {\r
+ UINT32 NotUsed:1; // Not used [0:0]\r
+ UINT32 Crc:7; // CRC [7:1]\r
+ UINT32 Reserved:2; // Reserved [9:8]\r
+ UINT32 FileFormat:2; // File format [11:10]\r
+ UINT32 TmpWriteProtect:1; // Temporary write protection [12:12]\r
+ UINT32 PermWriteProtect:1; // Permanent write protection [13:13]\r
+ UINT32 Copy:1; // Copy flag (OTP) [14:14]\r
+ UINT32 FileFormatGrp:1; // File format group [15:15]\r
+ UINT32 Reserved1:5; // Reserved [20:16]\r
+ UINT32 WriteBlPartial:1; // Partial blocks for write allowed [21:21]\r
+ UINT32 WriteBlLen:4; // Max. write data block length [25:22]\r
+ UINT32 R2WFactor:3; // Write speed factor [28:26]\r
+ UINT32 Reserved2:2; // Manufacturer default ECC [30:29]\r
+ UINT32 WpGrpEnable:1; // Write protect group enable [31:31]\r
+\r
+ UINT32 WpGrpSize:7; // Write protect group size [38:32]\r
+ UINT32 SectorSize:7; // Erase sector size [45:39]\r
+ UINT32 EraseBlkEn:1; // Erase single block enable [46:46]\r
+ UINT32 Reserved3:1; // Reserved [47:47]\r
+ UINT32 CSizeLow:16; // Device size low 16 bits [63:48]\r
+\r
+ UINT32 CSizeHigh:6; // Device size high 6 bits [69:64]\r
+ UINT32 Reserved4:6; // Reserved [75:70]\r
+ UINT32 DsrImp:1; // DSR implemented [76:76]\r
+ UINT32 ReadBlkMisalign:1; // Read block misalignment [77:77]\r
+ UINT32 WriteBlkMisalign:1; // Write block misalignment [78:78]\r
+ UINT32 ReadBlPartial:1; // Partial blocks for read allowed [79:79]\r
+ UINT32 ReadBlLen:4; // Max. read data block length [83:80]\r
+ UINT32 Ccc:12; // Card command classes [95:84]\r
+\r
+ UINT32 TranSpeed:8; // Max. data transfer rate [103:96]\r
+ UINT32 Nsac:8; // Data read access-time in CLK cycles (NSAC*100) [111:104]\r
+ UINT32 Taac:8; // Data read access-time [119:112]\r
+ UINT32 Reserved5:6; // Reserved [125:120]\r
+ UINT32 CsdStructure:2; // CSD structure [127:126]\r
+} SD_CSD2;\r
+\r
+typedef struct {\r
+ UINT32 Reserved; // Reserved [31:0]\r
+\r
+ UINT32 CmdSupport:4; // Command Support bits [35:32]\r
+ UINT32 Reserved1:6; // Reserved [41:36]\r
+ UINT32 SdSpec4:1; // Spec. Version 4.00 or higher [42:42]\r
+ UINT32 ExSecurity:4; // Extended Security Support [46:43]\r
+ UINT32 SdSpec3:1; // Spec. Version 3.00 or higher [47:47]\r
+ UINT32 SdBusWidths:4; // DAT Bus widths supported [51:48]\r
+ UINT32 SdSecurity:3; // CPRM security support [54:52]\r
+ UINT32 DataStatAfterErase:1; // Data status after erases [55]\r
+ UINT32 SdSpec:4; // SD Memory Card Spec. Version [59:56]\r
+ UINT32 ScrStructure:4; // SCR Structure [63:60]\r
+} SD_SCR;\r
+\r
+#pragma pack()\r
+\r
+#endif\r
projects / mirror_edk2.git / commitdiff