UefiCpuPkg/CpuDxe: Add support for PCD PcdPteMemoryEncryptionAddressOrMask

This PCD holds the address mask for page table entries when memory
encryption is enabled on AMD processors supporting the Secure Encrypted
Virtualization (SEV) feature.

The mask is applied when page tables entries are created or modified.

CC: Jeff Fan <jeff.fan@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Brijesh Singh <brijesh.singh@amd.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Leo Duran <leo.duran@amd.com>
Reviewed-by: Jeff Fan <jeff.fan@intel.com>

diff --git a/UefiCpuPkg/CpuDxe/CpuDxe.inf b/UefiCpuPkg/CpuDxe/CpuDxe.inf
index e568ceb53edfb0b1aafc81b06eb0a6a2ff7bdc37..3e8d1967395bddd699ce5d7b2fd7beb7e48bbdf4 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuDxe.inf
+++ b/UefiCpuPkg/CpuDxe/CpuDxe.inf
@@ -2,6 +2,8 @@
 #  CPU driver installs CPU Architecture Protocol and CPU MP protocol.\r
 #\r
 #  Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r
 #  CPU driver installs CPU Architecture Protocol and CPU MP protocol.\r
 #\r
 #  Copyright (c) 2008 - 2017, Intel Corporation. All rights reserved.<BR>\r

+#  Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+#\r

 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #  which accompanies this distribution.  The full text of the license may be found at\r
 #  This program and the accompanying materials\r
 #  are licensed and made available under the terms and conditions of the BSD License\r
 #  which accompanies this distribution.  The full text of the license may be found at\r


@@ -77,6 +79,9 @@
   gEfiSecPlatformInformation2PpiGuid            ## UNDEFINED # HOB\r
   gEfiSecPlatformInformationPpiGuid             ## UNDEFINED # HOB\r
 \r
   gEfiSecPlatformInformation2PpiGuid            ## UNDEFINED # HOB\r
   gEfiSecPlatformInformationPpiGuid             ## UNDEFINED # HOB\r
 \r

+[Pcd]\r
+  gEfiMdeModulePkgTokenSpaceGuid.PcdPteMemoryEncryptionAddressOrMask    ## CONSUMES\r
+\r

 [Depex]\r
   TRUE\r
 \r
 [Depex]\r
   TRUE\r
 \r

diff --git a/UefiCpuPkg/CpuDxe/CpuPageTable.c b/UefiCpuPkg/CpuDxe/CpuPageTable.c
index 202d1d9b64c8263b9168a7cedac806f0541f5324..65f607a90c3d1b31cae5017e628b664fda6742aa 100644 (file)
--- a/UefiCpuPkg/CpuDxe/CpuPageTable.c
+++ b/UefiCpuPkg/CpuDxe/CpuPageTable.c
@@ -2,6 +2,8 @@
   Page table management support.\r
 \r
   Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
   Page table management support.\r
 \r
   Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r

+  Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r
+\r

   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r
   This program and the accompanying materials\r
   are licensed and made available under the terms and conditions of the BSD License\r
   which accompanies this distribution.  The full text of the license may be found at\r


@@ -271,6 +273,7 @@ GetPageTableEntry (
   UINT64                *L2PageTable;\r
   UINT64                *L3PageTable;\r
   UINT64                *L4PageTable;\r
   UINT64                *L2PageTable;\r
   UINT64                *L3PageTable;\r
   UINT64                *L4PageTable;\r

+  UINT64                AddressEncMask;\r

 \r
   ASSERT (PagingContext != NULL);\r
 \r
 \r
   ASSERT (PagingContext != NULL);\r
 \r


@@ -279,6 +282,10 @@ GetPageTableEntry (
   Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;\r
   Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;\r
 \r
   Index2 = ((UINTN)Address >> 21) & PAGING_PAE_INDEX_MASK;\r
   Index1 = ((UINTN)Address >> 12) & PAGING_PAE_INDEX_MASK;\r
 \r

+  // Make sure AddressEncMask is contained to smallest supported address field.\r
+  //\r
+  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
+\r

   if (PagingContext->MachineType == IMAGE_FILE_MACHINE_X64) {\r
     L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;\r
     if (L4PageTable[Index4] == 0) {\r
   if (PagingContext->MachineType == IMAGE_FILE_MACHINE_X64) {\r
     L4PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.X64.PageTableBase;\r
     if (L4PageTable[Index4] == 0) {\r


@@ -286,7 +293,7 @@ GetPageTableEntry (
       return NULL;\r
     }\r
 \r
       return NULL;\r
     }\r
 \r

-    L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & PAGING_4K_ADDRESS_MASK_64);\r
+    L3PageTable = (UINT64 *)(UINTN)(L4PageTable[Index4] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r

   } else {\r
     ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0);\r
     L3PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageTableBase;\r
   } else {\r
     ASSERT((PagingContext->ContextData.Ia32.Attributes & PAGE_TABLE_LIB_PAGING_CONTEXT_IA32_X64_ATTRIBUTES_PAE) != 0);\r
     L3PageTable = (UINT64 *)(UINTN)PagingContext->ContextData.Ia32.PageTableBase;\r


@@ -301,7 +308,7 @@ GetPageTableEntry (
     return &L3PageTable[Index3];\r
   }\r
 \r
     return &L3PageTable[Index3];\r
   }\r
 \r

-  L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & PAGING_4K_ADDRESS_MASK_64);\r
+  L2PageTable = (UINT64 *)(UINTN)(L3PageTable[Index3] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r

   if (L2PageTable[Index2] == 0) {\r
     *PageAttribute = PageNone;\r
     return NULL;\r
   if (L2PageTable[Index2] == 0) {\r
     *PageAttribute = PageNone;\r
     return NULL;\r


@@ -313,7 +320,7 @@ GetPageTableEntry (
   }\r
 \r
   // 4k\r
   }\r
 \r
   // 4k\r

-  L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & PAGING_4K_ADDRESS_MASK_64);\r
+  L1PageTable = (UINT64 *)(UINTN)(L2PageTable[Index2] & ~AddressEncMask & PAGING_4K_ADDRESS_MASK_64);\r

   if ((L1PageTable[Index1] == 0) && (Address != 0)) {\r
     *PageAttribute = PageNone;\r
     return NULL;\r
   if ((L1PageTable[Index1] == 0) && (Address != 0)) {\r
     *PageAttribute = PageNone;\r
     return NULL;\r


@@ -499,11 +506,16 @@ SplitPage (
   UINT64   BaseAddress;\r
   UINT64   *NewPageEntry;\r
   UINTN    Index;\r
   UINT64   BaseAddress;\r
   UINT64   *NewPageEntry;\r
   UINTN    Index;\r

+  UINT64   AddressEncMask;\r

 \r
   ASSERT (PageAttribute == Page2M || PageAttribute == Page1G);\r
 \r
   ASSERT (AllocatePagesFunc != NULL);\r
 \r
 \r
   ASSERT (PageAttribute == Page2M || PageAttribute == Page1G);\r
 \r
   ASSERT (AllocatePagesFunc != NULL);\r
 \r

+  // Make sure AddressEncMask is contained to smallest supported address field.\r
+  //\r
+  AddressEncMask = PcdGet64 (PcdPteMemoryEncryptionAddressOrMask) & PAGING_1G_ADDRESS_MASK_64;\r
+\r

   if (PageAttribute == Page2M) {\r
     //\r
     // Split 2M to 4K\r
   if (PageAttribute == Page2M) {\r
     //\r
     // Split 2M to 4K\r


@@ -515,11 +527,11 @@ SplitPage (
       if (NewPageEntry == NULL) {\r
         return RETURN_OUT_OF_RESOURCES;\r
       }\r
       if (NewPageEntry == NULL) {\r
         return RETURN_OUT_OF_RESOURCES;\r
       }\r

-      BaseAddress = *PageEntry & PAGING_2M_ADDRESS_MASK_64;\r
+      BaseAddress = *PageEntry & ~AddressEncMask & PAGING_2M_ADDRESS_MASK_64;\r

       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r
       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r

-        NewPageEntry[Index] = BaseAddress + SIZE_4KB * Index + ((*PageEntry) & PAGE_PROGATE_BITS);\r
+        NewPageEntry[Index] = (BaseAddress + SIZE_4KB * Index) | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);\r

       }\r
       }\r

-      (*PageEntry) = (UINT64)(UINTN)NewPageEntry + ((*PageEntry) & PAGE_PROGATE_BITS);\r
+      (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);\r

       return RETURN_SUCCESS;\r
     } else {\r
       return RETURN_UNSUPPORTED;\r
       return RETURN_SUCCESS;\r
     } else {\r
       return RETURN_UNSUPPORTED;\r


@@ -536,11 +548,11 @@ SplitPage (
       if (NewPageEntry == NULL) {\r
         return RETURN_OUT_OF_RESOURCES;\r
       }\r
       if (NewPageEntry == NULL) {\r
         return RETURN_OUT_OF_RESOURCES;\r
       }\r

-      BaseAddress = *PageEntry & PAGING_1G_ADDRESS_MASK_64;\r
+      BaseAddress = *PageEntry & ~AddressEncMask  & PAGING_1G_ADDRESS_MASK_64;\r

       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r
       for (Index = 0; Index < SIZE_4KB / sizeof(UINT64); Index++) {\r

-        NewPageEntry[Index] = BaseAddress + SIZE_2MB * Index + IA32_PG_PS + ((*PageEntry) & PAGE_PROGATE_BITS);\r
+        NewPageEntry[Index] = (BaseAddress + SIZE_2MB * Index) | AddressEncMask | IA32_PG_PS | ((*PageEntry) & PAGE_PROGATE_BITS);\r

       }\r
       }\r

-      (*PageEntry) = (UINT64)(UINTN)NewPageEntry + ((*PageEntry) & PAGE_PROGATE_BITS);\r
+      (*PageEntry) = (UINT64)(UINTN)NewPageEntry | AddressEncMask | ((*PageEntry) & PAGE_PROGATE_BITS);\r

       return RETURN_SUCCESS;\r
     } else {\r
       return RETURN_UNSUPPORTED;\r
       return RETURN_SUCCESS;\r
     } else {\r
       return RETURN_UNSUPPORTED;\r