--- /dev/null
+/** @file\r
+ This file implement the MMC Host Protocol for the ARM PrimeCell PL180.\r
+\r
+ Copyright (c) 2011, ARM Limited. All rights reserved.\r
+ \r
+ This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+**/\r
+\r
+#include "PL180Mci.h"\r
+\r
+#include <Library/DevicePathLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+\r
+EFI_MMC_HOST_PROTOCOL *gpMmcHost;\r
+\r
+// Untested ...\r
+//#define USE_STREAM\r
+\r
+#define MMCI0_BLOCKLEN 512\r
+#define MMCI0_POW2_BLOCKLEN 9\r
+#define MMCI0_TIMEOUT 1000\r
+\r
+BOOLEAN\r
+MciIsPowerOn (\r
+ VOID\r
+ )\r
+{\r
+ return ((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);\r
+}\r
+\r
+EFI_STATUS\r
+MciInitialize (\r
+ VOID\r
+ )\r
+{\r
+ MCI_TRACE("MciInitialize()");\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+BOOLEAN\r
+MciIsCardPresent (\r
+ VOID\r
+ )\r
+{\r
+ return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 1);\r
+}\r
+\r
+BOOLEAN\r
+MciIsReadOnly (\r
+ VOID\r
+ )\r
+{\r
+ return (MmioRead32(FixedPcdGet32(PcdPL180SysMciRegAddress)) & 2);\r
+}\r
+\r
+#if 0\r
+//Note: This function has been commented out because it is not used yet.\r
+// This function could be used to remove the hardcoded BlockLen used\r
+// in MciPrepareDataPath\r
+\r
+// Convert block size to 2^n\r
+STATIC\r
+UINT32\r
+GetPow2BlockLen (\r
+ IN UINT32 BlockLen\r
+ )\r
+{\r
+ UINTN Loop;\r
+ UINTN Pow2BlockLen;\r
+\r
+ Loop = 0x8000;\r
+ Pow2BlockLen = 15;\r
+ do {\r
+ Loop = (Loop >> 1) & 0xFFFF;\r
+ Pow2BlockLen--;\r
+ } while (Pow2BlockLen && (!(Loop & BlockLen)));\r
+\r
+ return Pow2BlockLen;\r
+}\r
+#endif\r
+\r
+VOID\r
+MciPrepareDataPath (\r
+ IN UINTN TransferDirection\r
+ )\r
+{\r
+ // Set Data Length & Data Timer\r
+ MmioWrite32(MCI_DATA_TIMER_REG,0xFFFFFFF);\r
+ MmioWrite32(MCI_DATA_LENGTH_REG,MMCI0_BLOCKLEN);\r
+\r
+#ifndef USE_STREAM\r
+ //Note: we are using a hardcoded BlockLen (=512). If we decide to use a variable size, we could\r
+ // compute the pow2 of BlockLen with the above function GetPow2BlockLen()\r
+ MmioWrite32(MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | (MMCI0_POW2_BLOCKLEN << 4));\r
+#else\r
+ MmioWrite32(MCI_DATA_CTL_REG, MCI_DATACTL_ENABLE | MCI_DATACTL_DMA_ENABLE | TransferDirection | MCI_DATACTL_STREAM_TRANS);\r
+#endif\r
+}\r
+\r
+EFI_STATUS\r
+MciSendCommand (\r
+ IN MMC_CMD MmcCmd,\r
+ IN UINT32 Argument\r
+ )\r
+{\r
+ UINT32 Status;\r
+ UINT32 Cmd;\r
+ UINTN RetVal;\r
+ UINTN CmdCtrlReg;\r
+\r
+ RetVal = EFI_SUCCESS;\r
+\r
+ if ((MmcCmd == MMC_CMD17) || (MmcCmd == MMC_CMD11)) {\r
+ MciPrepareDataPath(MCI_DATACTL_CARD_TO_CONT);\r
+ } else if ((MmcCmd == MMC_CMD24) || (MmcCmd == MMC_CMD20)) {\r
+ MciPrepareDataPath(MCI_DATACTL_CONT_TO_CARD);\r
+ }\r
+\r
+ // Create Command for PL180\r
+ Cmd = (MMC_GET_INDX(MmcCmd) & INDX_MASK) | MCI_CPSM_ENABLED;\r
+ if (MmcCmd & MMC_CMD_WAIT_RESPONSE) {\r
+ Cmd |= MCI_CPSM_WAIT_RESPONSE;\r
+ }\r
+\r
+ if (MmcCmd & MMC_CMD_LONG_RESPONSE) {\r
+ Cmd |= MCI_CPSM_LONG_RESPONSE;\r
+ }\r
+\r
+ // Clear Status register static flags\r
+ MmioWrite32(MCI_CLEAR_STATUS_REG,0x7FF);\r
+\r
+ //Write to command argument register\r
+ MmioWrite32(MCI_ARGUMENT_REG,Argument);\r
+\r
+ //Write to command register\r
+ MmioWrite32(MCI_COMMAND_REG,Cmd);\r
+\r
+ if (Cmd & MCI_CPSM_WAIT_RESPONSE) {\r
+ Status = MmioRead32(MCI_STATUS_REG);\r
+ while (!(Status & (MCI_STATUS_CMD_RESPEND | MCI_STATUS_CMD_CMDCRCFAIL | MCI_STATUS_CMD_CMDTIMEOUT | MCI_STATUS_CMD_START_BIT_ERROR))) {\r
+ Status = MmioRead32(MCI_STATUS_REG);\r
+ }\r
+\r
+ if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) {\r
+ DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
+ RetVal = EFI_NO_RESPONSE;\r
+ goto Exit;\r
+ } else if ((Status & MCI_STATUS_CMD_CMDTIMEOUT)) {\r
+ //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
+ RetVal = EFI_TIMEOUT;\r
+ goto Exit;\r
+ } else if ((!(MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {\r
+ // The CMD1 and response type R3 do not contain CRC. We should ignore the CRC failed Status.\r
+ RetVal = EFI_CRC_ERROR;\r
+ goto Exit;\r
+ } else {\r
+ RetVal = EFI_SUCCESS;\r
+ goto Exit;\r
+ }\r
+ } else {\r
+ Status = MmioRead32(MCI_STATUS_REG);\r
+ while (!(Status & (MCI_STATUS_CMD_SENT | MCI_STATUS_CMD_CMDCRCFAIL | MCI_STATUS_CMD_CMDTIMEOUT| MCI_STATUS_CMD_START_BIT_ERROR))) {\r
+ Status = MmioRead32(MCI_STATUS_REG);\r
+ }\r
+\r
+ if ((Status & MCI_STATUS_CMD_START_BIT_ERROR)) {\r
+ DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) Start bit Error! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
+ RetVal = EFI_NO_RESPONSE;\r
+ goto Exit;\r
+ } else if ((Status & MCI_STATUS_CMD_CMDTIMEOUT)) {\r
+ //DEBUG ((EFI_D_ERROR, "MciSendCommand(CmdIndex:%d) TIMEOUT! Response:0x%X Status:0x%x\n",(Cmd & 0x3F),MmioRead32(MCI_RESPONSE0_REG),Status));\r
+ RetVal = EFI_TIMEOUT;\r
+ goto Exit;\r
+ } else\r
+ if ((!(MmcCmd & MMC_CMD_NO_CRC_RESPONSE)) && (Status & MCI_STATUS_CMD_CMDCRCFAIL)) {\r
+ // The CMD1 does not contain CRC. We should ignore the CRC failed Status.\r
+ RetVal = EFI_CRC_ERROR;\r
+ goto Exit;\r
+ } else {\r
+ RetVal = EFI_SUCCESS;\r
+ goto Exit;\r
+ }\r
+ }\r
+\r
+Exit:\r
+ //Disable Command Path\r
+ CmdCtrlReg = MmioRead32(MCI_COMMAND_REG);\r
+ MmioWrite32(MCI_COMMAND_REG, (CmdCtrlReg & ~MCI_CPSM_ENABLED));\r
+ return RetVal;\r
+}\r
+\r
+EFI_STATUS\r
+MciReceiveResponse (\r
+ IN MMC_RESPONSE_TYPE Type,\r
+ IN UINT32* Buffer\r
+ )\r
+{\r
+ if (Buffer == NULL) {\r
+ return EFI_INVALID_PARAMETER;\r
+ }\r
+\r
+ if ((Type == MMC_RESPONSE_TYPE_R1) || (Type == MMC_RESPONSE_TYPE_R1b) ||\r
+ (Type == MMC_RESPONSE_TYPE_R3) || (Type == MMC_RESPONSE_TYPE_R6) ||\r
+ (Type == MMC_RESPONSE_TYPE_R7))\r
+ {\r
+ Buffer[0] = MmioRead32(MCI_RESPONSE0_REG);\r
+ Buffer[1] = MmioRead32(MCI_RESPONSE1_REG);\r
+ } else if (Type == MMC_RESPONSE_TYPE_R2) {\r
+ Buffer[0] = MmioRead32(MCI_RESPONSE0_REG);\r
+ Buffer[1] = MmioRead32(MCI_RESPONSE1_REG);\r
+ Buffer[2] = MmioRead32(MCI_RESPONSE2_REG);\r
+ Buffer[3] = MmioRead32(MCI_RESPONSE3_REG);\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_STATUS\r
+MciReadBlockData (\r
+ IN EFI_LBA Lba,\r
+ IN UINTN Length,\r
+ IN UINT32* Buffer\r
+ )\r
+{\r
+ UINTN Loop;\r
+ UINTN Finish;\r
+ UINTN Status;\r
+ EFI_STATUS RetVal;\r
+ UINTN DataCtrlReg;\r
+\r
+ RetVal = EFI_SUCCESS;\r
+\r
+ // Read data from the RX FIFO\r
+ Loop = 0;\r
+ Finish = MMCI0_BLOCKLEN / 4;\r
+ do {\r
+ // Read the Status flags\r
+ Status = MmioRead32(MCI_STATUS_REG);\r
+\r
+ // Do eight reads if possible else a single read\r
+ if (Status & MCI_STATUS_CMD_RXFIFOHALFFULL) {\r
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
+ Loop++;\r
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
+ Loop++;\r
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
+ Loop++;\r
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
+ Loop++;\r
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
+ Loop++;\r
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
+ Loop++;\r
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
+ Loop++;\r
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
+ Loop++;\r
+ } else if (Status & MCI_STATUS_CMD_RXDATAAVAILBL) {\r
+ Buffer[Loop] = MmioRead32(MCI_FIFO_REG);\r
+ Loop++;\r
+ } else {\r
+ //Check for error conditions and timeouts\r
+ if(Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
+ DEBUG ((EFI_D_ERROR, "MciReadBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+ RetVal = EFI_TIMEOUT;\r
+ break;\r
+ } else if(Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
+ DEBUG ((EFI_D_ERROR, "MciReadBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+ RetVal = EFI_CRC_ERROR;\r
+ break;\r
+ } else if(Status & MCI_STATUS_CMD_START_BIT_ERROR) {\r
+ DEBUG ((EFI_D_ERROR, "MciReadBlockData(): Start-bit Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+ RetVal = EFI_NO_RESPONSE;\r
+ break;\r
+ }\r
+ }\r
+ //clear RX over run flag\r
+ if(Status & MCI_STATUS_CMD_RXOVERRUN) {\r
+ MmioWrite32(MCI_CLEAR_STATUS_REG, MCI_STATUS_CMD_RXOVERRUN);\r
+ }\r
+ } while ((Loop < Finish));\r
+\r
+ //Clear Status flags\r
+ MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF);\r
+\r
+ //Disable Data path\r
+ DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG);\r
+ MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE));\r
+\r
+ return RetVal;\r
+}\r
+\r
+EFI_STATUS\r
+MciWriteBlockData (\r
+ IN EFI_LBA Lba,\r
+ IN UINTN Length,\r
+ IN UINT32* Buffer\r
+ )\r
+{\r
+ UINTN Loop;\r
+ UINTN Finish;\r
+ UINTN Timer;\r
+ UINTN Status;\r
+ EFI_STATUS RetVal;\r
+ UINTN DataCtrlReg;\r
+\r
+ RetVal = EFI_SUCCESS;\r
+\r
+ // Write the data to the TX FIFO\r
+ Loop = 0;\r
+ Finish = MMCI0_BLOCKLEN / 4;\r
+ Timer = MMCI0_TIMEOUT * 100;\r
+ do {\r
+ // Read the Status flags\r
+ Status = MmioRead32(MCI_STATUS_REG);\r
+\r
+ // Do eight writes if possible else a single write\r
+ if (Status & MCI_STATUS_CMD_TXFIFOHALFEMPTY) {\r
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
+ Loop++;\r
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
+ Loop++;\r
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
+ Loop++;\r
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
+ Loop++;\r
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
+ Loop++;\r
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
+ Loop++;\r
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
+ Loop++;\r
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
+ Loop++;\r
+ } else if ((Status & MCI_STATUS_CMD_TXFIFOEMPTY)) {\r
+ MmioWrite32(MCI_FIFO_REG, Buffer[Loop]);\r
+ Loop++;\r
+ } else {\r
+ //Check for error conditions and timeouts\r
+ if(Status & MCI_STATUS_CMD_DATATIMEOUT) {\r
+ DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TIMEOUT! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+ RetVal = EFI_TIMEOUT;\r
+ goto Exit;\r
+ } else if(Status & MCI_STATUS_CMD_DATACRCFAIL) {\r
+ DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): CRC Error! Response:0x%X Status:0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status));\r
+ RetVal = EFI_CRC_ERROR;\r
+ goto Exit;\r
+ } else if(Status & MCI_STATUS_CMD_TX_UNDERRUN) {\r
+ DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): TX buffer Underrun! Response:0x%X Status:0x%x, Number of bytes written 0x%x\n",MmioRead32(MCI_RESPONSE0_REG),Status, Loop));\r
+ RetVal = EFI_BUFFER_TOO_SMALL;\r
+ ASSERT(0);\r
+ goto Exit;\r
+ }\r
+ }\r
+ } while (Loop < Finish);\r
+\r
+ // Wait for FIFO to drain\r
+ Timer = MMCI0_TIMEOUT * 60;\r
+ Status = MmioRead32(MCI_STATUS_REG);\r
+#ifndef USE_STREAM\r
+ // Single block\r
+ while (((Status & MCI_STATUS_CMD_TXDONE) != MCI_STATUS_CMD_TXDONE) && Timer) {\r
+#else\r
+ // Stream\r
+ while (((Status & MCI_STATUS_CMD_DATAEND) != MCI_STATUS_CMD_DATAEND) && Timer) {\r
+#endif\r
+ NanoSecondDelay(10);\r
+ Status = MmioRead32(MCI_STATUS_REG);\r
+ Timer--;\r
+ }\r
+\r
+ if(Timer == 0) {\r
+ DEBUG ((EFI_D_ERROR, "MciWriteBlockData(): Data End timeout Number of bytes written 0x%x\n",Loop));\r
+ ASSERT(Timer > 0);\r
+ return EFI_TIMEOUT;\r
+ }\r
+\r
+ //Clear Status flags\r
+ MmioWrite32(MCI_CLEAR_STATUS_REG, 0x7FF);\r
+ if (Timer == 0) {\r
+ RetVal = EFI_TIMEOUT;\r
+ }\r
+\r
+Exit:\r
+ //Disable Data path\r
+ DataCtrlReg = MmioRead32(MCI_DATA_CTL_REG);\r
+ MmioWrite32(MCI_DATA_CTL_REG, (DataCtrlReg & 0xFE));\r
+ return RetVal;\r
+}\r
+\r
+EFI_STATUS\r
+MciNotifyState (\r
+ IN MMC_STATE State\r
+ )\r
+{\r
+ UINT32 Data32;\r
+\r
+ switch(State) {\r
+ case MmcInvalidState:\r
+ ASSERT(0);\r
+ break;\r
+ case MmcHwInitializationState:\r
+ // If device already turn on then restart it\r
+ Data32 = MmioRead32(MCI_POWER_CONTROL_REG);\r
+ if ((Data32 & 0x2) == MCI_POWER_UP) {\r
+ MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOff MCI");\r
+\r
+ // Turn off\r
+ MmioWrite32(MCI_CLOCK_CONTROL_REG, 0);\r
+ MmioWrite32(MCI_POWER_CONTROL_REG, 0);\r
+ MicroSecondDelay(100);\r
+ }\r
+\r
+ MCI_TRACE("MciNotifyState(MmcHwInitializationState): TurnOn MCI");\r
+ // Setup clock\r
+ // - 0x1D = 29 => should be the clock divider to be less than 400kHz at MCLK = 24Mhz\r
+ MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);\r
+ //MmioWrite32(MCI_CLOCK_CONTROL_REG,0x1D | MCI_CLOCK_ENABLE);\r
+\r
+ // Set the voltage\r
+ MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_OPENDRAIN | (15<<2));\r
+ MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_UP);\r
+ MicroSecondDelay(10);\r
+ MmioWrite32(MCI_POWER_CONTROL_REG,MCI_POWER_ROD | MCI_POWER_OPENDRAIN | (15<<2) | MCI_POWER_ON);\r
+ MicroSecondDelay(100);\r
+\r
+ // Set Data Length & Data Timer\r
+ MmioWrite32(MCI_DATA_TIMER_REG,0xFFFFF);\r
+ MmioWrite32(MCI_DATA_LENGTH_REG,8);\r
+\r
+ ASSERT((MmioRead32(MCI_POWER_CONTROL_REG) & 0x3) == MCI_POWER_ON);\r
+ break;\r
+ case MmcIdleState:\r
+ MCI_TRACE("MciNotifyState(MmcIdleState)");\r
+ break;\r
+ case MmcReadyState:\r
+ MCI_TRACE("MciNotifyState(MmcReadyState)");\r
+ break;\r
+ case MmcIdentificationState:\r
+ MCI_TRACE("MciNotifyState(MmcIdentificationState)");\r
+ break;\r
+ case MmcStandByState:{\r
+ volatile UINT32 PwrCtrlReg;\r
+ MCI_TRACE("MciNotifyState(MmcStandByState)");\r
+\r
+ // Enable MCICMD push-pull drive\r
+ PwrCtrlReg = MmioRead32(MCI_POWER_CONTROL_REG);\r
+ //Disable Open Drain output\r
+ PwrCtrlReg &=~(MCI_POWER_OPENDRAIN);\r
+ MmioWrite32(MCI_POWER_CONTROL_REG,PwrCtrlReg);\r
+\r
+ // Set MMCI0 clock to 4MHz (24MHz may be possible with cache enabled)\r
+ //\r
+ // Note: Increasing clock speed causes TX FIFO under-run errors.\r
+ // So careful when optimising this driver for higher performance.\r
+ //\r
+ MmioWrite32(MCI_CLOCK_CONTROL_REG,0x02 | MCI_CLOCK_ENABLE | MCI_CLOCK_POWERSAVE);\r
+ // Set MMCI0 clock to 24MHz (by bypassing the divider)\r
+ //MmioWrite32(MCI_CLOCK_CONTROL_REG,MCI_CLOCK_BYPASS | MCI_CLOCK_ENABLE);\r
+ break;\r
+ }\r
+ case MmcTransferState:\r
+ //MCI_TRACE("MciNotifyState(MmcTransferState)");\r
+ break;\r
+ case MmcSendingDataState:\r
+ MCI_TRACE("MciNotifyState(MmcSendingDataState)");\r
+ break;\r
+ case MmcReceiveDataState:\r
+ MCI_TRACE("MciNotifyState(MmcReceiveDataState)");\r
+ break;\r
+ case MmcProgrammingState:\r
+ MCI_TRACE("MciNotifyState(MmcProgrammingState)");\r
+ break;\r
+ case MmcDisconnectState:\r
+ MCI_TRACE("MciNotifyState(MmcDisconnectState)");\r
+ break;\r
+ default:\r
+ ASSERT(0);\r
+ }\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_GUID mPL180MciDevicePathGuid = EFI_CALLER_ID_GUID;\r
+\r
+EFI_STATUS\r
+MciBuildDevicePath (\r
+ IN EFI_DEVICE_PATH_PROTOCOL **DevicePath\r
+ )\r
+{\r
+ EFI_DEVICE_PATH_PROTOCOL *NewDevicePathNode;\r
+\r
+ NewDevicePathNode = CreateDeviceNode(HARDWARE_DEVICE_PATH,HW_VENDOR_DP,sizeof(VENDOR_DEVICE_PATH));\r
+ CopyGuid(&((VENDOR_DEVICE_PATH*)NewDevicePathNode)->Guid,&mPL180MciDevicePathGuid);\r
+\r
+ *DevicePath = NewDevicePathNode;\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+EFI_MMC_HOST_PROTOCOL gMciHost = {\r
+ MciIsCardPresent,\r
+ MciIsReadOnly,\r
+ MciBuildDevicePath,\r
+ MciNotifyState,\r
+ MciSendCommand,\r
+ MciReceiveResponse,\r
+ MciReadBlockData,\r
+ MciWriteBlockData\r
+};\r
+\r
+EFI_STATUS\r
+PL180MciDxeInitialize (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ EFI_HANDLE Handle = NULL;\r
+\r
+ MCI_TRACE("PL180MciDxeInitialize()");\r
+\r
+ //Publish Component Name, BlockIO protocol interfaces\r
+ Status = gBS->InstallMultipleProtocolInterfaces (\r
+ &Handle, \r
+ &gEfiMmcHostProtocolGuid, &gMciHost,\r
+ NULL\r
+ );\r
+ ASSERT_EFI_ERROR (Status);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+ Header for the MMC Host Protocol implementation for the ARM PrimeCell PL180.\r
+\r
+ Copyright (c) 2011, ARM Limited. All rights reserved.\r
+ \r
+ This program and the accompanying materials \r
+ are licensed and made available under the terms and conditions of the BSD License \r
+ which accompanies this distribution. The full text of the license may be found at \r
+ http://opensource.org/licenses/bsd-license.php \r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+\r
+**/\r
+\r
+#ifndef __PL180_MCI_H\r
+#define __PL180_MCI_H\r
+\r
+#include <Uefi.h>\r
+\r
+#include <Protocol/MmcHost.h>\r
+\r
+#include <Library/UefiLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Library/IoLib.h>\r
+#include <Library/TimerLib.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#define PL180_MCI_DXE_VERSION 0x10\r
+\r
+#define MCI_SYSCTL FixedPcdGet32(PcdPL180MciBaseAddress)\r
+\r
+#define MCI_POWER_CONTROL_REG (MCI_SYSCTL+0x000)\r
+#define MCI_CLOCK_CONTROL_REG (MCI_SYSCTL+0x004)\r
+#define MCI_ARGUMENT_REG (MCI_SYSCTL+0x008)\r
+#define MCI_COMMAND_REG (MCI_SYSCTL+0x00C)\r
+#define MCI_RESPCMD_REG (MCI_SYSCTL+0x010)\r
+#define MCI_RESPONSE0_REG (MCI_SYSCTL+0x014)\r
+#define MCI_RESPONSE1_REG (MCI_SYSCTL+0x018)\r
+#define MCI_RESPONSE2_REG (MCI_SYSCTL+0x01C)\r
+#define MCI_RESPONSE3_REG (MCI_SYSCTL+0x020)\r
+#define MCI_DATA_TIMER_REG (MCI_SYSCTL+0x024)\r
+#define MCI_DATA_LENGTH_REG (MCI_SYSCTL+0x028)\r
+#define MCI_DATA_CTL_REG (MCI_SYSCTL+0x02C)\r
+#define MCI_DATA_COUNTER (MCI_SYSCTL+0x030)\r
+#define MCI_STATUS_REG (MCI_SYSCTL+0x034)\r
+#define MCI_CLEAR_STATUS_REG (MCI_SYSCTL+0x038)\r
+#define MCI_INT0_MASK_REG (MCI_SYSCTL+0x03C)\r
+#define MCI_INT1_MASK_REG (MCI_SYSCTL+0x040)\r
+#define MCI_FIFOCOUNT_REG (MCI_SYSCTL+0x048)\r
+#define MCI_FIFO_REG (MCI_SYSCTL+0x080)\r
+\r
+#define MCI_POWER_UP 0x2\r
+#define MCI_POWER_ON 0x3\r
+#define MCI_POWER_OPENDRAIN (1 << 6)\r
+#define MCI_POWER_ROD (1 << 7)\r
+\r
+#define MCI_CLOCK_ENABLE 0x100\r
+#define MCI_CLOCK_POWERSAVE 0x200\r
+#define MCI_CLOCK_BYPASS 0x400\r
+\r
+#define MCI_STATUS_CMD_CMDCRCFAIL 0x1\r
+#define MCI_STATUS_CMD_DATACRCFAIL 0x2\r
+#define MCI_STATUS_CMD_CMDTIMEOUT 0x4\r
+#define MCI_STATUS_CMD_DATATIMEOUT 0x8\r
+#define MCI_STATUS_CMD_TX_UNDERRUN 0x10\r
+#define MCI_STATUS_CMD_RXOVERRUN 0x20\r
+#define MCI_STATUS_CMD_RESPEND 0x40\r
+#define MCI_STATUS_CMD_SENT 0x80\r
+#define MCI_STATUS_CMD_TXDONE (MCI_STATUS_CMD_DATAEND | MCI_STATUS_CMD_DATABLOCKEND)\r
+#define MCI_STATUS_CMD_DATAEND 0x000100 // Command Status - Data end\r
+#define MCI_STATUS_CMD_START_BIT_ERROR 0x000200\r
+#define MCI_STATUS_CMD_DATABLOCKEND 0x000400 // Command Status - Data end\r
+#define MCI_STATUS_CMD_ACTIVE 0x800\r
+#define MCI_STATUS_CMD_RXACTIVE (1 << 13)\r
+#define MCI_STATUS_CMD_RXFIFOHALFFULL 0x008000\r
+#define MCI_STATUS_CMD_RXFIFOEMPTY 0x080000\r
+#define MCI_STATUS_CMD_RXDATAAVAILBL (1 << 21)\r
+#define MCI_STATUS_CMD_TXACTIVE (1 << 12)\r
+#define MCI_STATUS_CMD_TXFIFOFULL (1 << 16)\r
+#define MCI_STATUS_CMD_TXFIFOHALFEMPTY (1 << 14)\r
+#define MCI_STATUS_CMD_TXFIFOEMPTY (1 << 18)\r
+#define MCI_STATUS_CMD_TXDATAAVAILBL (1 << 20)\r
+\r
+#define MCI_DATACTL_ENABLE 1\r
+#define MCI_DATACTL_CONT_TO_CARD 0\r
+#define MCI_DATACTL_CARD_TO_CONT 2\r
+#define MCI_DATACTL_BLOCK_TRANS 0\r
+#define MCI_DATACTL_STREAM_TRANS 4\r
+#define MCI_DATACTL_DMA_ENABLE (1 << 3)\r
+\r
+#define INDX_MASK 0x3F\r
+\r
+#define MCI_CPSM_ENABLED (1 << 10)\r
+#define MCI_CPSM_WAIT_RESPONSE (1 << 6)\r
+#define MCI_CPSM_LONG_RESPONSE (1 << 7)\r
+\r
+#define MCI_TRACE(txt) DEBUG((EFI_D_BLKIO, "ARM_MCI: " txt "\n"))\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+MciGetDriverName (\r
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
+ IN CHAR8 *Language,\r
+ OUT CHAR16 **DriverName\r
+ );\r
+\r
+EFI_STATUS\r
+EFIAPI\r
+MciGetControllerName (\r
+ IN EFI_COMPONENT_NAME_PROTOCOL *This,\r
+ IN EFI_HANDLE ControllerHandle,\r
+ IN EFI_HANDLE ChildHandle OPTIONAL,\r
+ IN CHAR8 *Language,\r
+ OUT CHAR16 **ControllerName\r
+ );\r
+\r
+#endif\r
--- /dev/null
+#/** @file\r
+# INF file for the MMC Host Protocol implementation for the ARM PrimeCell PL180.\r
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#**/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL180MciDxe\r
+ FILE_GUID = 09831032-6fa3-4484-af4f-0a000a8d3a82\r
+ MODULE_TYPE = DXE_DRIVER\r
+ VERSION_STRING = 1.0\r
+\r
+ ENTRY_POINT = PL180MciDxeInitialize\r
+\r
+[Sources.common]\r
+ PL180Mci.c\r
+\r
+[Packages]\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ EmbeddedPkg/EmbeddedPkg.dec\r
+ MdePkg/MdePkg.dec\r
+\r
+[LibraryClasses]\r
+ BaseLib\r
+ UefiLib\r
+ UefiDriverEntryPoint\r
+ BaseMemoryLib\r
+ ArmLib\r
+ IoLib\r
+ TimerLib\r
+\r
+[Protocols]\r
+ gEfiCpuArchProtocolGuid\r
+ gEfiDevicePathProtocolGuid\r
+ gEfiMmcHostProtocolGuid\r
+ \r
+[Pcd]\r
+ gArmPlatformTokenSpaceGuid.PcdPL180SysMciRegAddress\r
+ gArmPlatformTokenSpaceGuid.PcdPL180MciBaseAddress\r
+ \r
+[Depex]\r
+ TRUE\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+\r
+#define PL301_QOS_TIDEMARK_MI_0 0x400\r
+#define PL301_QOS_ACCESSCONTROL_MI_0 0x404\r
+\r
+#define PL301_QOS_TIDEMARK_MI_1 0x420\r
+#define PL301_QOS_ACCESSCONTROL_MI_1 0x424\r
+\r
+#define PL301_QOS_TIDEMARK_MI_2 0x440\r
+#define PL301_QOS_ACCESSCONTROL_MI_2 0x444\r
+\r
+#define PL301_AR_ARB_MI_0 0x408\r
+#define PL301_AW_ARB_MI_0 0x40C\r
+\r
+#define PL301_AR_ARB_MI_1 0x428\r
+#define PL301_AW_ARB_MI_1 0x42C\r
+\r
+#define PL301_AR_ARB_MI_2 0x448\r
+#define PL301_AW_ARB_MI_2 0x44C\r
+\r
+#define PL301_MI_1_OFFSET 0x20\r
+#define PL301_MI_2_OFFSET 0x40\r
+#define PL301_MI_3_OFFSET 0x60\r
+#define PL301_MI_4_OFFSET 0x80\r
+#define PL301_MI_5_OFFSET 0xa0\r
+\r
+#define V2P_CA9_FAXI_MI0_TIDEMARK_VAL 0x6\r
+#define V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL 0x1\r
+\r
+#define V2P_CA9_FAXI_MI1_TIDEMARK_VAL 0x6\r
+#define V2P_CA9_FAXI_MI1_ACCESSCNTRL_VAL 0x1\r
+\r
+#define V2P_CA9_FAXI_MI2_TIDEMARK_VAL 0x6\r
+#define V2P_CA9_FAXI_MI2_ACCESSCNTRL_VAL 0x1\r
+\r
+\r
+#define FAxiWriteReg(reg,val) MmioWrite32(FAxiBase + reg, val)\r
+#define FAxiReadReg(reg) MmioRead32(FAxiBase + reg)\r
+\r
+// IN FAxiBase\r
+// Initialize PL301 Dynamic Memory Controller\r
+VOID PL301AxiInit(UINTN FAxiBase) {\r
+ // Configure Tidemark Register for Master Port 0 (MI 0)\r
+ FAxiWriteReg(PL301_QOS_TIDEMARK_MI_0, V2P_CA9_FAXI_MI0_TIDEMARK_VAL);\r
+\r
+ // Configure the Access Control Register (MI 0)\r
+ FAxiWriteReg(PL301_QOS_ACCESSCONTROL_MI_0, V2P_CA9_FAXI_MI0_ACCESSCNTRL_VAL);\r
+\r
+ // MP0 \r
+ // Set priority for Read\r
+ FAxiWriteReg(PL301_AR_ARB_MI_0, 0x00000100);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_0, 0x01000200);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_0, 0x02000200);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_0, 0x03000200);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_0, 0x04000200);\r
+ \r
+ // Set priority for Write\r
+ FAxiWriteReg(PL301_AW_ARB_MI_0, 0x00000100);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_0, 0x01000200);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_0, 0x02000200);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_0, 0x03000200);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_0, 0x04000200);\r
+\r
+ // MP1\r
+ // Set priority for Read\r
+ FAxiWriteReg(PL301_AR_ARB_MI_1, 0x00000100);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_1, 0x01000200);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_1, 0x02000200);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_1, 0x03000200);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_1, 0x04000200);\r
+\r
+ // Set priority for Write\r
+ FAxiWriteReg(PL301_AW_ARB_MI_1, 0x00000100);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_1, 0x01000200);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_1, 0x02000200);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_1, 0x03000200);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_1, 0x04000200);\r
+\r
+ // MP2\r
+ // Set priority for Read\r
+ FAxiWriteReg(PL301_AR_ARB_MI_2, 0x00000100);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_2, 0x01000100);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_2, 0x02000100);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_2, 0x03000100);\r
+ FAxiWriteReg(PL301_AR_ARB_MI_2, 0x04000100);\r
+ \r
+ // Set priority for Write\r
+ FAxiWriteReg(PL301_AW_ARB_MI_2, 0x00000100);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_2, 0x01000200);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_2, 0x02000200);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_2, 0x03000200);\r
+ FAxiWriteReg(PL301_AW_ARB_MI_2, 0x04000200);\r
+}\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL301Axi\r
+ FILE_GUID = 2ea84160-aba0-11df-9896-0002a5d5c51b\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PL301AxiLib\r
+\r
+[Sources]\r
+ PL301Axi.c\r
+\r
+[Packages]\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ MdePkg/MdePkg.dec\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/ArmLib.h>\r
+#include <Drivers/PL310L2Cache.h>\r
+#include <Library/PcdLib.h>\r
+\r
+#define L2x0WriteReg(reg,val) MmioWrite32(PcdGet32(PcdL2x0ControllerBase) + reg, val)\r
+#define L2x0ReadReg(reg) MmioRead32(PcdGet32(PcdL2x0ControllerBase) + reg)\r
+\r
+// Initialize PL320 L2 Cache Controller\r
+VOID\r
+L2x0CacheInit (\r
+ IN UINTN L2x0Base,\r
+ IN UINT32 L2x0TagLatencies,\r
+ IN UINT32 L2x0DataLatencies,\r
+ IN UINT32 L2x0AuxValue,\r
+ IN UINT32 L2x0AuxMask,\r
+ IN BOOLEAN CacheEnabled\r
+ )\r
+{\r
+ UINT32 Data;\r
+ UINT32 Revision;\r
+ UINT32 Aux;\r
+ UINT32 PfCtl;\r
+ UINT32 PwrCtl;\r
+\r
+ // Check if L2x0 is present and is an ARM implementation\r
+ Data = L2x0ReadReg(L2X0_CACHEID);\r
+ if ((Data >> 24) != L2X0_CACHEID_IMPLEMENTER_ARM) {\r
+ ASSERT(0);\r
+ return;\r
+ }\r
+\r
+ // Check if L2x0 is PL310\r
+ if (((Data >> 6) & 0xF) != L2X0_CACHEID_PARTNUM_PL310) {\r
+ ASSERT(0);\r
+ return;\r
+ }\r
+\r
+ // RTL release\r
+ Revision = Data & 0x3F;\r
+\r
+ // Check if L2x0 is already enabled then we disable it\r
+ Data = L2x0ReadReg(L2X0_CTRL);\r
+ if (Data & L2X0_CTRL_ENABLED) {\r
+ L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_DISABLED);\r
+ }\r
+\r
+ //\r
+ // Set up global configurations\r
+ //\r
+\r
+ // Auxiliary register: Non-secure interrupt access Control + Event monitor bus enable + SBO\r
+ Aux = L2X0_AUXCTRL_NSAC | L2X0_AUXCTRL_EM | L2X0_AUXCTRL_SBO;\r
+ // Use AWCACHE attributes for WA\r
+ Aux |= L2x0_AUXCTRL_AW_AWCACHE;\r
+ // Use default Size\r
+ Data = L2x0ReadReg(L2X0_AUXCTRL);\r
+ Aux |= Data & L2X0_AUXCTRL_WAYSIZE_MASK;\r
+ // Use default associativity\r
+ Aux |= Data & L2X0_AUXCTRL_ASSOCIATIVITY;\r
+ // Enabled I & D Prefetch\r
+ Aux |= L2x0_AUXCTRL_IPREFETCH | L2x0_AUXCTRL_DPREFETCH;\r
+\r
+ if (Revision >= 5) {\r
+ // Prefetch Offset Register\r
+ PfCtl = L2x0ReadReg(L2X0_PFCTRL);\r
+ // - Prefetch increment set to 0\r
+ // - Prefetch dropping off\r
+ // - Double linefills off\r
+ L2x0WriteReg(L2X0_PFCTRL, PfCtl);\r
+\r
+ // Power Control Register - L2X0_PWRCTRL\r
+ PwrCtl = L2x0ReadReg(L2X0_PWRCTRL);\r
+ // - Standby when idle off\r
+ // - Dynamic clock gating off\r
+ // - Nc,NC-shared dropping off\r
+ L2x0WriteReg(L2X0_PWRCTRL, PwrCtl);\r
+ }\r
+\r
+ if (Revision >= 2) {\r
+ L2x0WriteReg(L230_TAG_LATENCY, L2x0TagLatencies);\r
+ L2x0WriteReg(L230_DATA_LATENCY, L2x0DataLatencies);\r
+ } else {\r
+ // PL310 old style latency is not supported yet\r
+ ASSERT(0);\r
+ }\r
+\r
+ // Set the platform specific values\r
+ Aux = (Aux & L2x0AuxMask) | L2x0AuxValue;\r
+\r
+ // Write Auxiliary value\r
+ L2x0WriteReg(L2X0_AUXCTRL, Aux);\r
+\r
+ //\r
+ // Invalidate all entries in cache\r
+ //\r
+ L2x0WriteReg(L2X0_INVWAY, 0xffff);\r
+ // Poll cache maintenance register until invalidate operation is complete\r
+ while(L2x0ReadReg(L2X0_INVWAY) & 0xffff);\r
+\r
+ // Write to the Lockdown D and Lockdown I Register 9 if required\r
+ // - Not required\r
+\r
+ // Clear any residual raw interrupts\r
+ L2x0WriteReg(L2X0_INTCLEAR, 0x1FF);\r
+\r
+ // Enable the cache\r
+ if (CacheEnabled) {\r
+ L2x0WriteReg(L2X0_CTRL, L2X0_CTRL_ENABLED);\r
+ }\r
+}\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL310L2Cache\r
+ FILE_GUID = 16ad4fe0-b5b1-11df-8cbf-0002a5d5c51b\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = L2X0CacheLib\r
+\r
+[Sources]\r
+ PL310L2Cache.c\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ MdePkg/MdePkg.dec\r
+\r
+[FixedPcd]\r
+ gArmTokenSpaceGuid.PcdL2x0ControllerBase\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Library/IoLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Drivers/PL341Dmc.h>\r
+\r
+// Macros for writing to DDR2 controller.\r
+#define DmcWriteReg(reg,val) MmioWrite32(DmcBase + reg, val)\r
+#define DmcReadReg(reg) MmioRead32(DmcBase + reg)\r
+\r
+// Macros for writing/reading to DDR2 PHY controller\r
+#define DmcPhyWriteReg(reg,val) MmioWrite32(DmcPhyBase + reg, val)\r
+#define DmcPhyReadReg(reg) MmioRead32(DmcPhyBase + reg)\r
+\r
+// Initialise PL341 Dynamic Memory Controller\r
+VOID\r
+PL341DmcInit (\r
+ IN PL341_DMC_CONFIG *DmcConfig\r
+ )\r
+{\r
+ UINTN DmcBase;\r
+ UINTN Index;\r
+ UINT32 Chip;\r
+\r
+ DmcBase = DmcConfig->base;\r
+\r
+ // Set config mode\r
+ DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_CONFIGURE);\r
+\r
+ //\r
+ // Setup the QoS AXI ID bits\r
+ //\r
+ if (DmcConfig->HasQos) {\r
+ // CLCD AXIID = 000\r
+ DmcWriteReg(DMC_ID_0_CFG_REG, DMC_ID_CFG_QOS_ENABLE | DMC_ID_CFG_QOS_MIN);\r
+\r
+ // Default disable QoS\r
+ DmcWriteReg(DMC_ID_1_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_2_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_3_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_4_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_5_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_6_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_7_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_8_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_9_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_10_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_11_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_12_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_13_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_14_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ DmcWriteReg(DMC_ID_15_CFG_REG, DMC_ID_CFG_QOS_DISABLE);\r
+ }\r
+\r
+ //\r
+ // Initialise memory controlller\r
+ //\r
+ DmcWriteReg(DMC_REFRESH_PRD_REG, DmcConfig->refresh_prd);\r
+ DmcWriteReg(DMC_CAS_LATENCY_REG, DmcConfig->cas_latency);\r
+ DmcWriteReg(DMC_WRITE_LATENCY_REG, DmcConfig->write_latency);\r
+ DmcWriteReg(DMC_T_MRD_REG, DmcConfig->t_mrd);\r
+ DmcWriteReg(DMC_T_RAS_REG, DmcConfig->t_ras);\r
+ DmcWriteReg(DMC_T_RC_REG, DmcConfig->t_rc);\r
+ DmcWriteReg(DMC_T_RCD_REG, DmcConfig->t_rcd);\r
+ DmcWriteReg(DMC_T_RFC_REG, DmcConfig->t_rfc);\r
+ DmcWriteReg(DMC_T_RP_REG, DmcConfig->t_rp);\r
+ DmcWriteReg(DMC_T_RRD_REG, DmcConfig->t_rrd);\r
+ DmcWriteReg(DMC_T_WR_REG, DmcConfig->t_wr);\r
+ DmcWriteReg(DMC_T_WTR_REG, DmcConfig->t_wtr);\r
+ DmcWriteReg(DMC_T_XP_REG, DmcConfig->t_xp);\r
+ DmcWriteReg(DMC_T_XSR_REG, DmcConfig->t_xsr);\r
+ DmcWriteReg(DMC_T_ESR_REG, DmcConfig->t_esr);\r
+ DmcWriteReg(DMC_T_FAW_REG, DmcConfig->t_faw);\r
+ DmcWriteReg(DMC_T_WRLAT_DIFF, DmcConfig->t_wdata_en);\r
+ DmcWriteReg(DMC_T_RDATA_EN, DmcConfig->t_data_en);\r
+\r
+ //\r
+ // Initialise PL341 Mem Config Registers\r
+ //\r
+\r
+ // Set PL341 Memory Config\r
+ DmcWriteReg(DMC_MEMORY_CONFIG_REG, DmcConfig->MemoryCfg);\r
+\r
+ // Set PL341 Memory Config 2\r
+ DmcWriteReg(DMC_MEMORY_CFG2_REG, DmcConfig->MemoryCfg2);\r
+\r
+ // Set PL341 Chip Select <n>\r
+ DmcWriteReg(DMC_CHIP_0_CFG_REG, DmcConfig->ChipCfg0);\r
+ DmcWriteReg(DMC_CHIP_1_CFG_REG, DmcConfig->ChipCfg1);\r
+ DmcWriteReg(DMC_CHIP_2_CFG_REG, DmcConfig->ChipCfg2);\r
+ DmcWriteReg(DMC_CHIP_3_CFG_REG, DmcConfig->ChipCfg3);\r
+\r
+ // Delay\r
+ for (Index = 0; Index < 10; Index++) {\r
+ DmcReadReg(DMC_STATUS_REG);\r
+ }\r
+\r
+ // Set PL341 Memory Config 3\r
+ DmcWriteReg(DMC_MEMORY_CFG3_REG, DmcConfig->MemoryCfg3);\r
+\r
+ if (DmcConfig->IsUserCfg) {\r
+ //\r
+ // Set Test Chip PHY Registers via PL341 User Config Reg\r
+ // Note that user_cfgX registers are Write Only\r
+ //\r
+ // DLL Freq set = 250MHz - 266MHz\r
+ //\r
+ DmcWriteReg(DMC_USER_0_CFG_REG, DmcConfig->User0Cfg);\r
+\r
+ // user_config2\r
+ // ------------\r
+ // Set defaults before calibrating the DDR2 buffer impendence\r
+ // - Disable ODT\r
+ // - Default drive strengths\r
+ DmcWriteReg(DMC_USER_2_CFG_REG, 0x40000198);\r
+\r
+ //\r
+ // Auto calibrate the DDR2 buffers impendence\r
+ //\r
+ while (!(DmcReadReg(DMC_USER_STATUS_REG) & 0x100));\r
+\r
+ // Set the output driven strength\r
+ DmcWriteReg(DMC_USER_2_CFG_REG, 0x40800000 | DmcConfig->User2Cfg);\r
+\r
+ //\r
+ // Set PL341 Feature Control Register\r
+ //\r
+ // Disable early BRESP - use to optimise CLCD performance\r
+ DmcWriteReg(DMC_FEATURE_CRTL_REG, 0x00000001);\r
+ }\r
+\r
+ //\r
+ // Config memories\r
+ //\r
+ for (Chip = 0; Chip < DmcConfig->MaxChip; Chip++) {\r
+ // Send nop\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_NOP);\r
+\r
+ // Pre-charge all\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
+\r
+ // Delay\r
+ for (Index = 0; Index < 10; Index++) {\r
+ DmcReadReg(DMC_STATUS_REG);\r
+ }\r
+\r
+ // Set (EMR2) extended mode register 2\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG,\r
+ DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r
+ DMC_DIRECT_CMD_BANKADDR(2) |\r
+ DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+ // Set (EMR3) extended mode register 3\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG,\r
+ DMC_DIRECT_CMD_CHIP_ADDR(Chip) |\r
+ DMC_DIRECT_CMD_BANKADDR(3) |\r
+ DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+ //\r
+ // Set (EMR) Extended Mode Register\r
+ //\r
+ // Put into OCD default state\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG,DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_BANKADDR(1) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG);\r
+\r
+ //\r
+ // Set (MR) mode register - With DLL reset\r
+ //\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg | DDR2_MR_DLL_RESET);\r
+\r
+ // Pre-charge all\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_PRECHARGEALL);\r
+ // Auto-refresh\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
+ // Auto-refresh\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_AUTOREFRESH);\r
+\r
+ //\r
+ // Set (MR) mode register - Without DLL reset\r
+ //\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | DMC_DIRECT_CMD_MEMCMD_EXTMODEREG | DmcConfig->ModeReg);\r
+\r
+ // Delay\r
+ for (Index = 0; Index < 10; Index++) {\r
+ DmcReadReg(DMC_STATUS_REG);\r
+ }\r
+\r
+ //\r
+ // Set (EMR) extended mode register - Enable OCD defaults\r
+ //\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r
+ (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_DEFAULT << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r
+\r
+ // Delay\r
+ for (Index = 0; Index < 10; Index++) {\r
+ DmcReadReg(DMC_STATUS_REG);\r
+ }\r
+\r
+ // Set (EMR) extended mode register - OCD Exit\r
+ DmcWriteReg(DMC_DIRECT_CMD_REG, DMC_DIRECT_CMD_CHIP_ADDR(Chip) | (0x00090000) |\r
+ (1 << DDR_MODESET_SHFT) | (DDR_EMR_OCD_NS << DDR_EMR_OCD_SHIFT) | DmcConfig->ExtModeReg);\r
+ }\r
+\r
+ // Move DDR2 Controller to Ready state by issueing GO command\r
+ DmcWriteReg(DMC_COMMAND_REG, DMC_COMMAND_GO);\r
+\r
+ // wait for ready\r
+ while (!(DmcReadReg(DMC_STATUS_REG) & DMC_STATUS_READY));\r
+\r
+}\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL341Dmc\r
+ FILE_GUID = edf8da40-aad1-11df-a1f4-0002a5d5c51b\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PL341DmcLib\r
+\r
+[Sources]\r
+ PL341Dmc.c\r
+\r
+[Packages]\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ MdePkg/MdePkg.dec\r
+\r
+[FixedPcd]\r
--- /dev/null
+#\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http:#opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <AutoGen.h>\r
+#include <Drivers/PL35xSmc.h>\r
+\r
+.text\r
+\r
+#Maintain 8 byte alignment\r
+.align 3\r
+\r
+\r
+GCC_ASM_EXPORT(SMCInitializeNOR)\r
+GCC_ASM_EXPORT(SMCInitializeSRAM)\r
+GCC_ASM_EXPORT(SMCInitializePeripherals)\r
+GCC_ASM_EXPORT(SMCInitializeVRAM)\r
+\r
+\r
+# CS0 CS0-Interf0 NOR1 flash on the motherboard\r
+# CS1 CS1-Interf0 Reserved for the motherboard\r
+# CS2 CS2-Interf0 SRAM on the motherboard\r
+# CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
+# CS4 CS0-Interf1 NOR2 flash on the motherboard\r
+# CS5 CS1-Interf1 memory-mapped peripherals\r
+# CS6 CS2-Interf1 memory-mapped peripherals\r
+# CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
+\r
+// IN r1 SmcBase\r
+// IN r2 ChipSelect\r
+// NOTE: This code is been called before any stack has been setup. It means some registers\r
+// could be overwritten (case of 'r0')\r
+ASM_PFX(SMCInitializeNOR):\r
+#\r
+# Setup NOR1 (CS0-Interface0)\r
+#\r
+\r
+ # Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
+ #Read cycle timeout = 0xA (0:3)\r
+ #Write cycle timeout = 0x3(7:4)\r
+ #OE Assertion Delay = 0x9(11:8)\r
+ #WE Assertion delay = 0x3(15:12)\r
+ #Page cycle timeout = 0x2(19:16) \r
+ LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+ \r
+ # Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
+ # 0x00000002 = MemoryWidth: 32bit\r
+ # 0x00000028 = ReadMemoryBurstLength:continuous\r
+ # 0x00000280 = WriteMemoryBurstLength:continuous\r
+ # 0x00000800 = Set Address Valid\r
+ LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+\r
+ # Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
+ # 0x00000000 = ChipSelect0-Interface 0\r
+ # 0x00400000 = CmdTypes: UpdateRegs\r
+ LoadConstantToReg (0x00400000,r0) @ldr r0, = 0x00400000\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+ \r
+ bx lr\r
+\r
+ASM_PFX(SMCInitializeSRAM):\r
+#\r
+# Setup SRAM (CS2-Interface0)\r
+#\r
+ LoadConstantToReg (0x00027158,r0) @ldr r0, = 0x00027158\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+\r
+ # 0x00000002 = MemoryWidth: 32bit\r
+ # 0x00000800 = Set Address Valid\r
+ LoadConstantToReg (0x00000802,r0) @ldr r0, = 0x00000802\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ \r
+ # 0x01000000 = ChipSelect2-Interface 0\r
+ # 0x00400000 = CmdTypes: UpdateRegs\r
+ LoadConstantToReg (0x01400000,r0) @ldr r0, = 0x01400000\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+\r
+ bx lr\r
+\r
+ASM_PFX(SMCInitializePeripherals):\r
+#\r
+# USB/Eth/VRAM (CS3-Interface0)\r
+#\r
+ LoadConstantToReg (0x000CD2AA,r0) @ldr r0, = 0x000CD2AA\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+ \r
+ # 0x00000002 = MemoryWidth: 32bit\r
+ # 0x00000004 = Memory reads are synchronous\r
+ # 0x00000040 = Memory writes are synchronous\r
+ LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ \r
+ # 0x01800000 = ChipSelect3-Interface 0\r
+ # 0x00400000 = CmdTypes: UpdateRegs\r
+ LoadConstantToReg (0x01C00000,r0) @ldr r0, = 0x01C00000\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+\r
+#\r
+# Setup NOR3 (CS0-Interface1)\r
+#\r
+ LoadConstantToReg (0x0002393A,r0) @ldr r0, = 0x0002393A\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+ \r
+ # 0x00000002 = MemoryWidth: 32bit\r
+ # 0x00000028 = ReadMemoryBurstLength:continuous\r
+ # 0x00000280 = WriteMemoryBurstLength:continuous\r
+ # 0x00000800 = Set Address Valid\r
+ LoadConstantToReg (0x00000AAA,r0) @ldr r0, = 0x00000AAA\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ \r
+ # 0x02000000 = ChipSelect0-Interface 1\r
+ # 0x00400000 = CmdTypes: UpdateRegs\r
+ LoadConstantToReg (0x02400000,r0) @ldr r0, = 0x02400000\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+ \r
+#\r
+# Setup Peripherals (CS3-Interface1)\r
+#\r
+ LoadConstantToReg (0x00025156,r0) @ldr r0, = 0x00025156\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+ \r
+ # 0x00000002 = MemoryWidth: 32bit\r
+ # 0x00000004 = Memory reads are synchronous\r
+ # 0x00000040 = Memory writes are synchronous\r
+ LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ \r
+ # 0x03800000 = ChipSelect3-Interface 1\r
+ # 0x00400000 = CmdTypes: UpdateRegs\r
+ LoadConstantToReg (0x03C00000,r0) @ldr r0, = 0x03C00000\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+ bx lr\r
+\r
+// IN r1 SmcBase\r
+// IN r2 VideoSRamBase\r
+// NOTE: This code is been called before any stack has been setup. It means some registers\r
+// could be overwritten (case of 'r0')\r
+ASM_PFX(SMCInitializeVRAM):\r
+#\r
+# Setup VRAM (CS1-Interface0)\r
+#\r
+ LoadConstantToReg (0x00049249,r0) @ldr r0, = 0x00049249\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+ \r
+ # 0x00000002 = MemoryWidth: 32bit\r
+ # 0x00000004 = Memory reads are synchronous\r
+ # 0x00000040 = Memory writes are synchronous\r
+ LoadConstantToReg (0x00000046,r0) @ldr r0, = 0x00000046\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ \r
+ # 0x00800000 = ChipSelect1-Interface 0\r
+ # 0x00400000 = CmdTypes: UpdateRegs\r
+ LoadConstantToReg (0x00C00000,r0) @ldr r0, = 0x00C00000\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+ \r
+#\r
+# Page mode setup for VRAM\r
+#\r
+ #read current state \r
+ ldr r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+ LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
+ str r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+\r
+ #enable page mode \r
+ ldr r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+ LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
+ str r0, [r2, #0] \r
+ LoadConstantToReg (0x00900090,r0) @ldr r0, = 0x00900090\r
+ str r0, [r2, #0] \r
+\r
+ #confirm page mode enabled\r
+ ldr r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+ LoadConstantToReg (0x00000000,r0) @ldr r0, = 0x00000000\r
+ str r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+ \r
+ bx lr\r
+ \r
+ASM_FUNCTION_REMOVE_IF_UNREFERENCED
\ No newline at end of file
--- /dev/null
+//\r
+// Copyright (c) 2011, ARM Limited. All rights reserved.\r
+// \r
+// This program and the accompanying materials \r
+// are licensed and made available under the terms and conditions of the BSD License \r
+// which accompanies this distribution. The full text of the license may be found at \r
+// http://opensource.org/licenses/bsd-license.php \r
+//\r
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+//\r
+//\r
+\r
+#include <AsmMacroIoLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Drivers/PL35xSmc.h>\r
+#include <AutoGen.h>\r
+\r
+ INCLUDE AsmMacroIoLib.inc\r
+ \r
+ EXPORT SMCInitializeNOR\r
+ EXPORT SMCInitializeSRAM\r
+ EXPORT SMCInitializePeripherals\r
+ EXPORT SMCInitializeVRAM\r
+\r
+ PRESERVE8\r
+ AREA ModuleInitializeSMC, CODE, READONLY\r
+ \r
+// CS0 CS0-Interf0 NOR1 flash on the motherboard\r
+// CS1 CS1-Interf0 Reserved for the motherboard\r
+// CS2 CS2-Interf0 SRAM on the motherboard\r
+// CS3 CS3-Interf0 memory-mapped Ethernet and USB controllers on the motherboard\r
+// CS4 CS0-Interf1 NOR2 flash on the motherboard\r
+// CS5 CS1-Interf1 memory-mapped peripherals\r
+// CS6 CS2-Interf1 memory-mapped peripherals\r
+// CS7 CS3-Interf1 system memory-mapped peripherals on the motherboard.\r
+\r
+// IN r1 SmcBase\r
+// IN r2 ChipSelect\r
+// NOTE: This code is been called before any stack has been setup. It means some registers\r
+// could be overwritten (case of 'r0')\r
+SMCInitializeNOR\r
+ // Write to set_cycle register(holding register for NOR 1 cycle register or NAND cycle register)\r
+ // - Read cycle timeout = 0xA (0:3)\r
+ // - Write cycle timeout = 0x3(7:4)\r
+ // - OE Assertion Delay = 0x9(11:8)\r
+ // - WE Assertion delay = 0x3(15:12)\r
+ // - Page cycle timeout = 0x2(19:16)\r
+ ldr r0, = 0x0002393A\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+ \r
+ // Write to set_opmode register(holding register for NOR 1 opomode register or NAND opmode register)\r
+ ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_WR_BURST_LENGTH_CONT :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+\r
+ // Write to direct_cmd register so that the NOR 1 registers(set-cycles and opmode) are updated with holding registers\r
+ ldr r0, =PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE\r
+ orr r0, r0, r2\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+ \r
+ bx lr\r
+\r
+\r
+//\r
+// Setup SRAM (CS2-Interface0)\r
+//\r
+SMCInitializeSRAM\r
+ ldr r0, = 0x00027158\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+\r
+ ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_ADV)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ \r
+ ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,2))\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+\r
+ bx lr\r
+\r
+SMCInitializePeripherals\r
+//\r
+// USB/Eth/VRAM (CS3-Interface0)\r
+//\r
+ ldr r0, = 0x000CD2AA\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+ \r
+ ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ \r
+ ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,3))\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+\r
+\r
+//\r
+// Setup Peripherals (CS3-Interface1)\r
+//\r
+ ldr r0, = 0x00025156\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+ \r
+ ldr r0, =(PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ \r
+ ldr r0, =(PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(1,3))\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+\r
+ bx lr\r
+\r
+\r
+// IN r1 SmcBase\r
+// IN r2 VideoSRamBase\r
+// NOTE: This code is been called before any stack has been setup. It means some registers\r
+// could be overwritten (case of 'r0')\r
+SMCInitializeVRAM\r
+ //\r
+ // Setup VRAM (CS1-Interface0)\r
+ //\r
+ ldr r0, = 0x00049249\r
+ str r0, [r1, #PL354_SMC_SET_CYCLES_OFFSET]\r
+ \r
+ ldr r0, = (PL354_SMC_SET_OPMODE_MEM_WIDTH_32 :OR: PL354_SMC_SET_OPMODE_SET_RD_SYNC :OR: PL354_SMC_SET_OPMODE_SET_WR_SYNC)\r
+ str r0, [r1, #PL354_SMC_SET_OPMODE_OFFSET]\r
+ \r
+ ldr r0, = (PL354_SMC_DIRECT_CMD_ADDR_CMD_UPDATE :OR: PL354_SMC_DIRECT_CMD_ADDR_CS(0,1))\r
+ str r0, [r1, #PL354_SMC_DIRECT_CMD_OFFSET]\r
+ \r
+ //\r
+ // Page mode setup for VRAM\r
+ //\r
+\r
+ // Read current state\r
+ ldr r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+ ldr r0, = 0x00000000\r
+ str r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+\r
+ // Enable page mode\r
+ ldr r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+ ldr r0, = 0x00000000\r
+ str r0, [r2, #0] \r
+ ldr r0, = 0x00900090\r
+ str r0, [r2, #0] \r
+\r
+ // Confirm page mode enabled\r
+ ldr r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+ ldr r0, = 0x00000000\r
+ str r0, [r2, #0] \r
+ ldr r0, [r2, #0] \r
+ \r
+ bx lr\r
+ \r
+ END\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = PL35xSmc\r
+ FILE_GUID = 10952220-aa32-11df-a438-0002a5d5c51b\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = PL35xSmcLib\r
+\r
+[Sources.common]\r
+ InitializeSMC.asm | RVCT\r
+ InitializeSMC.S | GCC\r
+\r
+[Packages]\r
+ ArmPkg/ArmPkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
+ MdePkg/MdePkg.dec\r
--- /dev/null
+/** @file\r
+*\r
+* Copyright (c) 2011, ARM Limited. All rights reserved.\r
+* \r
+* This program and the accompanying materials \r
+* are licensed and made available under the terms and conditions of the BSD License \r
+* which accompanies this distribution. The full text of the license may be found at \r
+* http://opensource.org/licenses/bsd-license.php \r
+*\r
+* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+*\r
+**/\r
+\r
+#include <Uefi.h>\r
+#include <Drivers/PL310L2Cache.h>\r
+\r
+// Initialize L2X0 Cache Controller\r
+VOID\r
+L2x0CacheInit (\r
+ IN UINTN L2x0Base,\r
+ IN UINT32 L2x0TagLatencies,\r
+ IN UINT32 L2x0DataLatencies,\r
+ IN UINT32 L2x0AuxValue,\r
+ IN UINT32 L2x0AuxMask,\r
+ IN BOOLEAN CacheEnabled\r
+ )\r
+{\r
+ //No implementation\r
+}\r
--- /dev/null
+#/* @file\r
+# Copyright (c) 2011, ARM Limited. All rights reserved.\r
+# \r
+# This program and the accompanying materials \r
+# are licensed and made available under the terms and conditions of the BSD License \r
+# which accompanies this distribution. The full text of the license may be found at \r
+# http://opensource.org/licenses/bsd-license.php \r
+#\r
+# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r
+# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r
+#\r
+#*/\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = L2X0CacheLibNull\r
+ FILE_GUID = 9c76c900-1e8c-11e0-8766-0002a5d5c51b\r
+ MODULE_TYPE = SEC\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = L2X0CacheLib\r
+\r
+[Sources]\r
+ L2X0Cache.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
+ ArmPlatformPkg/ArmPlatformPkg.dec\r
projects / mirror_edk2.git / commitdiff