UefiCpuPkg/PentiumMsr.h: add MSR reference from SDM in comment

Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Cc: Giri P Mudusuru <giri.p.mudusuru@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Giri P Mudusuru <giri.p.mudusuru@intel.com>

diff --git a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
index a8916b4a448a9cf3870fffdc9cb44ed9b23ec6b1..62c5b7eba70d09de18c500de862b4fbb6cff8f66 100644 (file)
--- a/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
+++ b/UefiCpuPkg/Include/Register/Msr/PentiumMsr.h
@@ -40,6 +40,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_ADDR);\r
   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_ADDR, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_P5_MC_ADDR is defined as P5_MC_ADDR in SDM.\r
 **/\r
 #define MSR_PENTIUM_P5_MC_ADDR                   0x00000000\r
 \r
@@ -58,6 +59,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_P5_MC_TYPE);\r
   AsmWriteMsr64 (MSR_PENTIUM_P5_MC_TYPE, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_P5_MC_TYPE is defined as P5_MC_TYPE in SDM.\r
 **/\r
 #define MSR_PENTIUM_P5_MC_TYPE                   0x00000001\r
 \r
@@ -76,6 +78,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_TSC);\r
   AsmWriteMsr64 (MSR_PENTIUM_TSC, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_TSC is defined as TSC in SDM.\r
 **/\r
 #define MSR_PENTIUM_TSC                          0x00000010\r
 \r
@@ -94,6 +97,7 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_CESR);\r
   AsmWriteMsr64 (MSR_PENTIUM_CESR, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_CESR is defined as CESR in SDM.\r
 **/\r
 #define MSR_PENTIUM_CESR                         0x00000011\r
 \r
@@ -112,6 +116,8 @@
   Msr = AsmReadMsr64 (MSR_PENTIUM_CTR0);\r
   AsmWriteMsr64 (MSR_PENTIUM_CTR0, Msr);\r
   @endcode\r
+  @note MSR_PENTIUM_CTR0 is defined as CTR0 in SDM.\r
+        MSR_PENTIUM_CTR1 is defined as CTR1 in SDM.\r
   @{\r
 **/\r
 #define MSR_PENTIUM_CTR0                         0x00000012\r