--- /dev/null
+/** @file\r
+ Platform Flash Access library.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#include <PiDxe.h>\r
+\r
+#include <Library/BaseLib.h>\r
+#include <Library/BaseMemoryLib.h>\r
+#include <Library/DebugLib.h>\r
+#include <Library/PcdLib.h>\r
+#include <Library/PlatformFlashAccessLib.h>\r
+#include <Library/UefiBootServicesTableLib.h>\r
+#include <Protocol/Spi.h>\r
+\r
+//\r
+// SPI default opcode slots\r
+//\r
+#define SPI_OPCODE_JEDEC_ID_INDEX 0\r
+#define SPI_OPCODE_READ_ID_INDEX 1\r
+#define SPI_OPCODE_WRITE_S_INDEX 2\r
+#define SPI_OPCODE_WRITE_INDEX 3\r
+#define SPI_OPCODE_READ_INDEX 4\r
+#define SPI_OPCODE_ERASE_INDEX 5\r
+#define SPI_OPCODE_READ_S_INDEX 6\r
+#define SPI_OPCODE_CHIP_ERASE_INDEX 7\r
+\r
+#define SPI_ERASE_SECTOR_SIZE SIZE_4KB //This is the chipset requirement\r
+\r
+STATIC EFI_PHYSICAL_ADDRESS mInternalFdAddress;\r
+EFI_SPI_PROTOCOL *mSpiProtocol;\r
+\r
+/**\r
+ Writes specified number of bytes from the input buffer to the address\r
+\r
+ @param[in] WriteAddress The flash address to be written.\r
+ @param[in, out] NumBytes The number of bytes.\r
+ @param[in] Buffer The data buffer to be written.\r
+\r
+ @return The status of flash write.\r
+**/\r
+EFI_STATUS\r
+FlashFdWrite (\r
+ IN UINTN WriteAddress,\r
+ IN OUT UINTN *NumBytes,\r
+ IN UINT8 *Buffer\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = EFI_SUCCESS;\r
+\r
+ Status = mSpiProtocol->Execute (\r
+ mSpiProtocol,\r
+ SPI_OPCODE_WRITE_INDEX, // OpcodeIndex\r
+ 0, // PrefixOpcodeIndex\r
+ TRUE, // DataCycle\r
+ TRUE, // Atomic\r
+ TRUE, // ShiftOut\r
+ WriteAddress, // Address\r
+ (UINT32) (*NumBytes), // Data Number\r
+ Buffer,\r
+ EnumSpiRegionBios\r
+ );\r
+ DEBUG((DEBUG_INFO, "FlashFdWrite - 0x%x - %r\n", (UINTN)WriteAddress, Status));\r
+\r
+ AsmWbinvd ();\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Erase a certain block from address LbaWriteAddress\r
+\r
+ @param[in] WriteAddress The flash address to be erased.\r
+\r
+ @return The status of flash erase.\r
+**/\r
+EFI_STATUS\r
+FlashFdErase (\r
+ IN UINTN WriteAddress\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ Status = mSpiProtocol->Execute (\r
+ mSpiProtocol,\r
+ SPI_OPCODE_ERASE_INDEX, // OpcodeIndex\r
+ 0, // PrefixOpcodeIndex\r
+ FALSE, // DataCycle\r
+ TRUE, // Atomic\r
+ FALSE, // ShiftOut\r
+ WriteAddress, // Address\r
+ 0, // Data Number\r
+ NULL,\r
+ EnumSpiRegionBios // SPI_REGION_TYPE\r
+ );\r
+ DEBUG((DEBUG_INFO, "FlashFdErase - 0x%x - %r\n", (UINTN)WriteAddress, Status));\r
+\r
+ AsmWbinvd ();\r
+\r
+ return Status;\r
+}\r
+\r
+/**\r
+ Perform flash write opreation.\r
+\r
+ @param[in] FirmwareType The type of firmware.\r
+ @param[in] FlashAddress The address of flash device to be accessed.\r
+ @param[in] FlashAddressType The type of flash device address.\r
+ @param[in] Buffer The pointer to the data buffer.\r
+ @param[in] Length The length of data buffer in bytes.\r
+\r
+ @retval EFI_SUCCESS The operation returns successfully.\r
+ @retval EFI_WRITE_PROTECTED The flash device is read only.\r
+ @retval EFI_UNSUPPORTED The flash device access is unsupported.\r
+ @retval EFI_INVALID_PARAMETER The input parameter is not valid.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PerformFlashWrite (\r
+ IN PLATFORM_FIRMWARE_TYPE FirmwareType,\r
+ IN EFI_PHYSICAL_ADDRESS FlashAddress,\r
+ IN FLASH_ADDRESS_TYPE FlashAddressType,\r
+ IN VOID *Buffer,\r
+ IN UINTN Length\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+ UINTN SectorNum;\r
+ UINTN Index;\r
+ UINTN NumBytes;\r
+\r
+ DEBUG((DEBUG_INFO, "PerformFlashWrite - 0x%x(%x) - 0x%x\n", (UINTN)FlashAddress, (UINTN)FlashAddressType, Length));\r
+ if (FlashAddressType == FlashAddressTypeAbsoluteAddress) {\r
+ FlashAddress = FlashAddress - mInternalFdAddress;\r
+ }\r
+\r
+ //\r
+ // Erase & Write\r
+ //\r
+ SectorNum = Length / SPI_ERASE_SECTOR_SIZE;\r
+ for (Index = 0; Index < SectorNum; Index++){\r
+ if (CompareMem(\r
+ (UINT8 *)(UINTN)(FlashAddress + mInternalFdAddress) + Index * SPI_ERASE_SECTOR_SIZE,\r
+ (UINT8 *)Buffer + Index * SPI_ERASE_SECTOR_SIZE,\r
+ SPI_ERASE_SECTOR_SIZE) == 0) {\r
+ DEBUG((DEBUG_INFO, "Sector - 0x%x - skip\n", Index));\r
+ continue;\r
+ }\r
+ DEBUG((DEBUG_INFO, "Sector - 0x%x - update...\n", Index));\r
+\r
+ Status = FlashFdErase (\r
+ (UINTN)FlashAddress + Index * SPI_ERASE_SECTOR_SIZE\r
+ );\r
+ if (Status != EFI_SUCCESS){\r
+ break;\r
+ }\r
+ NumBytes = SPI_ERASE_SECTOR_SIZE;\r
+ Status = FlashFdWrite (\r
+ (UINTN)FlashAddress + Index * SPI_ERASE_SECTOR_SIZE,\r
+ &NumBytes,\r
+ (UINT8 *)Buffer + Index * SPI_ERASE_SECTOR_SIZE\r
+ );\r
+ if (Status != EFI_SUCCESS){\r
+ break;\r
+ }\r
+ }\r
+\r
+ return EFI_SUCCESS;\r
+}\r
+\r
+/**\r
+ Platform Flash Access Lib Constructor.\r
+\r
+ @param[in] ImageHandle The firmware allocated handle for the EFI image.\r
+ @param[in] SystemTable A pointer to the EFI System Table.\r
+\r
+ @retval EFI_SUCCESS Constructor returns successfully.\r
+**/\r
+EFI_STATUS\r
+EFIAPI\r
+PerformFlashAccessLibConstructor (\r
+ IN EFI_HANDLE ImageHandle,\r
+ IN EFI_SYSTEM_TABLE *SystemTable\r
+ )\r
+{\r
+ EFI_STATUS Status;\r
+\r
+ mInternalFdAddress = (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32(PcdFlashAreaBaseAddress);\r
+ DEBUG((DEBUG_INFO, "PcdFlashAreaBaseAddress - 0x%x\n", mInternalFdAddress));\r
+\r
+ Status = gBS->LocateProtocol(&gEfiSpiProtocolGuid, NULL, (VOID **)&mSpiProtocol);\r
+ ASSERT_EFI_ERROR(Status);\r
+\r
+ return EFI_SUCCESS;\r
+}\r
--- /dev/null
+/** @file\r
+ SPI flash device description.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+\r
+**/\r
+\r
+#include "SpiFlashDevice.h"\r
+\r
+#define FLASH_SIZE (FixedPcdGet32 (PcdFlashAreaSize))\r
+\r
+SPI_INIT_TABLE mSpiInitTable[] = {\r
+ //\r
+ // Macronix 32Mbit part\r
+ //\r
+ {\r
+ SPI_MX25L3205_ID1,\r
+ SPI_MX25L3205_ID2,\r
+ SPI_MX25L3205_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle20MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Winbond 32Mbit part\r
+ //\r
+ {\r
+ SPI_W25X32_ID1,\r
+ SF_DEVICE_ID0_W25QXX,\r
+ SF_DEVICE_ID1_W25Q32,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Winbond 32Mbit part\r
+ //\r
+ {\r
+ SPI_W25X32_ID1,\r
+ SPI_W25X32_ID2,\r
+ SPI_W25X32_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Atmel 32Mbit part\r
+ //\r
+ {\r
+ SPI_AT26DF321_ID1,\r
+ SPI_AT26DF321_ID2, // issue: byte 2 identifies family/density for Atmel\r
+ SPI_AT26DF321_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ (UINTN)(0x400000 - FLASH_SIZE), // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+\r
+ //\r
+ // Intel 32Mbit part bottom boot\r
+ //\r
+ {\r
+ SPI_QH25F320_ID1,\r
+ SPI_QH25F320_ID2,\r
+ SPI_QH25F320_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_ENABLE\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // SST 64Mbit part\r
+ //\r
+ {\r
+ SPI_SST25VF080B_ID1, // VendorId\r
+ SF_DEVICE_ID0_25VF064C, // DeviceId 0\r
+ SF_DEVICE_ID1_25VF064C, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // NUMONYX 64Mbit part\r
+ //\r
+ {\r
+ SF_VENDOR_ID_NUMONYX, // VendorId\r
+ SF_DEVICE_ID0_M25PX64, // DeviceId 0\r
+ SF_DEVICE_ID1_M25PX64, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Atmel 64Mbit part\r
+ //\r
+ {\r
+ SF_VENDOR_ID_ATMEL, // VendorId\r
+ SF_DEVICE_ID0_AT25DF641, // DeviceId 0\r
+ SF_DEVICE_ID1_AT25DF641, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+\r
+ //\r
+ // Spansion 64Mbit part\r
+ //\r
+ {\r
+ SF_VENDOR_ID_SPANSION, // VendorId\r
+ SF_DEVICE_ID0_S25FL064K, // DeviceId 0\r
+ SF_DEVICE_ID1_S25FL064K, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+\r
+ //\r
+ // Macronix 64Mbit part bottom boot\r
+ //\r
+ {\r
+ SF_VENDOR_ID_MX, // VendorId\r
+ SF_DEVICE_ID0_25L6405D, // DeviceId 0\r
+ SF_DEVICE_ID1_25L6405D, // DeviceId 1\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Winbond 64Mbit part bottom boot\r
+ //\r
+ {\r
+ SPI_W25X64_ID1,\r
+ SF_DEVICE_ID0_W25QXX,\r
+ SF_DEVICE_ID1_W25Q64,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Winbond 64Mbit part bottom boot\r
+ //\r
+ {\r
+ SPI_W25X64_ID1,\r
+ SPI_W25X64_ID2,\r
+ SPI_W25X64_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle50MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle50MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle50MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle50MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle50MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_ERASE, EnumSpiCycle50MHz, EnumSpiOperationErase_4K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle50MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle50MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ },\r
+ //\r
+ // Intel 64Mbit part bottom boot\r
+ //\r
+ {\r
+ SPI_QH25F640_ID1,\r
+ SPI_QH25F640_ID2,\r
+ SPI_QH25F640_ID3,\r
+ {\r
+ SPI_COMMAND_WRITE_ENABLE,\r
+ SPI_COMMAND_WRITE_S_EN\r
+ },\r
+ {\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_JEDEC_ID, EnumSpiCycle33MHz, EnumSpiOperationJedecId},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ_ID, EnumSpiCycle33MHz, EnumSpiOperationOther},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_WRITE_S, EnumSpiCycle33MHz, EnumSpiOperationWriteStatus},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_WRITE, EnumSpiCycle33MHz, EnumSpiOperationProgramData_1_Byte},\r
+ {EnumSpiOpcodeRead, SPI_COMMAND_READ, EnumSpiCycle33MHz, EnumSpiOperationReadData},\r
+ {EnumSpiOpcodeWrite, SPI_COMMAND_BLOCK_ERASE, EnumSpiCycle33MHz, EnumSpiOperationErase_64K_Byte},\r
+ {EnumSpiOpcodeReadNoAddr, SPI_COMMAND_READ_S, EnumSpiCycle33MHz, EnumSpiOperationReadStatus},\r
+ {EnumSpiOpcodeWriteNoAddr, SPI_COMMAND_CHIP_ERASE, EnumSpiCycle33MHz, EnumSpiOperationFullChipErase}\r
+ },\r
+ 0x800000 - FLASH_SIZE, // BIOS Start Offset\r
+ FLASH_SIZE // BIOS image size in flash\r
+ }\r
+};\r
--- /dev/null
+/** @file\r
+ SPI flash device header file.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+**/\r
+\r
+#ifndef _SPI_FLASH_DEVICE_H_\r
+#define _SPI_FLASH_DEVICE_H_\r
+\r
+#include <PiDxe.h>\r
+#include <Protocol/Spi.h>\r
+#include <Protocol/FirmwareVolumeBlock.h>\r
+\r
+//\r
+// Supported SPI Flash Devices\r
+//\r
+typedef enum {\r
+ EnumSpiFlash25L3205D, // Macronix 32Mbit part\r
+ EnumSpiFlashW25Q32, // Winbond 32Mbit part\r
+ EnumSpiFlashW25X32, // Winbond 32Mbit part\r
+ EnumSpiFlashAT25DF321, // Atmel 32Mbit part\r
+ EnumSpiFlashQH25F320, // Intel 32Mbit part\r
+ EnumSpiFlash25VF064C, // SST 64Mbit part\r
+ EnumSpiFlashM25PX64, // NUMONYX 64Mbit part\r
+ EnumSpiFlashAT25DF641, // Atmel 64Mbit part\r
+ EnumSpiFlashS25FL064K, // Spansion 64Mbit part\r
+ EnumSpiFlash25L6405D, // Macronix 64Mbit part\r
+ EnumSpiFlashW25Q64, // Winbond 64Mbit part\r
+ EnumSpiFlashW25X64, // Winbond 64Mbit part\r
+ EnumSpiFlashQH25F640, // Intel 64Mbit part\r
+ EnumSpiFlashMax\r
+} SPI_FLASH_TYPES_SUPPORTED;\r
+\r
+//\r
+// Flash Device commands\r
+//\r
+// If a supported device uses a command different from the list below, a device specific command\r
+// will be defined just below it's JEDEC id section.\r
+//\r
+#define SPI_COMMAND_WRITE 0x02\r
+#define SPI_COMMAND_WRITE_AAI 0xAD\r
+#define SPI_COMMAND_READ 0x03\r
+#define SPI_COMMAND_ERASE 0x20\r
+#define SPI_COMMAND_WRITE_DISABLE 0x04\r
+#define SPI_COMMAND_READ_S 0x05\r
+#define SPI_COMMAND_WRITE_ENABLE 0x06\r
+#define SPI_COMMAND_READ_ID 0xAB\r
+#define SPI_COMMAND_JEDEC_ID 0x9F\r
+#define SPI_COMMAND_WRITE_S_EN 0x50\r
+#define SPI_COMMAND_WRITE_S 0x01\r
+#define SPI_COMMAND_CHIP_ERASE 0xC7\r
+#define SPI_COMMAND_BLOCK_ERASE 0xD8\r
+\r
+//\r
+// Flash JEDEC device ids\r
+//\r
+// SST 8Mbit part\r
+//\r
+#define SPI_SST25VF080B_ID1 0xBF\r
+#define SPI_SST25VF080B_ID2 0x25\r
+#define SPI_SST25VF080B_ID3 0x8E\r
+//\r
+// SST 16Mbit part\r
+//\r
+#define SPI_SST25VF016B_ID1 0xBF\r
+#define SPI_SST25VF016B_ID2 0x25\r
+#define SPI_SST25V016BF_ID3 0x41\r
+//\r
+// Macronix 32Mbit part\r
+//\r
+// MX25 part does not support WRITE_AAI comand (0xAD)\r
+//\r
+#define SPI_MX25L3205_ID1 0xC2\r
+#define SPI_MX25L3205_ID2 0x20\r
+#define SPI_MX25L3205_ID3 0x16\r
+//\r
+// Intel 32Mbit part bottom boot\r
+//\r
+#define SPI_QH25F320_ID1 0x89\r
+#define SPI_QH25F320_ID2 0x89\r
+#define SPI_QH25F320_ID3 0x12 // 32Mbit bottom boot\r
+//\r
+// Intel 64Mbit part bottom boot\r
+//\r
+#define SPI_QH25F640_ID1 0x89\r
+#define SPI_QH25F640_ID2 0x89\r
+#define SPI_QH25F640_ID3 0x13 // 64Mbit bottom boot\r
+//\r
+// QH part does not support command 0x20 for erase; only 0xD8 (sector erase)\r
+// QH part has 0x40 command for erase of parameter block (8 x 8K blocks at bottom of part)\r
+// 0x40 command ignored if address outside of parameter block range\r
+//\r
+#define SPI_QH25F320_COMMAND_PBLOCK_ERASE 0x40\r
+//\r
+// Winbond 32Mbit part\r
+//\r
+#define SPI_W25X32_ID1 0xEF\r
+#define SPI_W25X32_ID2 0x30 // Memory Type\r
+#define SPI_W25X32_ID3 0x16 // Capacity\r
+#define SF_DEVICE_ID1_W25Q32 0x16\r
+\r
+//\r
+// Winbond 64Mbit part\r
+//\r
+#define SPI_W25X64_ID1 0xEF\r
+#define SPI_W25X64_ID2 0x30 // Memory Type\r
+#define SPI_W25X64_ID3 0x17 // Capacity\r
+#define SF_DEVICE_ID0_W25QXX 0x40\r
+#define SF_DEVICE_ID1_W25Q64 0x17\r
+//\r
+// Winbond 128Mbit part\r
+//\r
+#define SF_DEVICE_ID0_W25Q128 0x40\r
+#define SF_DEVICE_ID1_W25Q128 0x18\r
+\r
+//\r
+// Atmel 32Mbit part\r
+//\r
+#define SPI_AT26DF321_ID1 0x1F\r
+#define SPI_AT26DF321_ID2 0x47 // [7:5]=Family, [4:0]=Density\r
+#define SPI_AT26DF321_ID3 0x00\r
+\r
+#define SF_VENDOR_ID_ATMEL 0x1F\r
+#define SF_DEVICE_ID0_AT25DF641 0x48\r
+#define SF_DEVICE_ID1_AT25DF641 0x00\r
+\r
+//\r
+// SST 8Mbit part\r
+//\r
+#define SPI_SST25VF080B_ID1 0xBF\r
+#define SPI_SST25VF080B_ID2 0x25\r
+#define SPI_SST25VF080B_ID3 0x8E\r
+#define SF_DEVICE_ID0_25VF064C 0x25\r
+#define SF_DEVICE_ID1_25VF064C 0x4B\r
+\r
+//\r
+// SST 16Mbit part\r
+//\r
+#define SPI_SST25VF016B_ID1 0xBF\r
+#define SPI_SST25VF016B_ID2 0x25\r
+#define SPI_SST25V016BF_ID3 0x41\r
+\r
+//\r
+// Winbond 32Mbit part\r
+//\r
+#define SPI_W25X32_ID1 0xEF\r
+#define SPI_W25X32_ID2 0x30 // Memory Type\r
+#define SPI_W25X32_ID3 0x16 // Capacity\r
+\r
+#define SF_VENDOR_ID_MX 0xC2\r
+#define SF_DEVICE_ID0_25L6405D 0x20\r
+#define SF_DEVICE_ID1_25L6405D 0x17\r
+\r
+#define SF_VENDOR_ID_NUMONYX 0x20\r
+#define SF_DEVICE_ID0_M25PX64 0x71\r
+#define SF_DEVICE_ID1_M25PX64 0x17\r
+\r
+//\r
+// Spansion 64Mbit part\r
+//\r
+#define SF_VENDOR_ID_SPANSION 0xEF\r
+#define SF_DEVICE_ID0_S25FL064K 0x40\r
+#define SF_DEVICE_ID1_S25FL064K 0x00\r
+\r
+//\r
+// index for prefix opcodes\r
+//\r
+#define SPI_WREN_INDEX 0 // Prefix Opcode 0: SPI_COMMAND_WRITE_ENABLE\r
+#define SPI_EWSR_INDEX 1 // Prefix Opcode 1: SPI_COMMAND_WRITE_S_EN\r
+#define BIOS_CTRL 0xDC\r
+\r
+#define PFAB_CARD_DEVICE_ID 0x5150\r
+#define PFAB_CARD_VENDOR_ID 0x8086\r
+#define PFAB_CARD_SETUP_REGISTER 0x40\r
+#define PFAB_CARD_SETUP_BYTE 0x0d\r
+\r
+\r
+#endif\r
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