--- /dev/null
+/** @file\r
+ MSR Definitions for the Intel(R) Core(TM) 2 Processor Family.\r
+\r
+ Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
+ are provided for MSRs that contain one or more bit fields. If the MSR value\r
+ returned is a single 32-bit or 64-bit value, then a data structure is not\r
+ provided for that MSR.\r
+\r
+ Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
+ This program and the accompanying materials\r
+ are licensed and made available under the terms and conditions of the BSD License\r
+ which accompanies this distribution. The full text of the license may be found at\r
+ http://opensource.org/licenses/bsd-license.php\r
+\r
+ THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
+ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
+\r
+ @par Specification Reference:\r
+ Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 3,\r
+ December 2015, Chapter 35 Model-Specific-Registers (MSR), Section 35-2.\r
+\r
+**/\r
+\r
+#ifndef __CORE2_MSR_H__\r
+#define __CORE2_MSR_H__\r
+\r
+#include <Register/ArchitecturalMsr.h>\r
+\r
+/**\r
+ Shared. Model Specific Platform ID (R).\r
+\r
+ @param ECX MSR_CORE2_PLATFORM_ID (0x00000017)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PLATFORM_ID_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_PLATFORM_ID_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PLATFORM_ID);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_PLATFORM_ID 0x00000017\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_PLATFORM_ID\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:8;\r
+ ///\r
+ /// [Bits 12:8] Maximum Qualified Ratio (R) The maximum allowed bus ratio.\r
+ ///\r
+ UINT32 MaximumQualifiedRatio:5;\r
+ UINT32 Reserved2:19;\r
+ UINT32 Reserved3:18;\r
+ ///\r
+ /// [Bits 52:50] See Table 35-2.\r
+ ///\r
+ UINT32 PlatformId:3;\r
+ UINT32 Reserved4:11;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_PLATFORM_ID_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Processor Hard Power-On Configuration (R/W) Enables and disables\r
+ processor features; (R) indicates current processor configuration.\r
+\r
+ @param ECX MSR_CORE2_EBL_CR_POWERON (0x0000002A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_EBL_CR_POWERON_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_EBL_CR_POWERON_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_EBL_CR_POWERON);\r
+ AsmWriteMsr64 (MSR_CORE2_EBL_CR_POWERON, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_EBL_CR_POWERON 0x0000002A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_EBL_CR_POWERON\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:1;\r
+ ///\r
+ /// [Bit 1] Data Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Note: Not all processor implements R/W.\r
+ ///\r
+ UINT32 DataErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 2] Response Error Checking Enable (R/W) 1 = Enabled; 0 = Disabled\r
+ /// Note: Not all processor implements R/W.\r
+ ///\r
+ UINT32 ResponseErrorCheckingEnable:1;\r
+ ///\r
+ /// [Bit 3] MCERR# Drive Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
+ /// all processor implements R/W.\r
+ ///\r
+ UINT32 MCERR_DriveEnable:1;\r
+ ///\r
+ /// [Bit 4] Address Parity Enable (R/W) 1 = Enabled; 0 = Disabled Note:\r
+ /// Not all processor implements R/W.\r
+ ///\r
+ UINT32 AddressParityEnable:1;\r
+ UINT32 Reserved2:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 7] BINIT# Driver Enable (R/W) 1 = Enabled; 0 = Disabled Note: Not\r
+ /// all processor implements R/W.\r
+ ///\r
+ UINT32 BINIT_DriverEnable:1;\r
+ ///\r
+ /// [Bit 8] Output Tri-state Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 OutputTriStateEnable:1;\r
+ ///\r
+ /// [Bit 9] Execute BIST (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 ExecuteBIST:1;\r
+ ///\r
+ /// [Bit 10] MCERR# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 MCERR_ObservationEnabled:1;\r
+ ///\r
+ /// [Bit 11] Intel TXT Capable Chipset. (R/O) 1 = Present; 0 = Not Present.\r
+ ///\r
+ UINT32 IntelTXTCapableChipset:1;\r
+ ///\r
+ /// [Bit 12] BINIT# Observation Enabled (R/O) 1 = Enabled; 0 = Disabled.\r
+ ///\r
+ UINT32 BINIT_ObservationEnabled:1;\r
+ UINT32 Reserved4:1;\r
+ ///\r
+ /// [Bit 14] 1 MByte Power on Reset Vector (R/O) 1 = 1 MByte; 0 = 4 GBytes.\r
+ ///\r
+ UINT32 ResetVector:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bits 17:16] APIC Cluster ID (R/O).\r
+ ///\r
+ UINT32 APICClusterID:2;\r
+ ///\r
+ /// [Bit 18] N/2 Non-Integer Bus Ratio (R/O) 0 = Integer ratio; 1 =\r
+ /// Non-integer ratio.\r
+ ///\r
+ UINT32 NonIntegerBusRatio:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bits 21:20] Symmetric Arbitration ID (R/O).\r
+ ///\r
+ UINT32 SymmetricArbitrationID:2;\r
+ ///\r
+ /// [Bits 26:22] Integer Bus Frequency Ratio (R/O).\r
+ ///\r
+ UINT32 IntegerBusFrequencyRatio:5;\r
+ UINT32 Reserved7:5;\r
+ UINT32 Reserved8:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_EBL_CR_POWERON_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Control Features in Intel 64Processor (R/W) See Table 35-2.\r
+\r
+ @param ECX MSR_CORE2_FEATURE_CONTROL (0x0000003A)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_FEATURE_CONTROL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_FEATURE_CONTROL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FEATURE_CONTROL);\r
+ AsmWriteMsr64 (MSR_CORE2_FEATURE_CONTROL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_FEATURE_CONTROL 0x0000003A\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_FEATURE_CONTROL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:3;\r
+ ///\r
+ /// [Bit 3] Unique. SMRR Enable (R/WL) When this bit is set and the lock\r
+ /// bit is set makes the SMRR_PHYS_BASE and SMRR_PHYS_MASK registers read\r
+ /// visible and writeable while in SMM.\r
+ ///\r
+ UINT32 SMRREnable:1;\r
+ UINT32 Reserved2:28;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_FEATURE_CONTROL_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record n From IP (R/W) One of four pairs of last branch\r
+ record registers on the last branch record stack. This part of the stack\r
+ contains pointers to the source instruction for one of the last four\r
+ branches, exceptions, or interrupts taken by the processor. See also: -\r
+ Last Branch Record Stack TOS at 1C9H - Section 17.12, "Last Branch,\r
+ Interrupt, and Exception Recording (Pentium M Processors).".\r
+\r
+ @param ECX MSR_CORE2_LASTBRANCH_n_FROM_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP);\r
+ AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_FROM_IP, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_CORE2_LASTBRANCH_0_FROM_IP 0x00000040\r
+#define MSR_CORE2_LASTBRANCH_1_FROM_IP 0x00000041\r
+#define MSR_CORE2_LASTBRANCH_2_FROM_IP 0x00000042\r
+#define MSR_CORE2_LASTBRANCH_3_FROM_IP 0x00000043\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record n To IP (R/W) One of four pairs of last branch\r
+ record registers on the last branch record stack. This part of the stack\r
+ contains pointers to the destination instruction for one of the last four\r
+ branches, exceptions, or interrupts taken by the processor.\r
+\r
+ @param ECX MSR_CORE2_LASTBRANCH_n_TO_IP\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP);\r
+ AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_0_TO_IP, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_CORE2_LASTBRANCH_0_TO_IP 0x00000060\r
+#define MSR_CORE2_LASTBRANCH_1_TO_IP 0x00000061\r
+#define MSR_CORE2_LASTBRANCH_2_TO_IP 0x00000062\r
+#define MSR_CORE2_LASTBRANCH_3_TO_IP 0x00000063\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique. System Management Mode Base Address register (WO in SMM)\r
+ Model-specific implementation of SMRR-like interface, read visible and write\r
+ only in SMM.\r
+\r
+ @param ECX MSR_CORE2_SMRR_PHYSBASE (0x000000A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_SMRR_PHYSBASE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_SMRR_PHYSBASE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = 0;\r
+ AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSBASE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_SMRR_PHYSBASE 0x000000A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSBASE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:12;\r
+ ///\r
+ /// [Bits 31:12] PhysBase. SMRR physical Base Address.\r
+ ///\r
+ UINT32 PhysBase:20;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_SMRR_PHYSBASE_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. System Management Mode Physical Address Mask register (WO in SMM)\r
+ Model-specific implementation of SMRR-like interface, read visible and write\r
+ only in SMM.\r
+\r
+ @param ECX MSR_CORE2_SMRR_PHYSMASK (0x000000A1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_SMRR_PHYSMASK_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_SMRR_PHYSMASK_REGISTER Msr;\r
+\r
+ Msr.Uint64 = 0;\r
+ AsmWriteMsr64 (MSR_CORE2_SMRR_PHYSMASK, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_SMRR_PHYSMASK 0x000000A1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_SMRR_PHYSMASK\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:11;\r
+ ///\r
+ /// [Bit 11] Valid. Physical address base and range mask are valid.\r
+ ///\r
+ UINT32 Valid:1;\r
+ ///\r
+ /// [Bits 31:12] PhysMask. SMRR physical address range mask.\r
+ ///\r
+ UINT32 PhysMask:20;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_SMRR_PHYSMASK_REGISTER;\r
+\r
+\r
+/**\r
+ Shared. Scalable Bus Speed(RO) This field indicates the intended scalable\r
+ bus clock speed for processors based on Intel Core microarchitecture:.\r
+\r
+ @param ECX MSR_CORE2_FSB_FREQ (0x000000CD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_FSB_FREQ_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_FSB_FREQ_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_FSB_FREQ_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_FSB_FREQ);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_FSB_FREQ 0x000000CD\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_FSB_FREQ\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 2:0] - Scalable Bus Speed\r
+ /// 101B: 100 MHz (FSB 400)\r
+ /// 001B: 133 MHz (FSB 533)\r
+ /// 011B: 167 MHz (FSB 667)\r
+ /// 010B: 200 MHz (FSB 800)\r
+ /// 000B: 267 MHz (FSB 1067)\r
+ /// 100B: 333 MHz (FSB 1333)\r
+ ///\r
+ /// 133.33 MHz should be utilized if performing calculation with System\r
+ /// Bus Speed when encoding is 001B. 166.67 MHz should be utilized if\r
+ /// performing calculation with System Bus Speed when encoding is 011B.\r
+ /// 266.67 MHz should be utilized if performing calculation with System\r
+ /// Bus Speed when encoding is 000B. 333.33 MHz should be utilized if\r
+ /// performing calculation with System Bus Speed when encoding is 100B.\r
+ ///\r
+ UINT32 ScalableBusSpeed:3;\r
+ UINT32 Reserved1:29;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_FSB_FREQ_REGISTER;\r
+\r
+\r
+/**\r
+ Shared.\r
+\r
+ @param ECX MSR_CORE2_BBL_CR_CTL3 (0x0000011E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_BBL_CR_CTL3_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_BBL_CR_CTL3_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_BBL_CR_CTL3);\r
+ AsmWriteMsr64 (MSR_CORE2_BBL_CR_CTL3, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_BBL_CR_CTL3 0x0000011E\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_BBL_CR_CTL3\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] L2 Hardware Enabled (RO) 1 = If the L2 is hardware-enabled 0 =\r
+ /// Indicates if the L2 is hardware-disabled.\r
+ ///\r
+ UINT32 L2HardwareEnabled:1;\r
+ UINT32 Reserved1:7;\r
+ ///\r
+ /// [Bit 8] L2 Enabled (R/W) 1 = L2 cache has been initialized 0 =\r
+ /// Disabled (default) Until this bit is set the processor will not\r
+ /// respond to the WBINVD instruction or the assertion of the FLUSH# input.\r
+ ///\r
+ UINT32 L2Enabled:1;\r
+ UINT32 Reserved2:14;\r
+ ///\r
+ /// [Bit 23] L2 Not Present (RO) 1. = L2 Present 2. = L2 Not Present.\r
+ ///\r
+ UINT32 L2NotPresent:1;\r
+ UINT32 Reserved3:8;\r
+ UINT32 Reserved4:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_BBL_CR_CTL3_REGISTER;\r
+\r
+\r
+/**\r
+ Shared.\r
+\r
+ @param ECX MSR_CORE2_PERF_STATUS (0x00000198)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PERF_STATUS_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PERF_STATUS_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_PERF_STATUS_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_STATUS, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_PERF_STATUS 0x00000198\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_PERF_STATUS\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 15:0] Current Performance State Value.\r
+ ///\r
+ UINT32 CurrentPerformanceStateValue:16;\r
+ UINT32 Reserved1:15;\r
+ ///\r
+ /// [Bit 31] XE Operation (R/O). If set, XE operation is enabled. Default\r
+ /// is cleared.\r
+ ///\r
+ UINT32 XEOperation:1;\r
+ UINT32 Reserved2:8;\r
+ ///\r
+ /// [Bits 44:40] Maximum Bus Ratio (R/O) Indicates maximum bus ratio\r
+ /// configured for the processor.\r
+ ///\r
+ UINT32 MaximumBusRatio:5;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 46] Non-Integer Bus Ratio (R/O) Indicates non-integer bus ratio\r
+ /// is enabled. Applies processors based on Enhanced Intel Core\r
+ /// microarchitecture.\r
+ ///\r
+ UINT32 NonIntegerBusRatio:1;\r
+ UINT32 Reserved4:17;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_PERF_STATUS_REGISTER;\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE2_THERM2_CTL (0x0000019D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_THERM2_CTL_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_THERM2_CTL_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_THERM2_CTL_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_THERM2_CTL);\r
+ AsmWriteMsr64 (MSR_CORE2_THERM2_CTL, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_THERM2_CTL 0x0000019D\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_THERM2_CTL\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ UINT32 Reserved1:16;\r
+ ///\r
+ /// [Bit 16] TM_SELECT (R/W) Mode of automatic thermal monitor: 1. =\r
+ /// Thermal Monitor 1 (thermally-initiated on-die modulation of the\r
+ /// stop-clock duty cycle) 2. = Thermal Monitor 2 (thermally-initiated\r
+ /// frequency transitions) If bit 3 of the IA32_MISC_ENABLE register is\r
+ /// cleared, TM_SELECT has no effect. Neither TM1 nor TM2 are enabled.\r
+ ///\r
+ UINT32 TM_SELECT:1;\r
+ UINT32 Reserved2:15;\r
+ UINT32 Reserved3:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_THERM2_CTL_REGISTER;\r
+\r
+\r
+/**\r
+ Enable Misc. Processor Features (R/W) Allows a variety of processor\r
+ functions to be enabled and disabled.\r
+\r
+ @param ECX MSR_CORE2_IA32_MISC_ENABLE (0x000001A0)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_IA32_MISC_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_IA32_MISC_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_IA32_MISC_ENABLE);\r
+ AsmWriteMsr64 (MSR_CORE2_IA32_MISC_ENABLE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_IA32_MISC_ENABLE 0x000001A0\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_IA32_MISC_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Fast-Strings Enable See Table 35-2.\r
+ ///\r
+ UINT32 FastStrings:1;\r
+ UINT32 Reserved1:2;\r
+ ///\r
+ /// [Bit 3] Unique. Automatic Thermal Control Circuit Enable (R/W) See\r
+ /// Table 35-2.\r
+ ///\r
+ UINT32 AutomaticThermalControlCircuit:1;\r
+ UINT32 Reserved2:3;\r
+ ///\r
+ /// [Bit 7] Shared. Performance Monitoring Available (R) See Table 35-2.\r
+ ///\r
+ UINT32 PerformanceMonitoring:1;\r
+ UINT32 Reserved3:1;\r
+ ///\r
+ /// [Bit 9] Hardware Prefetcher Disable (R/W) When set, disables the\r
+ /// hardware prefetcher operation on streams of data. When clear\r
+ /// (default), enables the prefetch queue. Disabling of the hardware\r
+ /// prefetcher may impact processor performance.\r
+ ///\r
+ UINT32 HardwarePrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 10] Shared. FERR# Multiplexing Enable (R/W) 1 = FERR# asserted by\r
+ /// the processor to indicate a pending break event within the processor 0\r
+ /// = Indicates compatible FERR# signaling behavior This bit must be set\r
+ /// to 1 to support XAPIC interrupt model usage.\r
+ ///\r
+ UINT32 FERR:1;\r
+ ///\r
+ /// [Bit 11] Shared. Branch Trace Storage Unavailable (RO) See Table 35-2.\r
+ ///\r
+ UINT32 BTS:1;\r
+ ///\r
+ /// [Bit 12] Shared. Precise Event Based Sampling Unavailable (RO) See\r
+ /// Table 35-2.\r
+ ///\r
+ UINT32 PEBS:1;\r
+ ///\r
+ /// [Bit 13] Shared. TM2 Enable (R/W) When this bit is set (1) and the\r
+ /// thermal sensor indicates that the die temperature is at the\r
+ /// pre-determined threshold, the Thermal Monitor 2 mechanism is engaged.\r
+ /// TM2 will reduce the bus to core ratio and voltage according to the\r
+ /// value last written to MSR_THERM2_CTL bits 15:0.\r
+ /// When this bit is clear (0, default), the processor does not change\r
+ /// the VID signals or the bus to core ratio when the processor enters a\r
+ /// thermally managed state. The BIOS must enable this feature if the\r
+ /// TM2 feature flag (CPUID.1:ECX[8]) is set; if the TM2 feature flag is\r
+ /// not set, this feature is not supported and BIOS must not alter the\r
+ /// contents of the TM2 bit location. The processor is operating out of\r
+ /// specification if both this bit and the TM1 bit are set to 0.\r
+ ///\r
+ UINT32 TM2:1;\r
+ UINT32 Reserved4:2;\r
+ ///\r
+ /// [Bit 16] Shared. Enhanced Intel SpeedStep Technology Enable (R/W) See\r
+ /// Table 35-2.\r
+ ///\r
+ UINT32 EIST:1;\r
+ UINT32 Reserved5:1;\r
+ ///\r
+ /// [Bit 18] Shared. ENABLE MONITOR FSM (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 MONITOR:1;\r
+ ///\r
+ /// [Bit 19] Shared. Adjacent Cache Line Prefetch Disable (R/W) When set\r
+ /// to 1, the processor fetches the cache line that contains data\r
+ /// currently required by the processor. When set to 0, the processor\r
+ /// fetches cache lines that comprise a cache line pair (128 bytes).\r
+ /// Single processor platforms should not set this bit. Server platforms\r
+ /// should set or clear this bit based on platform performance observed in\r
+ /// validation and testing. BIOS may contain a setup option that controls\r
+ /// the setting of this bit.\r
+ ///\r
+ UINT32 AdjacentCacheLinePrefetchDisable:1;\r
+ ///\r
+ /// [Bit 20] Shared. Enhanced Intel SpeedStep Technology Select Lock\r
+ /// (R/WO) When set, this bit causes the following bits to become\r
+ /// read-only: - Enhanced Intel SpeedStep Technology Select Lock (this\r
+ /// bit), - Enhanced Intel SpeedStep Technology Enable bit. The bit must\r
+ /// be set before an Enhanced Intel SpeedStep Technology transition is\r
+ /// requested. This bit is cleared on reset.\r
+ ///\r
+ UINT32 EISTLock:1;\r
+ UINT32 Reserved6:1;\r
+ ///\r
+ /// [Bit 22] Shared. Limit CPUID Maxval (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 LimitCpuidMaxval:1;\r
+ ///\r
+ /// [Bit 23] Shared. xTPR Message Disable (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 xTPR_Message_Disable:1;\r
+ UINT32 Reserved7:8;\r
+ UINT32 Reserved8:2;\r
+ ///\r
+ /// [Bit 34] Unique. XD Bit Disable (R/W) See Table 35-2.\r
+ ///\r
+ UINT32 XD:1;\r
+ UINT32 Reserved9:2;\r
+ ///\r
+ /// [Bit 37] Unique. DCU Prefetcher Disable (R/W) When set to 1, The DCU\r
+ /// L1 data cache prefetcher is disabled. The default value after reset is\r
+ /// 0. BIOS may write '1' to disable this feature. The DCU prefetcher is\r
+ /// an L1 data cache prefetcher. When the DCU prefetcher detects multiple\r
+ /// loads from the same line done within a time limit, the DCU prefetcher\r
+ /// assumes the next line will be required. The next line is prefetched in\r
+ /// to the L1 data cache from memory or L2.\r
+ ///\r
+ UINT32 DCUPrefetcherDisable:1;\r
+ ///\r
+ /// [Bit 38] Shared. IDA Disable (R/W) When set to 1 on processors that\r
+ /// support IDA, the Intel Dynamic Acceleration feature (IDA) is disabled\r
+ /// and the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).\r
+ /// When set to a 0 on processors that support IDA, CPUID.06H: EAX[1]\r
+ /// reports the processor's support of IDA is enabled. Note: the power-on\r
+ /// default value is used by BIOS to detect hardware support of IDA. If\r
+ /// power-on default value is 1, IDA is available in the processor. If\r
+ /// power-on default value is 0, IDA is not available.\r
+ ///\r
+ UINT32 IDADisable:1;\r
+ ///\r
+ /// [Bit 39] Unique. IP Prefetcher Disable (R/W) When set to 1, The IP\r
+ /// prefetcher is disabled. The default value after reset is 0. BIOS may\r
+ /// write '1' to disable this feature. The IP prefetcher is an L1 data\r
+ /// cache prefetcher. The IP prefetcher looks for sequential load history\r
+ /// to determine whether to prefetch the next expected data into the L1\r
+ /// cache from memory or L2.\r
+ ///\r
+ UINT32 IPPrefetcherDisable:1;\r
+ UINT32 Reserved10:24;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_IA32_MISC_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r
+ that points to the MSR containing the most recent branch record. See\r
+ MSR_LASTBRANCH_0_FROM_IP (at 40H).\r
+\r
+ @param ECX MSR_CORE2_LASTBRANCH_TOS (0x000001C9)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LASTBRANCH_TOS);\r
+ AsmWriteMsr64 (MSR_CORE2_LASTBRANCH_TOS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_LASTBRANCH_TOS 0x000001C9\r
+\r
+\r
+/**\r
+ Unique. Last Exception Record From Linear IP (R) Contains a pointer to the\r
+ last branch instruction that the processor executed prior to the last\r
+ exception that was generated or the last interrupt that was handled.\r
+\r
+ @param ECX MSR_CORE2_LER_FROM_LIP (0x000001DD)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LER_FROM_LIP);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_LER_FROM_LIP 0x000001DD\r
+\r
+\r
+/**\r
+ Unique. Last Exception Record To Linear IP (R) This area contains a pointer\r
+ to the target of the last branch instruction that the processor executed\r
+ prior to the last exception that was generated or the last interrupt that\r
+ was handled.\r
+\r
+ @param ECX MSR_CORE2_LER_TO_LIP (0x000001DE)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_LER_TO_LIP);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_LER_TO_LIP 0x000001DE\r
+\r
+\r
+/**\r
+ Unique. Fixed-Function Performance Counter Register n (R/W).\r
+\r
+ @param ECX MSR_CORE2_PERF_FIXED_CTRn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR0);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_CORE2_PERF_FIXED_CTR0 0x00000309\r
+#define MSR_CORE2_PERF_FIXED_CTR1 0x0000030A\r
+#define MSR_CORE2_PERF_FIXED_CTR2 0x0000030B\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique. RO. This applies to processors that do not support architectural\r
+ perfmon version 2.\r
+\r
+ @param ECX MSR_CORE2_PERF_CAPABILITIES (0x00000345)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PERF_CAPABILITIES_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_PERF_CAPABILITIES_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PERF_CAPABILITIES);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_CAPABILITIES, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_PERF_CAPABILITIES 0x00000345\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_PERF_CAPABILITIES\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bits 5:0] LBR Format. See Table 35-2.\r
+ ///\r
+ UINT32 LBR_FMT:6;\r
+ ///\r
+ /// [Bit 6] PEBS Record Format.\r
+ ///\r
+ UINT32 PEBS_FMT:1;\r
+ ///\r
+ /// [Bit 7] PEBSSaveArchRegs. See Table 35-2.\r
+ ///\r
+ UINT32 PEBS_ARCH_REG:1;\r
+ UINT32 Reserved1:24;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_PERF_CAPABILITIES_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. Fixed-Function-Counter Control Register (R/W).\r
+\r
+ @param ECX MSR_CORE2_PERF_FIXED_CTR_CTRL (0x0000038D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_FIXED_CTR_CTRL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_PERF_FIXED_CTR_CTRL 0x0000038D\r
+\r
+\r
+/**\r
+ Unique. See Table 35-2. See Section 18.4.2, "Global Counter Control\r
+ Facilities.".\r
+\r
+ @param ECX MSR_CORE2_IA32_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS);\r
+ AsmWriteMsr64 (MSR_CORE2_IA32_PERF_GLOBAL_STAUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_IA32_PERF_GLOBAL_STAUS 0x0000038E\r
+\r
+\r
+/**\r
+ Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r
+\r
+ @param ECX MSR_CORE2_PERF_GLOBAL_STAUS (0x0000038E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_STAUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_PERF_GLOBAL_STAUS 0x0000038E\r
+\r
+\r
+/**\r
+ Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r
+\r
+ @param ECX MSR_CORE2_PERF_GLOBAL_CTRL (0x0000038F)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_CTRL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_PERF_GLOBAL_CTRL 0x0000038F\r
+\r
+\r
+/**\r
+ Unique. See Section 18.4.2, "Global Counter Control Facilities.".\r
+\r
+ @param ECX MSR_CORE2_PERF_GLOBAL_OVF_CTRL (0x00000390)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL);\r
+ AsmWriteMsr64 (MSR_CORE2_PERF_GLOBAL_OVF_CTRL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_PERF_GLOBAL_OVF_CTRL 0x00000390\r
+\r
+\r
+/**\r
+ Unique. See Table 35-2. See Section 18.4.4, "Precise Event Based Sampling\r
+ (PEBS).".\r
+\r
+ @param ECX MSR_CORE2_PEBS_ENABLE (0x000003F1)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.\r
+ @param EDX Upper 32-bits of MSR value.\r
+ Described by the type MSR_CORE2_PEBS_ENABLE_REGISTER.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ MSR_CORE2_PEBS_ENABLE_REGISTER Msr;\r
+\r
+ Msr.Uint64 = AsmReadMsr64 (MSR_CORE2_PEBS_ENABLE);\r
+ AsmWriteMsr64 (MSR_CORE2_PEBS_ENABLE, Msr.Uint64);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_PEBS_ENABLE 0x000003F1\r
+\r
+/**\r
+ MSR information returned for MSR index #MSR_CORE2_PEBS_ENABLE\r
+**/\r
+typedef union {\r
+ ///\r
+ /// Individual bit fields\r
+ ///\r
+ struct {\r
+ ///\r
+ /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r
+ ///\r
+ UINT32 Enable:1;\r
+ UINT32 Reserved1:31;\r
+ UINT32 Reserved2:32;\r
+ } Bits;\r
+ ///\r
+ /// All bit fields as a 32-bit value\r
+ ///\r
+ UINT32 Uint32;\r
+ ///\r
+ /// All bit fields as a 64-bit value\r
+ ///\r
+ UINT64 Uint64;\r
+} MSR_CORE2_PEBS_ENABLE_REGISTER;\r
+\r
+\r
+/**\r
+ Unique. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_CORE2_MC4_CTL (0x0000040C)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC4_CTL);\r
+ AsmWriteMsr64 (MSR_CORE2_MC4_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC4_CTL 0x0000040C\r
+\r
+\r
+/**\r
+ Unique. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
+\r
+ @param ECX MSR_CORE2_MC4_STATUS (0x0000040D)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC4_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_MC4_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC4_STATUS 0x0000040D\r
+\r
+\r
+/**\r
+ Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC4_ADDR\r
+ register is either not implemented or contains no address if the ADDRV flag\r
+ in the MSR_MC4_STATUS register is clear. When not implemented in the\r
+ processor, all reads and writes to this MSR will cause a general-protection\r
+ exception.\r
+\r
+ @param ECX MSR_CORE2_MC4_ADDR (0x0000040E)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC4_ADDR);\r
+ AsmWriteMsr64 (MSR_CORE2_MC4_ADDR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC4_ADDR 0x0000040E\r
+\r
+\r
+/**\r
+ See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r
+\r
+ @param ECX MSR_CORE2_MC3_CTL (0x00000410)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC3_CTL);\r
+ AsmWriteMsr64 (MSR_CORE2_MC3_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC3_CTL 0x00000410\r
+\r
+\r
+/**\r
+ See Section 15.3.2.2, "IA32_MCi_STATUS MSRS.".\r
+\r
+ @param ECX MSR_CORE2_MC3_STATUS (0x00000411)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC3_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_MC3_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC3_STATUS 0x00000411\r
+\r
+\r
+/**\r
+ Unique. See Section 15.3.2.3, "IA32_MCi_ADDR MSRs." The MSR_MC3_ADDR\r
+ register is either not implemented or contains no address if the ADDRV flag\r
+ in the MSR_MC3_STATUS register is clear. When not implemented in the\r
+ processor, all reads and writes to this MSR will cause a general-protection\r
+ exception.\r
+\r
+ @param ECX MSR_CORE2_MC3_ADDR (0x00000412)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC3_ADDR);\r
+ AsmWriteMsr64 (MSR_CORE2_MC3_ADDR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC3_ADDR 0x00000412\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE2_MC3_MISC (0x00000413)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC3_MISC);\r
+ AsmWriteMsr64 (MSR_CORE2_MC3_MISC, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC3_MISC 0x00000413\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE2_MC5_CTL (0x00000414)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC5_CTL);\r
+ AsmWriteMsr64 (MSR_CORE2_MC5_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC5_CTL 0x00000414\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE2_MC5_STATUS (0x00000415)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC5_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_MC5_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC5_STATUS 0x00000415\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE2_MC5_ADDR (0x00000416)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC5_ADDR);\r
+ AsmWriteMsr64 (MSR_CORE2_MC5_ADDR, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC5_ADDR 0x00000416\r
+\r
+\r
+/**\r
+ Unique.\r
+\r
+ @param ECX MSR_CORE2_MC5_MISC (0x00000417)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC5_MISC);\r
+ AsmWriteMsr64 (MSR_CORE2_MC5_MISC, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC5_MISC 0x00000417\r
+\r
+\r
+/**\r
+ Unique. Apply to Intel Xeon processor 7400 series (processor signature\r
+ 06_1D) only. See Section 15.3.2.2, "IA32_MCi_STATUS MSRS." and Chapter 23.\r
+\r
+ @param ECX MSR_CORE2_MC6_STATUS (0x00000419)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_MC6_STATUS);\r
+ AsmWriteMsr64 (MSR_CORE2_MC6_STATUS, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_MC6_STATUS 0x00000419\r
+\r
+\r
+/**\r
+ Unique. GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon\r
+ processor 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
+\r
+ @param ECX MSR_CORE2_EMON_L3_CTR_CTLn\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0);\r
+ AsmWriteMsr64 (MSR_CORE2_EMON_L3_CTR_CTL0, Msr);\r
+ @endcode\r
+ @{\r
+**/\r
+#define MSR_CORE2_EMON_L3_CTR_CTL0 0x000107CC\r
+#define MSR_CORE2_EMON_L3_CTR_CTL1 0x000107CD\r
+#define MSR_CORE2_EMON_L3_CTR_CTL2 0x000107CE\r
+#define MSR_CORE2_EMON_L3_CTR_CTL3 0x000107CF\r
+#define MSR_CORE2_EMON_L3_CTR_CTL4 0x000107D0\r
+#define MSR_CORE2_EMON_L3_CTR_CTL5 0x000107D1\r
+#define MSR_CORE2_EMON_L3_CTR_CTL6 0x000107D2\r
+#define MSR_CORE2_EMON_L3_CTR_CTL7 0x000107D3\r
+/// @}\r
+\r
+\r
+/**\r
+ Unique. L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor\r
+ 7400 series (processor signature 06_1D) only. See Section 17.2.2.\r
+\r
+ @param ECX MSR_CORE2_EMON_L3_GL_CTL (0x000107D8)\r
+ @param EAX Lower 32-bits of MSR value.\r
+ @param EDX Upper 32-bits of MSR value.\r
+\r
+ <b>Example usage</b>\r
+ @code\r
+ UINT64 Msr;\r
+\r
+ Msr = AsmReadMsr64 (MSR_CORE2_EMON_L3_GL_CTL);\r
+ AsmWriteMsr64 (MSR_CORE2_EMON_L3_GL_CTL, Msr);\r
+ @endcode\r
+**/\r
+#define MSR_CORE2_EMON_L3_GL_CTL 0x000107D8\r
+\r
+#endif\r
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